KR102064977B1 - Method and Apparatus for Image Filter Processing Based on Field Programmable Gate Array - Google Patents

Abstract

Disclosed are a method for processing an image filter based on a field programmable gate array and a device therefor. According to an embodiment of the present invention, an image filter processing device can comprise: an input image acquisition part for acquiring an input image; a filter setting part for setting an image filter for correcting the input image; a memory part for storing the image data dividing the input image per line in a block memory based on the preset image processing environment information; and an image processing part which sets the image processing environment information based on the filter setting information for the image filter, and acquires the image data divided per line from the block memory to perform image processing based on the image filter. Therefore, the present invention has an effect in which real-time image processing is possible using an internal memory of an FPGA.

Description

Field programmable gate array based image filter processing method and apparatus therefor {Method and Apparatus for Image Filter Processing Based on Field Programmable Gate Array}

The present invention relates to a field programmable gate array based image filter processing method and apparatus therefor.

The contents described in this section merely provide background information on the embodiments of the present invention and do not constitute a prior art.

In general, a method of performing image processing and correction by applying an image filter to an image is used in various business fields.

When a filter for image processing is implemented using a field programmable gate array (hereinafter referred to as an FPGA), when the size of the image filter becomes large, the available memory becomes insufficient and the FPGA for image processing The implementation of the device becomes difficult. When the FPGA device is implemented for real-time image processing, more memory capacity is required. For example, in the case of the Artix-7 series FPGA, the block memory size is 1.625 Mbytes. Therefore, if the filter size is 10 * 10, the design cannot be possible.

1 is an exemplary view showing an FPGA-based image filter processing operation according to the prior art.

Referring to FIG. 1, a conventional image filter processing apparatus performs image processing using a block memory equal to the number of image filters. Hereinafter, a conventional image filter processing apparatus that performs a 3 * 3 image filter operation will be described as an example.

In FIG. 1A, a conventional image filter processing apparatus includes an image filter that determines pixel values at positions 6 using pixel values at positions 1, 2, 3, 5, 7, 9, 10, and 11. use.

In FIG. 1 (b), the conventional image filter processing apparatus delays an input image by three lines using a block memory and simultaneously delays three clocks per line for real time operation. Allows you to calculate the pixel values at positions 2, 3, 5, 7, 9, 10, and 11.

When performing image processing as in the conventional image filter processing apparatus, an FPGA having a small internal memory is used, or when the image filter size is large, the internal memory is insufficient to design. In addition, the conventional image filter processing apparatus may not perform real-time image processing unless the number of block memories is as large as the size of the image filter, and there is a problem in that gaps between pixels of the output image are generated. In addition, the conventional image filter processing apparatus has a problem in that the board design is limited when the external memory is used due to insufficient internal memory.

The present invention sets image processing environment information according to an input image and an image filter, stores image data obtained by dividing an input image for each line based on the image processing environment information in each of at least one block memory, and stores the block memory. A main object of the present invention is to provide a gate array-based image filter processing method and an apparatus therefor, which are field-programmable to obtain image data divided by lines from each other and sequentially perform image filter-based image processing.

According to an aspect of the present invention, an image filter processing apparatus for achieving the above object, the input image acquisition unit for obtaining an input image; A filter setting unit configured to set an image filter for correcting the input image; A memory unit for storing image data obtained by dividing the input image into lines based on preset image processing environment information in a block memory; And an image processor configured to set the image processing environment information based on filter setting information on the image filter, and obtain image data divided by the lines from the block memory to perform the image filter based image processing. Can be.

In addition, according to another aspect of the present invention, an image filter processing method for achieving the above object, the step of obtaining an input image; Setting an image filter to correct the input image; Setting image processing environment information on a storage environment of a block memory and a filter processing environment of a first-in-first-out queue based on filter setting information on the image filter; Storing image data obtained by dividing the input image into lines based on preset image processing environment information in at least one block memory; And performing image processing based on the image filter by acquiring image data divided for each line from the at least one block memory into the first-in, first-out queue.

As described above, the present invention has the effect of processing a plurality of image processing using the image filter using a minimum internal memory of the FPGA.

In addition, the present invention has the effect that real-time image processing is possible using the internal memory of the FPGA.

In addition, the present invention has the effect that the image processing using the internal memory, even if the FPGA using a small internal memory or the size of the image filter is large.

In addition, the present invention has the effect of reducing the constraints on the board design of the FPGA by performing the image processing using only the internal memory without using an external memory.

1 is an exemplary view showing an FPGA-based image filter processing operation according to the prior art.
2 is a block diagram schematically illustrating an FPGA-based image filter processing apparatus according to an exemplary embodiment of the present invention.
3 is a block diagram schematically illustrating an image processor included in an image filter processing apparatus according to an exemplary embodiment of the present invention.
4 is a flowchart illustrating an FPGA-based image filter processing method according to an embodiment of the present invention.
5A and 5B are exemplary diagrams for describing an image processing environment setting for image filter processing according to an exemplary embodiment of the present invention.
6 is an exemplary diagram for describing an image filter processing operation according to an exemplary embodiment of the present invention.
7 is a block diagram schematically illustrating an FPGA device for image filter processing according to another exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the following will describe a preferred embodiment of the present invention, but the technical idea of the present invention is not limited thereto and may be variously modified and modified by those skilled in the art. Hereinafter, a field programmable gate array-based image filter processing method and apparatus therefor proposed by the present invention will be described in detail with reference to the drawings.

A method and apparatus for performing image filter processing using a limited internal memory in a field programmable gate array device (hereinafter, referred to as an FPGA) are described, but are not necessarily limited thereto. It can be applied to various image processing fields.

2 is a block diagram schematically illustrating an FPGA-based image filter processing apparatus according to an exemplary embodiment of the present invention.

The image filter processing apparatus 200 according to the present exemplary embodiment includes an input image acquisition unit 210, a filter setting unit 220, an image processing unit 230, and a memory unit 240. The image filter processing apparatus 200 of FIG. 2 is according to an exemplary embodiment, and not all blocks illustrated in FIG. 2 are essential components. In another embodiment, some blocks included in the image filter processing apparatus 200 are added. , Can be changed or deleted.

The input image acquisition unit 210 acquires an input image photographed from an image photographing apparatus (not shown). Here, the input image means an image having a preset size. For example, an image having a size such as 640 * 480 may be obtained.

The input image acquisition unit 210 may directly obtain an input image from an image photographing apparatus (not shown), but is not limited thereto. The input image acquisition unit 210 may also obtain an input image from an external server (storage) in which the photographed image is stored. .

The filter setting unit 220 sets an image filter for correcting the input image.

The filter setting unit 220 according to the present exemplary embodiment sets the filter setting information on the size, the correction method, and the like of the image filter so as to correct the pixels in the input image while moving in the window sliding method.

The filter setting unit 220 may set filter setting information for an image filter having an n * n form (n is a natural number of 3 or more). For example, the filter setting unit 220 may set an image filter having a square window shape such as 3 * 3, 5 * 5, 10 * 10, 30 * 30, and the like.

In addition, the filter setting unit 220 may set the filter setting information for the image filter by correcting the value of the pixel located in the center of the image filter by using the sum of the pixel values of the image filters. For example, when performing image processing using a 3 * 3 image filter on a 4 * 5 size input image, the filter setting unit 220 may perform 1, 2, 3, 5, 7, 9, 10 of the input image. The image filter may be configured by determining the pixel value at the 6th position (the center of the image filter) by using the sum of the pixel values at the 11th position.

The image processor 230 sets image processing environment information based on the image filter, acquires image data stored in the block memory according to the image processing environment information, and performs image filter based image processing.

The image processor 230 sets image processing environment information based on filter setting information (image filter size, correction method, etc.) for the image filter. In detail, the image processor 230 sets image processing environment information on the storage environment of the block memory and the filter processing environment of the first-in, first-out queue.

The image processor 230 sets the block memory storage environment for the number of block memories for storing the image data divided for each line and the size of each of the block memories based on the filter setting information. Also, the image processor 230 filters the number of first in first out queues and the size of the first in first out queue to process the filter operation of the image data based on the filter setting information for the image filter. Set up the environment.

In addition, the image processor 230 processes the filter operation by applying the image filter to the image data sequentially by reading the image data stored in the block memory divided by the lie of the input image according to the image processing environment information and sequentially.

The image processor 230 acquires image data of different lines from each of the at least one block memory as a first-in first-out queue, and sequentially applies image filters to the image data stored in the first-in first-out queue to process a filter operation.

After at least three lines of image data are stored in the at least one block memory, the image processor 230 loads the image data stored in the block memory into the first-in, first-out queue.

The image processor 230 corrects the pixel value of the image data located at the center of the image filter by using the sum of the pixel values of the image filters.

The memory unit 240 stores the image data of the input image in at least one block memory determined based on the image processing environment information.

The memory unit 240 stores image data obtained by dividing an input image by lines into a block memory. Here, the memory unit 240 stores image data for different lines of the input image in each of the at least one block memory. For example, when four block memories are used, such as the first block memory to the fourth block memory based on the image processing environment information, the memory unit 240 stores the first line image data of the input image in the first block memory. The second line image data of the input image is stored in the second block memory. In addition, the memory unit 240 stores the third line image data of the input image in the third block memory, and the fourth line image data of the input image in the fourth block memory.

3 is a block diagram schematically illustrating an image processor included in an image filter processing apparatus according to an exemplary embodiment of the present invention.

The image processor 230 included in the image filter processing apparatus 200 according to the present exemplary embodiment may include a block memory environment setting unit 310, a first-in, first-out environment setting unit 320, an image filter processing unit 330, and an image output unit ( 340). Here, the block memory environment setting unit 310 and the first-in, first-out environment setting unit 320 are described as separate modules, but are not necessarily limited thereto. For the storage environment of the block memory and the filter processing environment of the first-in, first-out queue, It may be implemented as one module such as an image processing environment setting unit for setting image processing environment information.

The block memory environment setting unit 310 sets the block memory storage environment based on the filter setting information for the input image and the image filter.

The block memory environment setting unit 310 stores the number of block memories and the block memories for storing the image data divided for each line of the input image based on filter setting information (image filter size, correction method, etc.) for the image filter. Set the block memory storage environment for the size of. Here, the block memory may be a block random access memory (BRAM), but is not necessarily limited thereto.

The block memory environment setting unit 310 sets a value obtained by adding 1 to the number of filter lines in the filter setting information as the number of block memories (the number of BRAMs). In addition, the block memory environment setting unit 310 may set the size of the block memory to be equal to the number of pixels included in one line of the input image. For example, when performing image processing using a 3 * 3 image filter on an input image having a size of 4 * 5, the block memory environment setting unit 310 adds 1 to the number of filter lines 3 and adds 4 to the number of block memories. The size of the block memory may be set to 4, the same as 4, which is the number of pixels included in one line of the input image.

The first-in, first-out environment setting unit 320 sets the filter processing environment of the first in first out queue for processing the filter operation of the image data based on the filter setting information for the image filter.

The first-in, first-out environment setting unit 320 sets the filter processing environment for the number of the first-in, first-out queue and the size of the first-in, first-out queue based on the filter setting information.

The first-in, first-out environment setting unit 320 sets the number of the first-in, first-out queues to be equal to the size of the image filter of the filter setting information. In addition, the first-in, first-out environment setting unit 320 may set the size of the first-in, first-out queue in the same manner as the number of filter lines in the filter setting information. For example, when image processing is performed using a 3 * 3 image filter on an input image having a size of 4 * 5, the first-in, first-out environment setting unit 320 may preempt the same as 3 * 3 = 9, which is the size of the image filter. The number of the first-in, first-out queues may be set to 9, and the size of the first-in, first-out queues may be set to three, similar to the number of three filter lines.

The image filter processor 330 acquires image data for different lines from each of the at least one block memory as a first-in first-out queue, and processes the filter operation by applying image filters to the image data sequentially according to the first-in first-out processing method.

After at least three lines of image data are stored in at least one block memory, the image filter processor 330 loads the image data stored in the block memory into a first-in, first-out queue and processes the filter operation.

The image output unit 340 outputs a corrected image according to the result of the filter operation. The image output unit 340 outputs the corrected image in line order of the input image according to the filter operation according to the first-in, first-out queue.

4 is a flowchart illustrating an FPGA-based image filter processing method according to an embodiment of the present invention.

The image filter processing apparatus 200 obtains an input image (S410). Here, the input image is an image captured by an image photographing apparatus (not shown), and means an image of a preset size. The image filter processing apparatus 200 may directly obtain an input image from an image photographing apparatus (not shown), but is not limited thereto. The image filter processing apparatus 200 may also obtain an input image from an external server (storage) in which the photographed image is stored. .

The image filter processing apparatus 200 sets filter setting information of an image filter for correcting an input image, and sets image processing environment information based on the image filter (S420).

The image filter processing apparatus 200 sets filter setting information about the size of the image filter, a correction method, and the like so that the pixels in the input image may be corrected while moving in a window sliding manner. The image filter processing apparatus 200 may set filter setting information for an image filter having an n * n form (n is a natural number of 3 or more). For example, the filter setting unit 220 may set an image filter having a square window shape such as 3 * 3, 5 * 5, 10 * 10, 30 * 30, and the like.

In addition, the image filter processing apparatus 200 may generate image processing environment information of the storage environment of the block memory and the filter processing environment of the first-in, first-out queue based on the filter setting information (the size of the image filter, the correction method, etc.) of the image filter. Set it.

The image filter processing apparatus 200 sets the block memory storage environment for the number of block memories for storing the image data divided for each line of the input image and the size of each of the block memories based on the filter setting information. The image filter processing apparatus 200 sets the filter processing environment for the number of the first-in first-out queue and the size of the first-in first-out queue based on the filter setting information.

The image filter processing apparatus 200 stores the image data for the input image in at least one block memory determined based on the image processing environment information (S430). The image filter processing apparatus 200 stores image data obtained by dividing an input image for each line in a block memory. Here, the image filter processing apparatus 200 stores image data for different lines of the input image in each of the at least one block memory.

The image filter processing apparatus 200 reads image data stored in the block memory into the first-in, first-out queue (S440). In other words, the image filter processing apparatus 200 acquires image data for different lines from each of the at least one block memory as a first-in first-out queue to perform image processing. Here, the image filter processing apparatus 200 performs an operation of loading the image data stored in the block memory into the first-in first-out queue after at least three lines of the image data are stored in the at least one block memory.

The image filter processing apparatus 200 processes the filter operation by sequentially applying image filters to the image data stored in the first-in, first-out queue (S450). The image filter processing apparatus 200 corrects the pixel value of the image data located at the center of the image filter by using the sum of the pixel values of the pixel values in the image filter.

The image filter processing apparatus 200 outputs a corrected image according to the result of the filter operation (S460). The image filter processing apparatus 200 outputs a corrected image in line order of the input image according to a filter operation according to a first-in, first-out queue. The image filter processing apparatus 200 repeatedly performs a filter operation until all image data of the input image is processed and outputs a corrected image.

In FIG. 4, the steps are described as being sequentially executed, but are not necessarily limited thereto. In other words, since the steps described in FIG. 4 may be applied by changing the steps or executing one or more steps in parallel, FIG. 4 is not limited to the time series order.

The FPGA-based image filter processing method according to the present embodiment described in FIG. 4 may be implemented as an application (or a program) and recorded on a recording medium that may be read by a terminal device (or a computer). An application (or program) for implementing an FPGA-based image filter processing method according to the present embodiment is recorded and a recording medium readable by a terminal device (or computer) may be any type of data that can be read by a computing system. Recording device or medium.

5A and 5B are exemplary diagrams for describing an image processing environment setting for image filter processing according to an exemplary embodiment of the present invention.

Unlike image processing using block memory itself as a buffer in a conventional FPGA, the FPGA-based image filter processing apparatus 200 according to the present invention performs image processing using a block memory and a first-in, first-out queue. .

The image filter processing apparatus 200 stores the input input image in a different block memory for each line. The required number of block memories may be set differently according to the size of the image filter. For example, four block memories are required for a 3 * 3 image filter, and six block memories are required for a 5 * 5 image filter.

In addition, the image filter processing apparatus 200 sequentially loads image data stored in the block memory into a first-in first-out queue to perform a filter operation.

5A and 5B are exemplary diagrams illustrating that image filter processing is performed by applying a 3 * 3 image filter.

In FIG. 5A (a), the image filter processing apparatus 200 classifies image data for each line of the input image.

In FIG. 5A (b), the image filter processing apparatus 200 stores each line of image data of the input image in each of four different block memories. Here, the size of the block memory (BRAM size) is preferably set so as to delay an image as many as one line of the input image. In addition, the number of block memories (the number of BRAMs) may be set to a value obtained by adding 1 to the number of lines of the image filter.

In FIG. 5B (a), the image filter processing apparatus 200 performs an operation of reading image data stored in the block memory into a first-in, first-out queue. The image filter processing apparatus 200 loads the image data stored in the block memory into the first-in, first-out queue after at least three lines of the image data are stored in the at least one block memory.

Here, the size of the first-in, first-out queue (FIFO size) may be set equal to the number of lines of the image filter, or may be set to be equal to or greater than the minimum number of filter lines of the image filter. In addition, the number of first-in, first-out queues (FIFOs) may be set equal to the size of the image filter.

In FIG. 5B (b), the image filter processing apparatus 200 processes a filter operation by applying an image filter to image data sequentially output from a first-in first-out queue according to a first-in first-out process method, and according to the result of the filter operation. Output the corrected image.

6 is an exemplary diagram for describing an image filter processing operation according to an exemplary embodiment of the present invention.

In FIG. 6, an image filter processing operation of the image filter processing apparatus 200 will be described on the assumption that an input image of 4 * 5 size and an image filter of 3 * 3 size are used.

The image filter processing apparatus 200 receives an input image having a size of 4 * 5 as shown in FIG. 6A, and performs the image processing using the 3 * 3 filter as shown in FIG. 6B. At this time, the positions of the pixels to be processed are 6 and 15. The image filter processing method of the image filter processing apparatus 200 determines the pixel value at 6 positions by using the sum of the values at positions 1, 2, 3, 5, 7, 9, 10, 11, and 10, 11 The pixel value at position 15 is determined using the sum of the values at positions 12, 14, 16, 18, 19, and 20.

As shown in FIG. 6C, each block of the input image is stored in the block memory BRAM. Here, the size of the block memory is 4, and in the case of the first block memory 610, a value when the image data (1 to 4) of the first line is input and maintained while the image data (17 to 20) of the fifth line is input. Will change. The other block memories BRAM2 to 4 also hold the stored image data until the next data comes in.

When you want to process the pixel at the 1 or 2 position of the input image, only 2 lines of the input image are operated. Therefore, after 2 lines are stored in the block memory, the image data stored in the block memory is sequentially read from the first-in first-out queue. Calculate with

When the pixels at positions 5 or 6 of the input image are to be processed, the image filter processing apparatus 200 may store up to 3 lines in the block memory and read image data necessary for filter calculation into a first-in, first-out queue. At this time, the video data in the block memory is maintained while 3 lines of video are inputted, so it can be repeatedly read and used in the first-in, first-out queue. Here, the size of the first-in, first-out queue is three, and the section in which the image data necessary for the operation is to be maintained is three spaces of the first-in, first-out queue.

After maintaining three lines in the block memory, the image filter processing apparatus 200 receives the next data in order. Since the image filter processing apparatus 200 uses the first-in, first-out processing method, when the image data is input, the first-in first-out image data is pushed out, so the size of the first-in first-out queue is set to at least three.

When the first line data of the input image enters and is stored in the first block memory 610, the second, third, and fourth line data are maintained while the first line data is input, and when the fifth line data is input, new data is stored in the first block memory 610. ) Will be stored. Accordingly, the image of 3 lines is maintained in the block memory while being input.

In (c) of FIG. 6, when the image output is 6, it is confirmed that the pixels required to process the values in the first-in, first-out queues 1 to 9 are 1, 2, 3, 5, 7, 9, 10, 11, and the image When the output is 15, the necessary pixels are 10, 11, 12, 14, 16, 18, 19, and 20.

The image filter processing apparatus 200 outputs a pixel that does not require image processing as it is, and outputs a pixel that requires processing by applying an image filter to the corresponding data and outputting the processed image. However, since the gap between pixels does not occur, real-time processing is possible.

When a new image is input to the block memory and the first-in, first-out queue, the image filter processing apparatus 200 sequentially stores the image data and repeatedly performs the image filter process until the operation of all the images is completed.

In the image filter processing apparatus 200 according to the present invention, even if an FPGA having a small internal memory is used or the size of the image filter is large, the required memory is not large so that image processing may be performed using the internal memory. Table 1 compares the required memory size of the prior art and the required memory size according to the size of the image filter.

In addition, the image filter processing apparatus 200 is capable of real-time image processing using the image filter, by performing the image processing using only the internal memory without using an external memory, there is an advantage that the restrictions in the design of the board disappears.

7 is a block diagram schematically illustrating an FPGA device for image filter processing according to another exemplary embodiment of the present invention.

The FPGA device 700 for image filter processing includes an input module 710, a processor 720, a memory 730, and an output module 740.

The input module 710 acquires an input image from an external device or a server. Here, the input image is an image captured by an image photographing apparatus (not shown), and means an image of a preset size.

Processor 720 controls the overall operation of FPGA device 700.

The processor 720 sets filter setting information of an image filter for correcting an input image, and sets image processing environment information based on the image filter.

The processor 720 sets filter setting information on the size of the image filter, a correction method, and the like so that the pixels in the input image can be corrected while moving in a window sliding manner. The processor 720 may set filter setting information for an image filter having an n * n form (n is a natural number of 3 or more). For example, the filter setting unit 220 may set an image filter having a square window shape such as 3 * 3, 5 * 5, 10 * 10, 30 * 30, and the like.

In addition, the processor 720 sets image processing environment information on the storage environment of the block memory and the filter processing environment of the first-in, first-out queue based on the filter setting information (image filter size, correction method, etc.) for the image filter.

The processor 720 sets the block memory storage environment for the number of block memories for storing the divided image data for each line of the input image and the size of each of the block memories based on the filter setting information. The processor 720 sets the filter processing environment for the number of the first-in, first-out queue and the size of the first-in, first-out queue based on the filter setting information.

The processor 720 reads image data stored in the block memory of the memory 730 into the first-in, first-out queue. In other words, the processor 720 acquires image data for different lines from each of the at least one block memory of the memory 730 as a first-in first-out queue to perform image processing. Here, the processor 720 performs an operation of loading the image data stored in the block memory into the first-in, first-out queue after at least three lines of the image data are stored in the at least one block memory of the memory 730.

The processor 720 processes the filter operation by sequentially applying image filters to the image data stored in the first-in, first-out queue. The processor 720 corrects the pixel value of the image data located at the center of the image filter by using the pixel sum value obtained by adding the pixel values in the image filter.

The memory 730 is a block memory preset in the FPGA device 700, and stores and manages various data. Here, the block memory may be a BRAM, and the number of block memories may be changed under the control of the processor 720.

The memory 730 stores image data of an input image in at least one block memory determined based on image processing environment information. The memory 730 stores image data obtained by dividing an input image by lines into a block memory. The memory 730 stores image data for different lines of the input image in each of the at least one block memory.

The output module 740 outputs a corrected image according to the result of the filter operation. The output module 740 outputs the corrected image in line order of the input image according to a filter operation according to the first-in, first-out queue. Here, the output module 740 may be a module for transmitting a corrected image to an external display device, but is not necessarily limited thereto and may be implemented as a module for directly displaying a corrected image.

The operation and function of the FPGA device for image filter processing according to the present embodiment described in FIG. 7 may be implemented in an application (or a program) and recorded on a recording medium readable by a terminal device (or a computer). An application (or program) for implementing an operation and a function of an FPGA device for image filter processing according to the present embodiment is recorded, and a recording medium readable by a terminal device (or computer) includes data that can be read by a computing system. It includes all kinds of recording devices or media to be stored.

The above description is merely illustrative of the technical spirit of the embodiments of the present invention, and those skilled in the art to which the embodiments of the present invention pertain various modifications and modifications without departing from the essential characteristics of the embodiments of the present invention. Modifications may be possible. Therefore, the embodiments of the present invention are not intended to limit the technical spirit of the embodiments of the present invention, but to describe, and the scope of the technical spirit of the embodiments of the present invention is not limited by these embodiments. The protection scope of the embodiments of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the embodiments of the present invention.

200: image filter processing device
210: input image acquisition unit 220: filter setting unit
230: image processing unit 240: memory unit
310: block memory environment setting unit 320: first-in, first-out environment setting unit
330: Image filter processing unit 340: Image output unit

Claims (12)

An apparatus for processing a field programmable gate array based image filter,
An input image obtaining unit obtaining an input image;
A filter setting unit configured to set an image filter for correcting the input image;
A memory unit for storing image data obtained by dividing the input image into lines based on preset image processing environment information in a block memory; And
And an image processor configured to set the image processing environment information based on filter setting information for the image filter, and obtain the image data divided by the line from the block memory to perform the image filter based image processing.
The memory unit stores the image data in at least one block memory determined based on the image processing environment information, and stores image data for different lines in each of the at least one block memory.
The image processing unit may include an image processing environment setting unit configured to determine the image processing environment information regarding a storage environment of the block memory and a filter processing environment of a first-in, first-out queue; An image filter processor configured to acquire image data for the different lines from the at least one block memory as the first-in first-out queue, and apply the image filter to the image data sequentially according to a first-in first-out process to process a filter operation. ; And an image output unit configured to output a corrected image according to a result of the filter operation. delete delete The method of claim 1,
The image processing environment setting unit,
A block memory environment setting unit configured to set the storage environment for the number of the block memories for storing the image data divided for each line and the size of each of the block memories based on the set image filter; And
A first-in, first-out environment setting unit that sets the filter processing environment for the number of the first-in first-out queue and the size of the first-in first-out queue based on the set image filter.
Image filter processing apparatus comprising a. The method of claim 4, wherein
The block memory environment setting unit,
The number of filter lines of the filter setting information plus 1 is set to the number of the block memories, and the size of the block memory is set to be equal to the number of pixels included in one line of the input image. Image filter processing unit. The method of claim 4, wherein
The first-in, first-out environment setting unit,
The number of the first-in, first-out queue is set equal to the size of the image filter of the filter setting information, and the image is set to the size of the first-in, first-out queue equal to the number of filter lines of the filter setting information. Filter processing unit. The method of claim 1,
The image filter processor,
And after the at least three lines are stored in the at least one block memory, the image data stored in the block memory is loaded into a first-in first-out queue to process the filter operation. The method of claim 1,
The filter setting unit,
Set the size of the image filter of the form n * n (n is a natural number of 3 or more),
And the image filter for correcting a value of a pixel located at the center of the image filter by using a pixel sum value obtained by adding pixel values in the filter. A method of processing a field programmable gate array based image filter,
Obtaining an input image;
Setting an image filter to correct the input image;
Setting image processing environment information of a storage environment of a block memory and a filter processing environment of a first-in, first-out queue based on filter setting information of the image filter;
Storing image data obtained by dividing the input image into lines based on preset image processing environment information in at least one block memory; And
And acquiring the image data divided by the lines from the at least one block memory into the first-in, first-out queue to perform the image filter based image processing.
The storing of the at least one block memory may include storing image data for different lines in each of the at least one block memory,
The performing of the image processing may include obtaining image data for the different lines as the first-in first-out queue, and sequentially applying the image filter to the image data according to a first-in first-out process to process a filter operation. And after the two lines are stored in the block memory, the image data stored in the block memory is loaded into a first-in, first-out queue to process the filter operation. delete delete A computer program stored in a medium for causing a computer to execute the image filter processing method according to claim 9.

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