JPS63244667A - Manufacture of bipolar integrated circuit - Google Patents

Abstract

PURPOSE:To make the breakdown voltage of element isolation and the breakdown voltage between the emitter and the collector of a vertical type PNP transistor sufficiently high, by etching a P-type semiconductor substrate of a region serving as the collector of the vertical type PNP transistor before the formation of an N-type epitaxial layer. CONSTITUTION:A first N-type impurity diffusion layer 3 is formed in a region on a P-type semiconductor substrate 1 where a vertical type PNP transistor is formed, and a first P-type impurity diffusion layers 5,5' are formed in an isolation region from the other element neighboring with the vertical type PNP transistor and in a prescribed region on the first N-type impurity diffusion layer 3. Before an N-type epitaxial layer 6 is formed on the P-type semiconductor substrate 1, a part of the first P-type impurity diffusion layers 5, 5' formed on the P-type semiconductor substrate 1 is subjected to etching. Thereby, the first P-type impurity diffusion layers 5, 5' are restrained from diffusing into the N-type epitaxial layer 6, and so a sufficient base width of the vertical type PNP transistor can be maintained. As the result, the breakdown voltage between the emitter and the collector or the vertical type PNP transistor can be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing bipolar integrated circuits, and in particular to a method for manufacturing bipolar integrated circuits, in which vertical P integrated circuits are manufactured on the same semiconductor substrate while being isolated from other devices in PN.
The present invention relates to a method of forming an NP transistor.

[Prior Art] Figs. 2A to 2-2 are cross-sectional views showing each step of a conventional bipolar IC manufacturing method. Below, these Figures 2A~
A conventional method of manufacturing a bipolar IC will be explained with reference to FIG.

FIG. 2A First, a first oxide film 2 is formed on the surface of a P-type silicon substrate 1 by oxidation treatment, and this is patterned using photolithography. Next, using the buttered first oxide 112 as a mask, N of antimony, arsenic, phosphorus, etc.
A type impurity is introduced into a P-type silicon substrate 1 using an ion implantation method or a diffusion method.

FIG. 2B heat-treats the P-type silicon substrate 1 into which Nl impurities are introduced,
The N-type impurity is activated to form the N-type buried diffusion layer 3. At the same time, a second oxide film P is formed on the N'l buried diffusion layer 3 of the P-type silicon substrate 1. Next, this second oxidation l! Using the patterned second oxide 114 as a mask, a P-type impurity such as boron is introduced into the P-type silicon substrate 1 using ion implantation or diffusion.

FIG. 2C heat-treats the P-type silicon substrate 1 into which P-type impurities have been introduced,
By activating the P-type impurity and utilizing the difference in diffusion constant, P-type buried isolation layers 5 and 5' are formed on the N-type buried diffusion layer 3.
(These layers will become the collector and element isolation diffusion layer of a vertical PNP transistor in the future), and remove the oxide film 4 on the P-type silicon substrate 1 by wet etching.
An N-type silicon epitaxial layer 6 is formed. Next 1.
NP! l! A third oxide film 7 is formed on the silicon epitaxial layer 6 by layering theory, and this is buttered using photolithography, and using this buttered third oxide 117 as a mask, phosphorus, arsenic, etc. An N-type impurity is introduced onto the N-type silicon epitaxial layer 6 by ion implantation or the like.

FIG. 2D Next, heat treatment is performed to form the fourth oxide W49,
The N-type impurity is activated and the N-well layer 8 (this layer is a vertical type P
NPI - forms part of the base of the transistor). Next, the fourth oxide film 9 is buttered by photolithography, and using the patterned fourth oxide iI 9 as a mask, a P-type impurity such as boron is diffused onto the surface of the N-type silicon epitaxial layer 6. to be introduced.

FIG. 2E Heat treatment is performed on the P-type silicon substrate 1 in which P-type impurities are introduced into the N-type silicon epitaxial layer 6, and a fifth oxide film 1 is formed.
1, activates the P-type impurity, diffuses the P-type upper separation layer 10, 10' to reach the P-type buried layer 1l11 layer 5, 5', and forms the P-type buried separation layer 5'. and P-type upward separation m
Element isolation is performed at 1o'.

Figure 2F Next, the fifth oxidation! 111 is patterned by photolithography, and using the patterned fifth oxide film 11 as a mask, a P-type impurity such as boron is introduced onto the N-type silicon epitaxial layer W6 by ion implantation or the like.

FIG. 2G: Further, heat treatment is performed to form the sixth oxide film 13 into N-type silicon epitaxial W! Activating the P-type impurity while forming the P-type emitter layer 12 (this layer is a vertical PNP).
)--which will serve as the emitter of the transistor) and a P-type base layer 12' (which will serve as the base of the NPN transistor). Then, the sixth oxide film 13 is buttered by photolithography, and using the patterned sixth oxide film 13 as a mask, an N-type impurity such as arsenic is implanted onto the N-type silicon epitaxial layer 6 by ion implantation or the like. to be introduced.

Figure 2H Heat treatment is applied to this to activate the N-type impurity, resulting in an N-type base layer 14 (this layer becomes the base of the vertical PNP transistor) and an N-type emitter 1114' (this layer becomes the emitter of the NPN transistor). ) and N type collector F1
14" (this layer becomes the collector of the NPN transistor). Furthermore, several moi layers are formed on the sixth oxide film 13.
PSG containing % phosphorus (Phospho 5ll
A surface protection 11115 such as lcate Glass) is formed.

FIG. 2I Sixth oxide film 13 and surface protection layer 11 on each impurity diffusion layer
Contact holes are formed at 115, metal wiring 16 is formed, and final protection 1117 is formed on the surface.

[Problems to be Solved by the Invention] Conventional semiconductor devices are manufactured using the steps described above, so in order to increase the element isolation breakdown voltage, the P-type buried isolation layer 5.5' is placed above the P-type. If the separation layer reaches 10°10' too much, the base width of the vertical PNP transistor (portion a in Figure 2) becomes small, and the emitter-collector breakdown voltage of the vertical PNP transistor becomes small, or in the worst case, In this case, there were problems such as the inability to operate as a PNP transistor.

This invention was made in order to solve the above-mentioned problems, and the element isolation withstand voltage can be made sufficiently high.
It is an object of the present invention to provide a method for manufacturing a bipolar IC in which a vertical PNP transistor has a high emitter-collector voltage.

[Means for Solving the Problems] A method for manufacturing a bipolar integrated circuit according to the present invention includes first forming a first N-type impurity diffusion layer on a P-type semiconductor substrate in a region where a vertical PNP transistor is to be formed. do.

Next, on the P-type semiconductor substrate, a first P-type impurity diffusion layer is formed in a region separating the vertical PNP transistor from other adjacent elements and in a predetermined region on the first N-type impurity diffusion layer. .

Next, a first P layer is formed on the first N-type impurity diffusion layer.
A portion of the type impurity diffusion layer is removed by etching.

Next, PgJ! An N-type epitaxial layer with a flat surface is formed over the entire surface of a semiconductor substrate.

Next, in the N-type epitaxial layer, a second layer is etched at a position opposite to the etched portion of the first P-type impurity diffusion layer.
An N-type impurity layer is formed.

Next, in the N-type epitaxial layer, an upper region of the first P-type impurity diffusion layer formed in a region separating the vertical PNP transistor from other adjacent elements and on the first N-type impurity diffusion layer are formed. A second P-type impurity diffusion layer is formed in the upper region of the unetched portion of the first P-type impurity diffusion layer to a depth that reaches the first P-type impurity diffusion layer.

Next, in the N-type epitaxial layer, a third P-type impurity layer is formed within the second N-type impurity diffusion layer.

Finally, in the N-type epitaxial layer, a third N-type impurity diffusion layer is formed at a position other than the third P-type impurity layer within the second N-type impurity diffusion layer.

[Effect]

In this invention, before forming an N-type epitaxial layer on a P-type semiconductor substrate, a first P-type impurity diffusion layer (which will form the collector of a vertical PNP transistor in the future) is formed on a P-type semiconductor substrate. ), this first P-type impurity diffusion layer is suppressed from diffusing into the N-type epitaxial layer, thereby forming a vertical P-type impurity layer.
A sufficient base width of the NP transistor is ensured, and as a result, the emitter-collector breakdown voltage of the vertical PNP transistor is improved.

[Example] FIGS. 1A to 1H are cross-sectional views showing steps for manufacturing a bipolar IC according to an example of the present invention. Hereinafter, a method for manufacturing a bipolar IC according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1H.

FIG. 1A A first oxide 11!2 is formed on the surface of a P-type silicon substrate 1 by oxidation treatment, and this is buttered using photolithography, and this buttered first oxide 12 is used as a mask. , antimony, or other N-type impurities are introduced into the P-type silicon substrate 1 by a diffusion method or the like.

FIG. 1B heat-treats the P-type silicon substrate 1 into which N-type impurities have been introduced,
At the same time as forming the second oxidized WIA 4, the N-type impurity is activated to form the N-type buried diffusion layer 3. Next, the second oxide 114 is buttered using photolithography, and using the patterned second oxide 114 as a mask, a P-type impurity such as boron is added using an ion implantation method or a diffusion method. A mold silicon substrate 1 is introduced.

Figure 1C P'! The P-type silicon substrate 1 into which impurities have been introduced is heat-treated to activate the P-type impurities, form a P-type layer separation layer 5.5', and remove the oxide film on the surface.

FIG. 1D Next, the P-type silicon substrate 1 (that is, a part of the P-type buried isolation layer 5) in the region that will become the collector of the vertical PNP transistor is etched to form the buried collector 1150 of the vertical PNP transistor. As the etching method at this time, either wet etching or dry etching may be used, and furthermore, either isotropic or anisotropic etching may be used.

FIG. 1E: On the P-type silicon substrate 1 on which each buried diffusion layer is formed, an N-type silylon epitaxial layer H6 is formed so that the surface is flat (for example, formed using an etch-back method). A third oxide film 7 is formed on the silicon epitaxial layer 6 by oxidation treatment. At this time, Plj:
! N-type silicon epitaxial layer 116 of buried valve 11115' and vertical PNP transistor buried collector layer 50
However, since the P-type impurity mjf on the surface of the etched portion of the vertical PNP transistor buried collector layer 50 is lower than that of other portions, the diffusion in the vertical PNP transistor buried collector layer 1150 N-type silicon epitaxial WJ6 in the etched part
The spread to PPJ! This can be more suppressed than the diffusion of the buried isolation layer 5'. Next, the third oxidation 117 on the surface is buttered using photolithography, and using this buttered third oxidation 1117 as a mask, N such as phosphorus is removed.
Type impurities are introduced into the N-type silicon epitaxial layer 6 by ion implantation or the like.

FIG. 1F Next, heat treatment is performed to form a fourth oxide film 9 while activating the N-type impurity, forming an N-well layer 8 (this layer is a vertical PNP).
(forms part of the base of the transistor). Next, the fourth oxide film 9 is patterned using photolithography, and using the patterned fourth oxide film 9 as a mask, P-type impurities such as boron are introduced into the surface of the N-type epitaxial layer 6. .

Figure 1G heat-treats this to form a fifth oxide 1111 on the surface and activates the P-type impurity to form P-type upper isolation layers io, io.
'P-type embedded separation! 115' and vertical PNP transistor buried collector l150;
Element isolation is performed by the type buried isolation layer 5' and the upper P type 11 layer 10'.

Figure 1H ゛Then, in the same manner as in Figures 2F to 2■,
Type emitter layer 12. P-type base layer 12'.

6th (7) ml 3. N-type' (-S 1114.N-type emitter layer 14', N-type collector layer 14'', surface protection 1
1 Wi 5. Metal arrangement Jii16. A final protective film 17 is formed to complete the vertical PNP transistor and NPN transistor.

By the manufacturing method explained above, the element isolation breakdown voltage can be made sufficiently high, the base width of the sit type PNP transistor (portion A in Figure 1H) can be made sufficiently large, and the vertical type PNP transistor can be made sufficiently large.
It is possible to increase the withstand voltage between the emitter and noctor of the transistor.

In the above embodiment, a method was described in which an NPN transistor is simultaneously formed adjacent to a vertical PNP transistor, but in this invention, the element adjacent to a vertical PNP transistor is not limited to an NPN transistor.
For example, a diffused resistor and a PNP transistor may be formed simultaneously. Further, other elements adjacent to the vertical PNP transistor may be already formed before forming the vertical PNP transistor.

[Effects of the Invention] As described above, according to the present invention, since the P-type semiconductor substrate in the region that becomes the collector of the vertical PNP transistor is etched before forming the N-type epitaxial layer, the device isolation withstand voltage is increased. In addition, the emitter-collector breakdown voltage of the vertical PNP transistor is sufficiently high, and a high-performance, highly integrated bipolar integrated circuit can be obtained.

[Brief explanation of the drawing]

FIGS. 1A to 1H are sectional views showing main steps in a method of manufacturing a bipolar IC according to an embodiment of the present invention. Second
Figures A to 2 are cross-sectional views showing the main steps in a conventional bipolar IC manufacturing method. In the figure, 1 is a P-type silicon substrate, 2 is a first oxide film, 3 is an N-type buried diffusion layer, 4 is a second oxide film, 5.5' is a P-type buried isolation layer, and 50 is a vertical type PNP transistor buried collector layer, 6 is an N type silicon epitaxial layer, 7 is a third oxide film, 8 is an N well layer, 9 is a fourth oxide film, 10
．． 10' is a P-type upper separation layer, 11 is a fifth oxide film, 12
is a P-type emitter layer, 12' is a P-type heath layer, and 13 is a sixth layer.
14 is an N-type base layer, 14' is an N-type emitter layer, 14'' is an N-type collector layer, 15 is a surface protective film, 16
indicates metal wiring, and 17 indicates the final image Im.

Claims (8)

[Claims] (1) A method for manufacturing a bipolar integrated circuit for forming a vertical PNP transistor with PN separation from other adjacent elements on the same P-type semiconductor substrate, the method comprising: on the P-type semiconductor substrate, at least The vertical P
forming a first N-type impurity diffusion layer in a region where an NP transistor is to be formed;
forming a first P type impurity diffusion layer in a predetermined region on the type impurity diffusion layer; and forming a part of the first P type impurity diffusion layer formed on the first N type impurity diffusion layer. a step of etching; a step of forming an N-type epitaxial layer with a flat surface on the entire surface of the P-type semiconductor substrate; forming a second N-type impurity diffusion layer at a position in which the upper region of the first P-type impurity diffusion layer formed in the isolation region and the first N-type impurity diffusion layer are formed in the isolation region; A second P-type impurity diffusion layer is formed in an upper region of an unetched portion of the first P-type impurity diffusion layer formed on the impurity diffusion layer, and the second P-type impurity diffusion layer reaches the first P-type impurity diffusion layer. forming a third P-type impurity layer in the second N-type impurity diffusion layer in the N-type epitaxial layer; forming a third N-type impurity diffusion layer at a position other than the third P-type impurity layer in the type impurity diffusion layer. (2) The method for manufacturing a bipolar integrated circuit according to claim 1, wherein the other element is formed simultaneously with the vertical PNP transistor. (3) The method for manufacturing a bipolar integrated circuit according to claim 2, wherein the other element is an NPN transistor. (4) The first aspect of the present invention is characterized in that the step of etching a portion of the first P-type impurity diffusion layer formed on the first N-type impurity diffusion layer is wet etching. A method for manufacturing a bipolar integrated circuit according to any one of items 1 to 3. (5) Claim 1, wherein the step of etching a portion of the first P-type impurity diffusion layer formed on the first N-type impurity diffusion layer is dry etching. A method for manufacturing a bipolar integrated circuit according to any one of items 1 to 3. (6) Claims characterized in that the step of etching a portion of the first P-type impurity diffusion layer formed on the first N-type impurity diffusion layer is isotropic etching. 6. A method for manufacturing a bipolar integrated circuit according to any one of items 1 to 5. (7) Claims characterized in that the step of etching a portion of the first P-type impurity diffusion layer formed on the first N-type impurity diffusion layer is anisotropic etching. 6. A method for manufacturing a bipolar integrated circuit according to any one of items 1 to 5. (8) Manufacturing the bipolar integrated circuit according to any one of claims 1 to 7, wherein the step of forming the N-type epitaxial layer is performed using an etch-back method. Method.