JPS63244227A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To eliminate need for providing an exclusive register in a byte shifter, by providing a shifter for coupling and shifting the data outputted from two pieces of read-out ports of a register file and outputting them as data of one word. CONSTITUTION:The data in a main storage device is loaded as it is to register files 11, 12, and data are fetched from outputs of shifters 21, 22 to be calculated by a computing element 25, and its result is stored in a word designated by an address A of the register file 12. When addresses which are set to registers 13, 14 are increased by every +1 word and are processed repeatedly, the result of calculation is obtained in the register file 12. In such a way, the shifters 21, 22 couple the data which are outputted from two pieces of read-out ports of the register files 11, 12 and output them as a data of one word, therefore, even in case of loading the data to the register files 11, 12, it is unnecessary to execute a byte alignment by using a byte shifter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an arithmetic device in a computer system.

(Prior Art) In general, in a computer system, when performing an operation between data stored in the main memory device, it is necessary to convert each data read from the main memory device 1 into a byte shifter, as shown in FIG. 4, for example. Align using 2,
The data is loaded into a register file 3 and a register file 4, and an arithmetic unit (ALU) 5 performs calculations.

For example, when one word is 4 bytes, the byte shifter SF is used as the read data RD (Go-
31) and register file RWD (Go-31
) is connected to one word stored adjacently on the LSB side of the first stage, and shifted based on the data address,
Outputs 1 word of data.

In addition, when reading one word (4 bytes) of data from the main memory f1 and aligning the byte byte shifter 2, as shown in FIG.
When the read data is within the 1-word area W, the read data is not shifted and is loaded into the register file as it is.

Here, as shown in FIG. 7, if data D spans two adjacent 1-word areas w, , w2, first, as shown in FIG. 1 on the LSB side stored adjacent to the side
Step A) to read a word, step B) to store it in a register in the byte shifter, step C) to read the next word, connect these two words to create one word of data, and load it into the register file. (Step D).

(Problems to be Solved by the Invention) In the conventional arithmetic device, it is necessary to provide a dedicated register in order to store one word on the LSB side of the first stage. Furthermore, depending on the relationship between the data and the word area of the main memory, two types of processing must be performed when loading data from the main memory to the register file.

That is, when data spans adjacent word areas, the data must be loaded into a register within the byte shifter, resulting in more processing steps than when the data does not span word boundaries.

The present invention was made under these circumstances, and aims to provide an arithmetic device that does not require a dedicated register in the byte shifter and does not require an increase in the number of processing steps even when data crosses word boundaries. .

[Configuration of the Invention (Means for Solving Problems)] The arithmetic device of the present invention includes a register file having two read ports, a register for setting a read address of one port of the register file, An adder adds a predetermined value to this read address to set the read address of the other port of the register file, and combines and shifts the data output from the two read ports of the register file to form one word. It includes a shifter that outputs data and a register that specifies the number of shifts in this shifter.

(Function) In the arithmetic device of the present invention, the register file includes two read ports, and the shifter combines data output from two read reports of the register file and outputs the combined data as one word of data. Therefore, even when loading data into the register file, there is no need to perform byte alignment using a byte shifter, and even when data spans adjacent word areas, there is no need to load data into a dedicated register within the byte shifter. There is no

(Example) Hereinafter, details of an example of the present invention will be described based on the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

In the figure, 11 and 12 are register files for storing data read from the main memory, and a port outputs a word at the address specified by A, and a port B
A port for outputting the word at the address specified by A is provided, and writing is performed to the word at the address specified by A.

13.14 is address A of register file 11.12
register for setting, 15.16 is register 13
．． Add +1 to address A stored in 14,
This is an ALU for creating address B of register files 11.12.

Further, 17 is data output from the word specified by address A of the register file 11.12, and 18 is data output from the word specified by address B of the register file 11.

Similarly, 19 is data output from the word specified by address A of the register file 12, and 20 is data output from the word specified by address B of the register file 12.

21.22 is a shifter that combines and shifts the data output from each of the two read ports of the register file 11.12, and outputs one word of data; 23.22;
A register 24 determines the number of shifts of the shifters 21 and 22.

And 25 is an ALU that performs calculations on the data output from the shifters 21 and 22.

A case will be explained in which one word is 4 bytes and the addressing of data in the main memory is LSB.

First, the data in the main memory is loaded directly into the register file 11.12 without using a byte shifter, and the lower two bits of the address of the data loaded into the register file 11.12 are transferred to each register 23.2.
Set it to 4.

And in registers 13 and 14, register file 11
．． When the word position in which the LSB of the data loaded into the ALU 25 is stored is set, the LSB side 1 side control word byte of the data to be calculated is taken out from the output of the shifter 21 and 22, and the calculation is performed in the ALU 25. The result is stored in the word specified by address A of the register file 12.

Therefore, by increasing the address set in the registers 13 and 14 by +1 word and repeating the above-described processing, the result of the operation can be obtained in the register file 12.

By the way, Figure 2 shows a case where the data in the main memory is within word boundaries, the lower two bits of the address are 00, and the one word extracted from the word specified by address A from the register file. The calculation is performed by outputting the data as is from the shifter.

Figure 3 also shows a case where data in the main memory straddles word boundaries, and the lower two bits of the address are 1.
It is 0.

In this case, the MSB is valid from one word of data extracted from the word specified by address A of the register file.
Extract the 2 bytes on the side, specify and extract the next MSB side with the 1st side control word address, extract the 2 bytes on the LSB side, connect the extracted data, output 1 word of data from the shifter, and perform the calculation. Thus, according to this embodiment, when loading data from the main memory to the register file, there is no need to perform byte alignment using a byte shifter, so even if the data spans adjacent word areas, It is no longer necessary to once load data into the register in the byte shifter, and the processing steps when loading data from the main memory to the register file can be reduced.

Further, since there is no need to separate processing depending on whether data is stored in one word area, processing becomes extremely easy.

Furthermore, according to the present embodiment, there is no need for a register to temporarily store data as in a conventional byte shifter.

[Effects of the Invention] As explained above, the arithmetic device of the present invention includes a register file having two read ports, a register for setting a read address of one port of this register file, and a register for setting a read address of one port of this register file, and a an adder that adds values and sets a read address for the other port of the register file; and a shifter that combines and shifts the data output from the two read ports of the register file and outputs it as one word of data. and a register that specifies the number of shifts in this shifter, so
There is no need to provide a dedicated register in the byte shifter,
Furthermore, even when data straddles word boundaries, the number of processing steps does not increase.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2 and 3 are diagrams explaining the operation of the embodiment, and FIG.
FIG. 5 is a block diagram showing an example of the configuration of a conventional arithmetic device, FIG. 5 is a diagram explaining the operation of the conventional device, FIGS. 6 and 7 are diagrams showing the storage state of data handled by the conventional device, FIG. 8 is a flowchart illustrating the operation of the conventional device. 11.12...Register file 13.14.
23.24... Register 15.16... Adder 17-20... Data 21.22... Shifter 25... ...ALtJ applicant
Toshiba Corporation Agent Patent Attorney Satoshi Suyama - Figure 2 Figure 3': x 4
7th Ko

Claims (1)

[Claims] (1) A register file that has two read ports, a register that sets the read address of one port of this register file, and a read address of the other port of the register file that adds a predetermined value to this read address. a shifter that combines and shifts the data output from the two read ports of the register file and outputs it as one word of data, and a register that specifies the number of shifts in this shifter. A computing device characterized by: