JPS63243910A - Synchronizing circuit for optical scanner - Google Patents

Abstract

PURPOSE:To improve the quality of a writing image by providing a delay clock control circuit to a synchronizing circuit of an optical scanner so as to prevent selection of a clock signal delayed by >=1 periods as an image scanning clock. CONSTITUTION:A modulated laser beam 1 is subjected to main scanning by a rotary polarizer 3 on the surface of a photosensitive body 5 to form an electrostatic latent image thereon. An optical sensor 6 detects the light of the polarizer 3 at this time and the synchronizing circuit 7 generates the image scanning clock synchronized therewith. The laser light is then modulated according to the image signal synchronized with this scanning clock. The delay circuit 12 of the circuit 7 in this constitution generates a reference clock CK1 and clocks CK2-CK7 delayed in phase from said clock. The clock matched most in phase with the photodetection signal is selected and the clocks delayed by >=1 periods are expelled by the delay clock control circuit 15, a latch circuit 13 and a clock selection circuit 14. The synchronization accuracy is thereby inexpensively and surely improved and the good image quality is obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a synchronization circuit for an optical scanning device, and particularly to an optical scanning device that scans a laser beam using a rotating deflector used in a laser printer or the like.

This invention relates to a synchronization circuit for synchronizing image writing.

A light beam is scanned over the object to be scanned using a rotating deflector, and image writing is synchronized by the output of a photosensor installed outside the one-image scanning area, and an image is written on the photoreceptor, which is the object to be scanned. An optical scanning device configured to form a laser beam is used in, for example, a laser printer.

In this case, due to manufacturing errors in the rotating deflector, jitter of up to one pixel may occur in the main scanning direction, reducing image quality.
Conventionally, an original signal with a frequency n times that of the image scanning clock is applied to a 1/n divider, and the divider is reset when a light beam is detected, or the phase is sequentially changed from the reference clock signal by a delay circuit. By creating a group of delayed (n-1) clock signals and selecting the signal that is most in phase with the output of the optical sensor as the image scanning clock, the jitter is suppressed to about 1/n pixels.

However, when n is increased in order to obtain good image quality, the former requires a higher frequency of the original signal, making the circuit more sophisticated and complex, and the latter requires increasing the accuracy of the delay circuit to prevent malfunctions. Both methods had disadvantages such as increased costs.

1- Keiko This invention was made in view of the above points. l
? The purpose of this invention is to inexpensively and reliably increase the accuracy of synchronization without increasing the performance of sensors or circuits, and to improve the image quality of images written by an optical scanning device.

In order to achieve the above-mentioned object, this invention scans an object with a light beam using a rotating deflector, and generates a reference clock signal and a group of clock signals having the same frequency and sequentially delayed phase as the reference clock signal. In the synchronization circuit of an optical scanning device that synchronizes image writing by selecting one clock signal as the image scanning clock based on the output of a photosensor provided outside the image scanning area, one cycle or more than the reference clock signal. Determine the delayed clock signal and
A delay clock management circuit is provided to manage the delay clock so that it is not selected as the image scanning clock.

Hereinafter, the present invention will be specifically explained based on embodiments.

First, the optical system of the optical scanning device to which the present invention is applied will be explained with reference to FIG.
After being deflected by a rotating deflector 3 consisting of a rotating polygonal mirror, it is imaged as a scanning spot by an fO lens 4 onto a photoreceptor 5, which is an object to be scanned.

This laser beam is modulated by a recording signal, and is main-scanned over the surface of the photoreceptor 5 by the rotary deflector 3 to form an electrostatic latent image thereon. Sub-scanning is performed by rotating the photoreceptor 5 around its axis.

The optical sensor 6 is a photodetecting element such as a photodiode provided outside the image recording area on the main scanning line, and detects the laser beam from the one-rotation polarizer and outputs a photodetection signal DETP.

Next, the electrical control system of this optical scanning device will be explained with reference to FIG.

The synchronous circuit 7 is a circuit targeted by the present invention, and functions as an image scanning clock generation circuit, and when the optical detection signal DETP is input from the optical sensor 6, it outputs an image scanning clock WCLK synchronized therewith to the image control circuit 8. .

As mentioned above, since the optical sensor 6 is provided outside the image recording area, the image control circuit 8 counts the WCLK until the light beam reaches the image recording area or a predetermined space is taken, and then displays the character. Start sending a control signal to the generator 9.

The character generator 9 outputs an image information signal synchronized with WCLK for each main scanning line based on the control signal, and the signal is sent to the light source drive circuit 10 via the image control circuit 8.

The light source driving circuit 10 modulates (blinks) the semiconductor laser 1 shown in FIG. 2 in accordance with the image information signal, and forms one line of electrostatic latent image on the photoreceptor 5.

In some cases, the image control circuit 8 may send a reset signal LSYC to the synchronization circuit 7 for each line before the optical sensor 8 detects the light beam.

Although an example in which a semiconductor laser is used as the light source has been described, a gas laser such as a He-Na laser is used as the light source, and a light modulation element such as an acousto-optic element driven by the light source drive circuit 10 is used instead of the collimator lens '2. may be arranged to modulate the laser beam.

FIG. 1 is a block circuit diagram showing the configuration of a synchronization circuit 7 according to a first embodiment of the present invention.

This synchronization circuit 7 includes a reference clock oscillator 11° delay circuit 12. Latch circuit 13. Clock selection circuit 14. and a delay clock management circuit 15 provided between the delay circuit 12 and the latch circuit 13.

The reference clock oscillator 11 generates an image scanning clock WCLK.
oscillates and outputs a reference clock signal (hereinafter "signal" will be omitted) CKI having a frequency equal to that of .

The delay circuit 12 inputs the reference clock CKI and outputs (n-
1) A group of clock signals (hereinafter "signals" will be omitted) whose frequency and waveform are equal to the reference clock CKI and whose phase is delayed by approximately 1/n of the period from the output terminals GK2. C.K.
3... Outputs CKn (the figure shows an example where n=7).

The latch circuit 13 receives a light detection signal DET from the light sensor 6.
When P rises, n inputs are latched and latch signals Q1 to Qn and Q1 to Qn are output.

The clock selection circuit 14 selects clock groups GKI-CKn by a combination of latch signals Q1-Qn and Q1-Qn.
Among them, the clock having the highest phase with the photodetection signal DF:TP is selected and output as the image scanning clock WCLK.

The delayed clock management circuit 15 has clock groups CKI to CK.
P clock groups CK with relatively large delay times among n
(rrp+1) ~ CK n (in the example shown, CK5 ~
CK7) is input, and depending on the phase delay from the reference clock CKI, it is passed through as is, or it is locked to °l'' or °O°, and the signals C(n-p+1) to Cn are output.

For example, as shown in FIG. 4, the clock selection circuit 14 consists of n AND circuits 101 to 107 (seven in the figure) and one OR circuit 10B to which each output is input.

Then, the k-th AND circuit has inputs Dk and D(k+
1) That is, the latch signals Qk and Q(k+1) and the clock CK(k+1) are input, and the clock CK(k
+1) gate is formed. However, only latch signals Qn and Ql and clock CK1 are input to k=n, that is, to the final stage.

Note that here, for ease of explanation, the clock G
K (k+1) is gated, but actually the delay clock management circuit 15. Latch circuit 13 and AN
Since the gates open and close due to the delay in the operation of the D circuits 101 to 107, they are often combined with a clock delayed by about half a cycle to ensure the operation.

In two cases, n==7. In the illustrated case where P=3, clock CK6. The operation of the synchronizing circuit 7 will be explained with reference to the timing chart of the fifth Vl in an example in which CK7 is delayed by one cycle or more than the reference clock CKI.

The phase relationship between the reference clock CKI generated by the reference clock oscillator 11 shown in FIG. 1 and the clock group CK2 . . . CK7 output from the delay circuit 12 is as shown in FIG.

Now, suppose that the delay clock management circuit 15 does not function and the input clocks CK5 to CK7 are passed through as they are.
~C7 output state (delayed clock management circuit 15
).

If the optical detection signal DETP from the optical sensor 6 is input to the latch circuit 13 at the time point (A) or (B) in FIG. 5, for example, each of the clocks CKI to CK7. C5~
Table 1 shows the values of C7, latch signals Q1 to Q7 and logic values Qk and Q(k÷1) for opening and closing the gates.

Table 1 Therefore, in case (A), the fourth clock selection circuit 14
Only the AND circuit 102, which is the second gate shown in the figure, is open and clock CK3 is output, and the other AND circuits 101, 10! Since the outputs of i to 107 are all at 0°, the clock CK3 is selected from the OR circuit 108 and the image scanning clock WC is selected as shown in FIG. 5(A).
It is output as LK.

However, in case (B), AND circuits 101 and 106, which are the first and sixth gates, are open and the clock C
Since K2 and CK7 are outputted, added by the OR circuit 108, and outputted as the image scanning clock WCLK, there is an inconvenience that the waveform becomes likely to cause malfunctions in the subsequent stage, as shown in FIG. 5(B).

This is because clocks (CK6, CK7) whose phase is delayed by one cycle or more from the reference clock CKI are also selected.

Therefore, it is necessary to design so that even the most delayed clock output from the delay circuit 12 does not lag by more than one cycle from the reference clock, but depending on the accuracy and temperature characteristics of the delay circuit, the delay time may become more than one cycle. There is a fear.

Therefore, in this embodiment, the delay clock management circuit 1
5, the delay time is relatively large and the lock group CK5
- Regarding CK7, the phase relationship between the reference clock CKI and the reference clock CKI is monitored, and if there is a clock delayed by one cycle or more, it is determined and managed so that the clock is not selected as the image scanning clock.

FIG. 6 shows a circuit example of the delayed clock management circuit 15, which consists of three sets of circuit systems that have the same configuration and function but are independent from each other, and each circuit system latches the input clock CKk at the rising edge of the reference clock CKI. A D-type flip-flop circuit (hereinafter referred to as rD-FFJ) 11
0, NOT circuit 111 and negative input OR circuit 112
The connection is as shown in the figure.

FIG. 7 is a timing chart showing the relationship between each signal, and as is clear from this diagram, the delay clock management circuit 1
The delay time of the clocks CK5 to CK7 that are input to Clock 5 is around one cycle, so if the level is 1° when latched at the rising edge of the reference clock CKI, the delay time of that clock is one cycle. If it is less than 0°, it means that it is one cycle or more.

The operation of one circuit system of the delayed clock management circuit 15, for example, the circuit system that manages the clock CK5, will now be described.

When the reference clock CKI rises, if the clock CK5 input to the data input terminal of the D-FF110 is 1°, the output G5 of the D-FFllQ will be the next reference clock CK.
It is latched at 1 until the rising edge of I, and the clock CK5 is
If it is 0°, G5 is latched at 0°.

Further, this clock CK5 is inverted by the NOT circuit 111, becomes CK5, and is inputted to the negative input OR circuit 112 together with G5.

Therefore, the output C5 of the OR circuit 112 is C3=G5+
Since it is CK5, the output G5 of D-FFIIO is °1°
If G5 is latched at 0°, C3=CK5 and CK5 passes through as is, and when G5 is latched at 0°, 05 is always held at 1°.

The same applies to other circuit systems, so if the delay time of the input clock CKk is less than one cycle, the delay clock management circuit 15 outputs it as is, and if it is more than one cycle, it always outputs 1°. works.

Therefore, in FIG. 7, the light detection signal D from the light sensor 6
Each clock CKI when the ETP is input to the latch circuit 13 in FIG. 1 at the same time point (A) or (B) as in FIG.
~CK7. C5-C7, latch signals Q1-Q7 and Q1-
Q7 and the logical value Q K-Q (K+
The values of 1) are shown in Table 2.

Table 2 Therefore, in case (A), only the AND circuit 102, which is the second gate of the clock selection circuit 14 shown in FIG. Only one AND circuit 101 is open and clock G
K2 is correctly output as the image scanning clock WCLK (see FIG. 7).

FIG. 8 shows another example of the delay clock management circuit.
The first optical detection signal DETP is sent from the optical sensor 6 for every l line.
1 image control circuit 8 before being input to the latch circuit 13 in the figure.
A reset signal L is sent to this delayed clock management circuit 15' from
It is assumed that SYC is sent.

This delayed clock management circuit 15' has a reference clock CK
Set/reset type flip-flop circuits (hereinafter referred to as rR5-FFJ) 120 to 12 that are set by I and reset by each clock GK4 to CK7, respectively.
3, D-FFs 124 to 12B (125 and 128 are equipped with preset terminals PR), which are cleared at the falling edge of the reset signal LSYC, and their respective outputs G5. G6
．． OR circuits 127 to 129 each using G7 as a negative input
The connection is as shown in the figure.

The operation of this delayed clock management circuit 15 will be explained with reference also to the timing chart of FIG.

The first stage R8-FF120 to 123 uses the reference clock CK.
Since it is set at the rising edge of I and reset at the rising edge of each clock CK4 to CK7, its output Q4 to
Q7 becomes as shown in FIG.

The next stage D-FF124 to 126 receives the reset signal LSY
It is cleared by the falling edge of C.

Each of the Q outputs 05 to G7 becomes 1° at that point, regardless of the previous level.

Since the D-FFs 124 to 12B each latch the D inputs (Q4 to Q6) by the fall of the CP large input due to the outputs Q5 to Q7 of the previous stage, the inputs are 0 at that time.
Since the Q output is 0° and the Q output is 1°, the output Gk (k=1 to 3) is maintained at 1°. If the D input is °1°, the output Gk becomes 0°, and the D-FF whose output is input to the preset terminal is preset, so its output also becomes °0°, and the following D - All outputs of FF become 0°.

In the example of FIG. 9, each o is reset at the falling edge of the reset signal LSYC.
-Outputs 05 to G7 of FF124 to 12B are all °1°
After that, when G5 falls, G4 is at °0°, so G5 maintains 01°, and when G6 falls, G5 remains at °1°.
Therefore, G6 becomes °0゛, and therefore C7 also becomes 6
It becomes 0#.

This state is maintained during this one line scan.

These signals 05 to G7 are respectively input to the next stage OR circuit 127.
This is because it is input to the negative input terminal of ~129.

Clock CK5 is output as is as C5, but C
6, C7 is CK6. It remains at 1, regardless of CK7, and has the same effect as the circuit shown in FIG.

FIG. 10 is a block circuit diagram of a synchronous circuit showing a second embodiment of the present invention, in which a delay circuit 12 and a clock selection circuit 2
A delay clock management circuit 25 is provided between the four clocks.

In this synchronous circuit 7', reference clock oscillation [111
The delay circuit 12 and latch circuit 13 function exactly the same as in the embodiment shown in FIG.

The delayed clock management circuit 25 receives P clock groups CK (n-p
+1) ~CK n by °1 ° or O ° depending on whether the phase delay from the reference clock CK1 is within one cycle or not.
It outputs signals G (n-p◆1) to Gn locked to (the figure shows an example where n=7.P=3).

The clock selection circuit 24 is composed of, for example, seven AND circuits 201 to 207 as shown in FIG. Regarding the processing of the 11 clock groups, the clock selection circuit 1 shown in FIG.
Regarding the clock group managed by the delayed clock management circuit 25 using the logical product Qk-τ as in 4.

By the logical product Qk-Q(k◆1)・Gk, A
Gates by ND circuits 201 to 207 are opened and closed.

FIG. 12 shows an example of the delayed clock management circuit 25, in which three D-FFIIs each latch the human clocks CK5 to CK7 at the rising edge of the reference clock CKI.
Consists of O.

As explained in the delayed clock management circuit 25 shown in FIG. 6, when each D-FFIIO latches the D input at the rising edge of the reference clock CKI.

If the clock CKk that is the D input is °1" (delay time is less than one cycle), the output Gk is at °1° and 0° (
If the delay time is one cycle or more), Gk is locked at °o°.

FIG. 13 shows another example of the delay clock management circuit;
The same parts as in the figure are given the same reference numerals.

This delayed clock management circuit 25' is the circuit 15 in FIG.
This is a circuit obtained by removing the OR circuits 127 to 129 from ', and its operation is the same as described for the delayed clock management circuit 15', and the output becomes 0 at the falling edge of the reset signal LSYC.
5 to G7 once reach ゛1°, the output GK corresponding to the clock input with a delay time of less than one cycle maintains ゛1°,
Since all the outputs Gk corresponding to clock inputs of one cycle or more become and are maintained at 0°, there is an effect similar to that of the circuit shown in FIG. 12.

In the synchronous circuit 7' of FIG. 10, the optical detection signal DETP from the optical sensor 6 is the same as that of FIG. 5 (A) or (B).
Each clock C when input to the latch circuit 13 at the time of
KI~CK7. Latch signals Q1-Q7 and Q1-Q7.
Managed signals 05-G7 and clock selection circuit 24
The logic values for opening and closing the gates are shown in Table 3.

Table 3 Note that the logical values for opening and closing the gates are Qk-Q(k+1) for k=1 to 4, and Qk-Q(k+1)·Gk for k=5 to 7.

That is, in this embodiment as well, in case (A), the first
The second gate (
AND circuit 202) is opened and clock CK3 is output (B)
In this case, the first gate (AND circuit 201) is opened, and the clock CK2 is selected by the OR circuit 208 and correctly output as the one-image scanning clock WCLK.

As described above, according to each of the above embodiments, by providing the delayed clock management circuit 15 (15') or 1B (1B'), even if a clock whose delay time from the reference clock is one cycle or more is generated, Since this is determined so that it is not selected as an image scanning clock, the optimum image scanning clock can always be accurately output.

Also, even if n is set large to improve synchronization accuracy,
Since the number of clocks that need to be managed is not so large, the circuit is simple and does not increase costs.

As explained above, in the synchronization circuit of the optical scanning device according to the present invention, even if n is set large to improve synchronization accuracy,
Unlike the 1/n frequency divider circuit method, it does not handle high frequencies, and unlike the conventional delay clock selection method, it does not malfunction due to delay circuit accuracy or temperature changes, and there is no need to improve the delay circuit accuracy. Adjustment is easy, and the accuracy of synchronization can be inexpensively and reliably increased, and the quality of images written by the optical scanning device can be improved.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of a synchronous circuit according to a first embodiment of the present invention. FIG. 2 is a configuration diagram of an optical system of an example of an optical scanning device to which the present invention is applied. FIG. 3 is a block diagram of the electrical control system, FIG. 4 is a circuit diagram showing an example of the clock selection circuit 14 in FIG. 1, and FIG. 5 is a circuit diagram showing an example of the clock selection circuit 14 in FIG. FIG. 3 is a timing chart diagram for explaining the operation assuming that. 6 is a circuit diagram showing an example of the delayed clock management circuit 15 in FIG. 1, FIG. 7 is a timing chart diagram for explaining the normal operation of the embodiment shown in FIG. 1, and FIG. 8 is a delay clock management circuit. FIG. 3 is a circuit diagram showing another example of the circuit. FIG. 9 is a timing chart diagram for explaining the operation thereof, and FIG. 10 is a block circuit diagram of a synchronous circuit according to a second embodiment of the present invention. FIG. 11 is a circuit diagram showing an example of the clock selection circuit 24 in FIG. 10, and FIG. 12 is a circuit diagram showing an example of the clock selection circuit 24 in FIG. 10.
The circuit diagram which shows an example. FIG. 13 is a circuit diagram showing another example of the delayed clock management circuit. 1... Semiconductor laser 2... Collimator lens 3
...Rotating deflector 4...Fθ lens 5...Photoconductor 6...Photo sensor 7...Synchronization circuit 8...Image control circuit 11...Reference clock oscillation @ 12... Delay circuit 13...Latch circuit 14.24...Clock selection circuit 15, 15', 25.25'...Delay clock management circuit Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 (A ) (B) Figure 6 Figure 7 Figure 8 Figure 9 C7/C7 Nini: Yu Akira 1, Indication of Case Patent Application No. 62-76098 2, Title of Invention Synchronous Circuit for Optical Scanning Device 3, Person Making Amendment Relationship to Case Patent Applicant 1-3-6 Nakamagome, Ota-ku, Tokyo No. (674) Ricoh Co., Ltd. - 4, Agent (Telephone: 986-23JlG)
1-20 Higashiikebukuro, Toshima-ku, Tokyo ” he corrected. (2) rWcLK on page 5, lines 11 and 14 of the same book.”
Insert "image scan clock" before each. (3) Same number @ page 21, first line rH; (IB')J
is corrected as ff2s (25')ffl. (4) "Figure 1" of the drawing is corrected as shown in the attached corrected drawing. Figure 1 of the above corrected drawing

Claims (1)

[Claims] 1 A light beam is scanned over the scanning object by a rotating deflector, and an optical sensor installed outside the image scanning area is selected from among a reference clock signal and a group of clock signals whose frequency is equal to that of the reference clock signal and whose phase is sequentially delayed. In the synchronization circuit of an optical scanning device, which synchronizes image writing by selecting one clock signal as an image scanning clock based on the output of 1. A synchronization circuit for an optical scanning device, comprising a delay clock management circuit that manages the delay clock so that it is not selected as a scanning clock.