JPS6324326B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer type transversal filter. More specifically, charge detection means such as floating electrodes and floating diffusion layers that non-destructively detect signal charges at each transfer stage of a charge transfer element having a large number of transfer stages or every integer multiple of transfer stages, and charge detection means for each such means. Field effect transistor (FET)
The first analog signal detected by the detection means is multiplied by a second analog signal such as a weighting coefficient of a filter, and each detection means has a four-quadrant analog signal multiplier. This invention relates to a charge transfer type transversal filter that can add the multiplication results of . Since this type of filter allows arbitrary weighting coefficients to be controlled externally, by changing the weighting coefficients, one filter can be configured to suitably have a large number of filters with different characteristics. . That is, the weighting coefficient is set externally,
It can be applied to a wide range of fields, such as programmable filters that are semi-fixed only during a certain period of time, and adaptive filters that automatically set weighting coefficients as appropriate over time. However, conventional charge transfer type transversal filters have drawbacks such as a complex tap circuit consisting of a non-destructive charge detection means and a multiplier, making it difficult to integrate, and consuming a large amount of power. Furthermore, two MOS FETs (hereinafter referred to as
Since a multiplier composed of MOSFETs (referred to as MOSFETs) was used, due to the size of the two MOSFETs, that is, the difference in gate length L (W/L) with respect to gate width W (W/L) and characteristics, true analog multiplication function could not be achieved. I couldn't be more satisfied. Therefore, it has been difficult to realize a high performance programmable or adaptive filter with a wide dynamic range.

FIG. 1 shows the configuration of a conventional charge transfer type transversal filter (hereinafter referred to as charge transfer device, hereinafter referred to as CTD). 1 shows, as an example, a charge transfer stage of a delay line using a charge-coupled device (hereinafter referred to as CCD). Note that the input section of the CCD, etc. are omitted. Here, as an example, a three-phase structure in which one transfer stage includes transfer electrodes 2 and 3 and a detection electrode 4 used as means for non-destructively detecting signal charges is shown. Furthermore, a detection electrode serving as the detection means is provided for each transfer stage. The transfer electrodes 2 and 3
are driven by voltage pulses supplied from wirings 2' and 3', respectively. Since the potential of the detection electrode 4 is set to be in a floating state when detecting a signal,
Usually called a floating electrode. The output signal of electrode 4 is applied to tap circuit 5. Reference numeral 6 is a switch such as a MOSFET that is periodically opened and closed by a pulse applied to the wiring 7, sets the potential of the detection electrode 4 to the DC potential applied to the wiring 8, and then puts it into a floating state.
A source follower composed of MOSFETs 9 and 10 is a buffer circuit provided between the detection electrode 4 and multipliers 11 and 12, and its input terminal is a buffer circuit provided between the detection electrode 4 and the multipliers 11 and 12.
is connected to. 11 and 12 are MOSFETs that constitute two analog signal multipliers, and both MOSFETs
The drains (or sources) of both are connected to the output terminal 10' of the source follower. Applicable
The gate of MOSFET 11 is connected to wiring 13,
A direct current potential is supplied. On the other hand, the MOSFET12
Analog signals such as weighting coefficients are supplied from a terminal 14 to the gate. The sources (or drains) of the MOSFETs 11 and 12 are connected to wirings 15 and 1, respectively.
6 to the non-inverting input terminals of operational amplifiers 17 and 18. The inverting input terminals of the operational amplifiers 17 and 18 are connected to a terminal 21 and supplied with a DC potential. Furthermore, the resistors 19 and 20 form an adder circuit together with the corresponding operational amplifiers 17 and 18, and the adder circuit converts the current flowing through the wiring 15 or 16 into a voltage, that is, constitutes a current/voltage converter. The output terminals of both operational amplifiers 17 and 18 are connected to a subtracter 22, and the subtraction result, ie, the output signal of the CTD filter, can be obtained from a terminal 23.

Next, the operation shown in FIG. 1 will be explained. When the switch 6 closes due to a pulse applied to the wiring 7 immediately before the signal charge is transferred from directly under the electrode 3 of each transfer stage to directly under the detection electrode 4, the detection electrode 4 changes to the DC potential applied to the wiring 8. is set to Next, when the pulse applied to the electrode 3 returns to a low level, the charge accumulated directly under the transfer electrode 3 is transferred to the detection electrode 4 and is accumulated there. The charge is detected non-destructively by the electrode 4 during the storage period. Next, when the pulse applied to electrode 2 becomes high level,
The signal charge immediately below the detection electrode 4 is transferred to the area immediately below the transfer electrode 2. In the same way as below, periodic pulses applied to the wirings 2', 3', and 7 cause the signal charge to
The data is sequentially transferred inside the CCD 1 from left to right. Assume that the potential of the detection electrode 4 is V _d /G when the accumulated charge directly under the detection electrode 4 is only a bias charge, that is, when the input signal is zero. on the other hand,
Assume that the potential of the electrode 4 becomes (V _d +v _ik )/G when the input signal is detected. Here, V _d is a DC component, v _ik (k=1, 2, 3...N) is a signal component containing positive and negative signs, and G is a source follower 9, 10.
is the gain of Therefore, the potential at the output terminal 10' of the source follower becomes V _d or V _d +v _ik . now,
DC potential V _g is applied to the wiring 13, and V _g +v _gk (k
= 1, 2, 3...N), and V _d is applied to the terminal 21. However, it is assumed that these potentials are set within a range in which the MOSFETs 11 and 12 operate in the triode region. Note that v _gk is an analog signal corresponding to a weighting coefficient etc. including positive and negative signs. v _ik is positive and V _g
>V _d , currents I 1k , I _2k flow through MOSFETs 12 and 11 from terminal 10' to 19 or 20 _.
shall be.

Drain current I in the triode region of MOSFET
is the formula (11.4) on page 99 of Integrated Circuit Engineering (2) Circuit Technology Edition (Corona Publishing), co-authored by Hisayoshi Yanai and Minoru Nagata.I _D = β {(V _GS −V _T )V _DS −V ² _DS /2 } is given by Here, β is a constant determined by the characteristics of the MOSFET, V _GS is the voltage between the gate and source, and V _DS
is the voltage between the drain and source, and V _T is the threshold voltage. Therefore, the gate potential and source potential of MOSFET 12 are (V _g +v _gk ) and the potential of terminal 21 V _d , respectively, so the potential between the gate and source of MOSFET 12 is (V _g +v _gk −V _d ). . Similarly, the drain potential of the MOSFET 12 is V _d
+v _ik ), the potential between the drain and source of the MOSFET 12 becomes v _ik . Therefore, in the triode region, the drain current flowing through the MOSFET 12
I _1k is given by I _1k = β ₁ {(V _g +v _gk −V _d −V _T1 )v _ik −v ² _ik /2} (1). Here, β ₁ is mainly MOSFET
The constant determined by the characteristics of 12, V _T1 , is
This is the threshold voltage of MOSFET 12. MOSFET1
The drain current I _2k flowing through 1 is given in the same way.
The potential between the gate and source of MOSFET11 is (V _g −
V _d ), and the potential between the drain and source is v _ik , so I _2k is given by I _2k = β ₂ {(V _g −V _d −V _T2 )v _ik −v ² _ik /2} (2) It will be done. Here β ₂ is mainly MOSFET1
1, V _T2 is a constant determined by the characteristics of MOSFET
11 threshold voltage. Now, if the resistance values of resistors 19 and 20 are 1Ω, the output voltages v ₁ and v ₂ of operational amplifiers 18 and 17 are respectively v ₁ = V _d − _N 〓 ^k=1 I _1k (3) v ₂ = V _d − _N 〓 ^k=1 I _2k (4). Therefore, if the gain of the subtractor is 1, then
The signal voltage v ₀ obtained from the terminal 23 becomes v ₁ −v ₂ . That is, v ₀ = _N 〓 ^k=1 {β ₁ v _ik v _gk −v _ik (β ₁ V _T1 −β ₂ V _T2 ) +v _ik (V _g −V _d )(β ₁ −β ₂ )+v ² _ik (β ₁ − β ₂ )/
2}(5). Now the size of MOSFET12 and 11 (W/
L) are equal, that is, β ₁ = β ₂ and the threshold voltages are also equal (V _T1 = V _T2 ), then the above equation becomes v ₀ = β _1N 〓 ^k=1 v _ik v _gk (6), It can be seen that the convolution calculation function is satisfied and the CTD filter satisfies the transversal filter function. Similar results are obtained when v _ik is a negative value.

The configuration and driving method of a conventional CTD filter has been explained above. Conventional CTD filter tap circuit 5
is a buffer source follower composed of two MOSFETs 9 and 10, and also two MOSFETs 1.
It consisted of an analog signal multiplier consisting of 1 and 12. In order to more accurately transmit the output signal of the signal detection electrode 4 to the input terminal 10' of the multiplier, the current supply capacity of the source follower should be made sufficiently large.
It was necessary to reduce the output impedance as much as possible. For this reason, it is necessary to set the size (W/L) of MOSFETs 9 and 10 to be extremely large.
Not favorable for integration. Furthermore, because the current supply capacity was large, a large amount of power was consumed. For this reason, it has been almost impossible to construct a filter that requires a large number of taps. Furthermore, the distortion characteristics of the source follower were poor, reducing the dynamic range of the filter. Furthermore, β ₁ of MOSFET12 and
β ₂ of MOSFET11 or V _T1 of MOSFET12
Since it is almost impossible to make V _T2 of MOSFET 11 and V T2 completely equal to each other, the output signal of the CTD filter cannot obtain the true multiplication result shown in equation (6), and is expressed as shown in equation (5). , and a nonlinear term has been added. As a result, it does not satisfy the basic "convolution" calculation formula of transversal filters, resulting in disadvantages such as large errors and distortions, and in reality it is difficult to achieve high performance.
It was almost impossible to realize a CTD filter.

The present invention provides a charge transfer type transversal filter that eliminates the drawbacks of conventional CTD filters.Furthermore, the present invention greatly simplifies the tap circuit of conventional CTD filters and is suitable for programmable filters and adaptive filters. This is what makes it possible. That is, the source hollow buffer circuit that made the tap circuit of the conventional CTD filter complicated was removed, and one of the two MOSFETs in the analog signal multiplier was also removed. As a result, power consumption has been reduced, true analog multiplication has been realized, and integration has become easier.

This will be explained in detail below using the drawings.

FIG. 2 is an example showing a specific configuration of the CTD transversal filter of the present invention. FIG. 3 shows an example of a basic pulse waveform for driving the CTD filter of FIG. 2 and an example of a tap output waveform. In FIG. 2, numerals 1 to 6 are the same as the components indicated by the same numbers in FIG. 1 is a charge transfer device, for example a CCD
It is shown using It is assumed that the electrodes per one transfer stage of the CCD are composed of transfer electrodes 2 and 3, and a signal detection electrode 4 serving as charge detection means. Pulses 60 and 61 that periodically turn on and off are applied to the transfer electrodes 2 and 3 from common wiring lines 2' and 3', respectively. MOSFET6 is a reset switch, and
The gate of MOSFET 6 is connected to the pulse 6 from the common wiring 7.
2 is applied, the MOSFET switch is opened and closed, and the detection electrode 4 is set to the DC potential _VF periodically applied to the common wiring 8. 30 is a switch such as a MOSFET, and a periodic pulse 63 is applied to the gate of the MOSFET from the common wiring 31, so that the detection electrode 4 is connected to the DC potential V′ _g periodically applied to the common wiring 32. Set. 33 is a MOSFET, which constitutes an analog signal multiplier. The gate of the MOSFET 33 is connected to the detection electrode 4, and the source (or drain) end thereof is connected to the common wiring 34. on the other hand,
The drain (or source) has a DC potential V′ _d and an analog signal v′ _dk (k=1, 2,
3...N) is connected to the terminal 35 that applies the voltage. 4
0 is a converter that converts current into voltage, and is composed of, for example, an adder circuit including an operational amplifier 41, a resistor 42, and the like. The inverting input terminal of the operational amplifier 41 is connected to the multiplier of each tap circuit 36, that is, the source (or drain) of the MOSFET 33 via the common wiring 34, and the DC potential V _d is applied from the non-inverting input terminal 43. Ru. The output terminal of the adder circuit 40 is coupled via one switch 44 to a memory element 45 such as a sample and hold circuit, and via the other switch 46 to a memory element 47 such as another sample and hold circuit. The memory element 4
Output terminals 5 and 47 are respectively connected to two input terminals of a subtracter 48, and the output signal of the CTD filter is obtained from a terminal 49.

Next, the operation of the CTD transversal filter of the present invention will be explained with reference to the drive pulse timing shown in FIG. Now, attention is paid to the kth transfer stage and the kth tap circuit. Now, assume that charge is accumulated directly under the transfer electrode 2 of the k-th transfer stage during a period 70 in which the pulse 60 is at a high level. In the next period 71, the pulse 61 also becomes high level, so a part of the charge directly under the electrode 2 is transferred to the electrode 3.
Transferred directly below. When pulse 60 returns to a low level during period 72, all of the charge immediately below electrode 2 is transferred to immediately below electrode 3, where it is accumulated. On the other hand, the period 7
Since the pulse 62 applied to the wiring 7 at 2 also becomes high level and the switch 6 is closed, the potential of the detection electrode 4 is set to the DC potential V _F applied from the common wiring 8 as shown at 64. Here, if the level of V _F is sufficiently lower than the high-level potential of the pulse 61, the signal charge immediately below the electrode 3 will not be transferred to immediately below the detection electrode 4. next period 73
Now, since the pulse 62 returns to a low level, the switch 6 is opened again, and the potential of the detection electrode 4 becomes
Stays floating at V _F. However,
Since the pulse 61 to the electrode 3 is also at a low level, the electric charges immediately below the electrode 3 are all transferred to immediately below the detection electrode 4. Therefore, the potential of the detection electrode 4, which is in a floating state, changes as shown at 64.
That is, the potential of the floating electrode 4 changes via the insulating film capacitance between the detection electrode 4 and the signal charge accumulated in the semiconductor substrate immediately below the electrode 4 (due to capacitance coupling). This displacement voltage is positive, centered around a certain constant DC voltage V′ _g every cycle,
Assuming that the signal component v' _gk with a negative sign varies, the potential of the detection electrode 4 can always be written as V' _g +v' _gk during the period 73. When the pulse 60 becomes high level again in the period 74, the charge directly under the electrode 4 is transferred to the electrode 2 of the (k+1)th transfer stage. Next, in the period 75, the pulse 61 becomes high level again, so that charges are accumulated directly under the electrodes 2 and 3. On the other hand, since the pulse 63 also becomes high level during the period 75, the switch 30 is closed and the detection electrode 4
is set to the potential V′ _g applied from the common wiring 32. Note that the signal voltage applied from terminal 35
V' _d + v' _dk is 2 of the period 75 and the period 73
A constant value over a period of time. Similarly, pulse 6
0, 61, 62, and 63 are applied periodically, the potential of the detection electrode 4 alternately repeats the potential of V' _g +v' _gk and V' _g .

Electrical stamp applied from terminal 35 during periods 73 and 75
The following description assumes that all signal components v' _dk of V' _d +v' _dk (k=1, N) are positive values. In this state, period 7
3 from the terminal 35 to the common wiring 34
The drain current I ₁ in the triode region flowing through MOSFET 33 is expressed as I ₁ = β′ _N 〓 〓 ^k=1 {(V′ _g +v′ _gk −V′ _d −V ′ _T )v′ _dk −(v′ _dk )2
/2}(7) Therefore, the output voltage of the adder circuit 40 v′ ₁
If the resistor 42 is 1Ω, then v′ ₁ =V′ _d −I ₁ (8). Here, β' is a constant determined by the size (W/L) of MOSFET 33, and V' _T is a threshold voltage.
If the switch 44 is closed and the switch 46 is opened during this period 73, the voltage v' ₁ will be applied to the memory element 45.
is maintained. On the other hand, if the switch 46 is closed during the period 75 and the switch 44 is left open, the terminal 35
The drain current I ₂ in the triode region, which flows from the MOSFET 33 toward the common wiring 34, is given by I ₂ = β′ _N 〓 〓 ^k=1 {(V′ _g −V ′ _d −V′ _T )v′ _dk −(v′ _dk ) ² /2}(9
), and the output voltage v' ₂ of the adder circuit 40 becomes v' ₂ +v' _d −I ₂ (10). This value v' ₂ is held in storage element 47.
Therefore, if the gain of the subtracter 48 is 1, the signal voltage v ₀ obtained from the terminal 49 during the period 75 is the difference between equations (8) and (10), that is, v′ ₀ =β′ _N 〓 It is given by ^k=1 v′ _gk v′ _dk (11) and achieves the basic operation formula of transversal filter, ``convolution.'' In addition, all taps (k
Similar results are obtained if the value of v' _dk at (=1, N) is negative, or if it is negative or positive for each tap. It is also clear that the value of v′ _gk may have either a positive or negative sign.

In FIG. 2, normal operation can be obtained even if the memory element 47 is omitted and the output terminal of the converter 40 constituted by a direct addition circuit or the like is connected to the input terminal of the subtracter 48 via the switch 46. That is, period 7
Since the switch 44 is opened at 5 and the switch 46 is closed, the output signal v' ₂ of the adder circuit 40 is directly applied to the subtracter 48. On the other hand, during this period, the output signal v' ₁ of the storage element 45 is also applied to the subtracter, so that the subtracter 48 calculates the difference between v' ₁ and v' ₂ , that is,
v′ ₀ in equation (11) is obtained.

The CTD transversal filter of the present invention has a simple structure mainly consisting of a CTD that performs signal delay and non-destructive signal detection, and a tap circuit consisting of a multiplier consisting of a reset switch and one FET. That is, the CTD filter of the present invention, in which the source holo buffer circuit that constitutes the tap circuit of the conventional CTD filter is omitted, and the multiplier configured with two FETs is configured with one FET, is as follows. It has the following characteristics. Since the structure is simple, integration of CTD filters can be easily achieved.
A source hollow buffer circuit can be omitted, and power consumption can be significantly reduced. 1 piece
Multipliers using FETs do not have errors that depend on the size and characteristics of the FETs, so true analog multiplication results can be easily obtained. Therefore, by using the CTD filter of the present invention having the above-mentioned advantages, it becomes possible to easily realize complex programmable filters and adaptive filters, which were almost impossible to realize with conventional CTD filters.

The CTD transversal filter has been explained above. Here, as an example, we have explained a CCD that uses a floating gate for signal delay and detection.
Brigade Device). Further, in this description, a three-phase mode was used to drive the CTD, but any drive mode may be used as long as normal functions are satisfied. The timing of the drive pulses used in this description is merely an example, and it is clear that pulses with any timing may be used as long as normal operation is achieved. In the present invention
Although the explanation was made using a MOS structure FET, a junction type FET (JFET) or a MOSFET may also be used. Furthermore, the FET can be either an enhancement type or a depletion type, and
It doesn't matter if it's channel or N channel. CTD,
The components of the CTD filter of the present invention, such as the tap circuit, adder, sample-and-hold circuit, and subtracter, may be independent components or may be integrated on the same semiconductor substrate.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a conventional CTD filter. FIG. 2 shows an example of the CTD filter of the present invention, and FIG. 3 shows the timing of pulses for driving the CTD filter of FIG. 2. 1 is a CTD such as CCD or BBD, 5 and 36 are tap circuits, 17, 18 and 41 are operational amplifiers, 45,
47 is a storage element, 22, 48 is a subtracter, 6, 9,
10, 11, 12, 30, 33 are MOSFETs, 1
9, 20, and 42 are resistors, and 44, 46 are switches.

Claims (1)

[Claims] 1. The signal charge is detected non-destructively at each signal charge transfer stage or every integer multiple transfer stage, and the voltage signal is
The k _- th detection means (k=1, 2, 3 _... N) of the charge transfer element with a tap, which has the detection means for converting V g +v gk (k=1, 2, 3...N), into the detection means The k-th detection means is connected to the first common wiring, which is common to all the detection means and to which a constant potential is applied, through a first switch in one-to-one correspondence for each of the k-th detection means. The second one corresponds to each method on a one-to-one basis.
common to all the detection means through a switch,
and is connected to the second common wiring to which the potential V _g is applied, and connects all of the detection means to the first common wiring.
One pair of corresponding field effect transistors are provided, each detecting means and the gate of the corresponding field effect transistor are respectively connected, and each source terminal of the field effect transistor is connected to a signal source V _d +v _dk that changes with time. (k=1, 2, 3...N),
The drain terminals of all the field effect transistors are connected to a third common wiring, and the third common wiring is connected to an inverting input terminal of a current/voltage converter configured with an adding circuit, and the current/voltage is The non-inverting input terminal of the converter is connected to a voltage source at potential V _d , the output terminal of the current-to-voltage converter is connected to a third and a fourth switch, and one of the third and fourth switches A charge transfer type, characterized in that one of the switches is connected to one input terminal of a subtracter via a memory element, and the other of the switch is connected to the other input terminal of the subtracter, either directly or via a memory element. Transversal filter. 2 Non-destructively detects the signal charge at each signal charge transfer stage or at each integer multiple transfer stage, and converts the voltage signal into
The k _- th detection means (k=1, 2, 3 _... N) of the charge transfer element with a tap, which has the detection means for converting V g +v gk (k=1, 2, 3...N), into the detection means The k-th detection means is connected to the first common wiring, which is common to all the detection means and to which a constant potential is applied, through a first switch in one-to-one correspondence for each of the k-th detection means. The second one corresponds to each method on a one-to-one basis.
A field effect transistor is connected to a second common wiring common to all of the detection means and to which a potential V _g is applied through a switch, and is connected to all of the detection means in one-to-one correspondence with the detection means. are connected to the gates of the corresponding field effect transistors, and each source terminal of the field effect transistors is connected to a signal source V _d +v _dk (k=1, 2, 3) that changes with time. ...Connect with N),
The drain terminals of all the field effect transistors are connected to a third common wiring, and the third common wiring is connected to an inverting input terminal of a current/voltage converter configured with an adding circuit, and the current/voltage is The non-inverting input terminal of the converter is connected to a voltage source at potential V _d , the output terminal of the current-to-voltage converter is connected to a third and a fourth switch, and one of the third and fourth switches In a charge transfer type transversal filter, one of the switches is connected to one input terminal of a subtracter via a memory element, and the other of the switch is connected to the other input terminal of the subtracter, either directly or via a memory element, The first switch is set to the closed state, the second, third, and fourth switches are set to the open state, and then, after the first switch is also set to the open state, only the third switch is set to the open state. One cycle is a series of open and close states in which the switch is closed and then opened again, then the second switch is closed, the fourth switch is also closed, the fourth switch is opened, and the second switch is opened. , repeating the first, second, third, and fourth switches at the timing,
The third switch is opened and closed at the same period, and the signal charge is transferred in the charge transfer element so that the signal charge is detected by the detection means almost in synchronization with the closed state of the third switch, and the V _d +v _dk is set so that it maintains the same value during the one cycle period and changes to a desired _value every _cycle , _{and the} field _{effect transistor} A method for driving a charge transfer type transversal filter, characterized in that setting is performed within a range that operates in a triode region. 3 Non-destructively detects the signal charge at each signal charge transfer stage or at each integer multiple transfer stage, and converts the voltage signal into
The k _- th detection means (k=1, 2, 3 _... N) of the charge transfer element with a tap, which has the detection means for converting V g +v gk (k=1, 2, 3...N), into the detection means The k-th detection means is connected to the first common wiring, which is common to all the detection means and to which a constant potential is applied, through a first switch in one-to-one correspondence for each of the k-th detection means. The second one corresponds to each method on a one-to-one basis.
A field effect transistor is connected to a second common wiring common to all of the detection means and to which a potential V _g is applied through a switch, and is connected to all of the detection means in one-to-one correspondence with the detection means. are connected to the gates of the corresponding field effect transistors, and each source terminal of the field effect transistors is connected to a signal source V _d +v _dk (k=1, 2, 3) that changes with time. ...Connect with N),
The drain terminals of all the field effect transistors are connected to a third common wiring, and the third common wiring is connected to an inverting input terminal of a current/voltage converter configured with an adding circuit, and the current/voltage is The non-inverting input terminal of the converter is connected to a voltage source at potential V _d , the output terminal of the current-to-voltage converter is connected to a third and a fourth switch, and one of the third and fourth switches In the charge transfer type transversal filter, one of the switches is connected to one input terminal of the subtracter via a memory element, and the other of the switch is connected to the other input terminal of the subtracter directly or via the memory element. The first and fourth switches are kept closed, first the second switch is closed, then the third switch is also closed, and then the third switch is closed.
Open the second switch, then open the second switch, close the first switch, open it again, close the fourth switch, then open it. As a cycle, the first, second, third, and fourth switches are repeatedly opened and closed at the same timing, and
The signal charge is transferred in the charge transfer element so that the signal charge is detected by the detection means almost synchronously with the state in which the fourth switch is closed, and the V _d +v _dk is maintained during the one cycle period. The V _g +
A method for driving a charge transfer transversal filter, comprising setting v _gk , V _d +v _dk , V _g , and V _d within a range in which the field effect transistor operates in a triode region.