JP2526204B2 - Constant current circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a constant current circuit, for example, an MO
The present invention relates to a technique which is effective when used in a constant current circuit that is composed of an SFET (insulated gate type field effect transistor) and forms a minute constant current.

[Background technology]

Generally, the static current equation of MOSFET is approximated by the following equation (1).

I = W / L × (Vgs-Vth) ² (1) where W is the channel width of the MOSFET, L is the channel length, Vgs is the gate-source voltage, and Vth is the threshold voltage.

As is clear from the above equation (1), in order to set the current I small, the channel width W is set small, the channel length L is set large, and the gate-source voltage Vgs is set small. However, firstly, the channel width W
When is smaller, the error of the channel reduction amount, which is a device parameter of the Fitting model, becomes large. Secondly, in increasing the channel length L,
Naturally, the layout area increases. Third,
When the gate-source voltage Vgs is reduced, the MOSFET operates in the weak inversion region, and the accuracy in this region is poor and the error increases.

For example, a small constant current is required in the following digital telephone. In a digital telephone, a voice signal is converted into a pulse signal and transmitted. In this case, since the transmitted signal contains the echo component in addition to the main pulse, an equalizer is used to remove it. This equalizer forms an equalized signal by forming an echo component and subtracting it from the transmitted pulse signal. In order to configure such an equalizer, a voltage generation circuit for canceling the echo component is required. In this case, in order to perform highly accurate equalization, a voltage corresponding to a multi-order echo component is formed, so it is necessary to form a highly accurate controlled minute voltage that does not have power supply voltage dependency or the like. It will be.

Therefore, the inventor of the present application uses a negative feedback circuit using a differential amplifier circuit to form a positive and negative polar current whose current value is controlled in absolute value, and extracts the difference current as an output current. I thought about it.

As an example of a constant current circuit using a differential amplifier circuit, there is JP-A-55-59515.

[Object of the Invention]

An object of the present invention is to provide a constant current circuit capable of forming a minute constant current controlled with high accuracy.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
A constant current MOSFET Q2 composed of a first conductivity type MOSFET and a second conductivity type MOSFET Q3 are connected in series so that the drain voltage of the MOSFET Q3 becomes the midpoint potential of the operating voltage supplied between the sources of the MOSFETs Q2 and Q3. A differential amplifier circuit that controls the gate voltage of MOSFET Q3 is provided so that both MOSFETs Q2 and
Q3 and two current mirror type MOSFETs with different size ratios are connected in series and the difference between them is used as the output current.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a constant current circuit according to the present invention. Although not particularly limited, each circuit element in the figure is formed on a semiconductor substrate such as one single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. N-channel MOSF
ET is a source region formed on the surface of the semiconductor substrate,
The gate electrode is made of polysilicon and is formed on the surface of the semiconductor substrate between the drain region and the source region with a thin gate insulating film interposed therebetween. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. by this,
The semiconductor substrate has a plurality of N channels formed thereon.
Constructs a common substrate gate for MOSFETs. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. The substrate gate of the N-channel MOSFET, that is, the semiconductor substrate is set to the ground potential of the circuit, and the P-channel MO
The substrate gate of the SFET, that is, the N-type well region, is coupled to the power supply terminal Vcc in FIG.

The N-channel MOSFET Q1 forms a reference constant current I1. That is, the fixed resistance R is provided between the drain of the MOSFET Q1 and the power supply voltage Vcc, although not particularly limited thereto. The drain voltage of the MOSFET Q1 is supplied to the non-inverting input terminal (+) of the differential amplifier circuit (operational amplifier circuit) OP1. The inverting input terminal (-) of this differential amplifier circuit OP1 is
For example, the constant voltage Vcc-Vref is supplied. The differential amplifier circuit
The output voltage of OP1 is supplied to the gate of the MOSFET Q1.
The operational amplifier circuit OP1 supplies an output voltage such that the drain voltage of the MOSFET Q1 becomes equal to the constant voltage Vcc-Vref.
Controls the conductance of MOSFET Q1. For example, the resistance R
If the voltage drop (I1 × R) at is higher than the constant voltage Vref, the output voltage of the differential amplifier circuit OP1 becomes low and the MOSFET Q1
Is shallowly biased to reduce the current I1 and the voltage drop (I1 × R) in the resistor R is lower than the constant voltage Vref,
The output voltage of the differential amplifier circuit OP1 becomes high and the MOSFET Q1 is deeply biased to increase the current I1. Due to the negative feedback loop of the differential amplifier circuit OP1, the MOSFET Q1
A constant current I1 as shown in the following equation (2) flows through the device.

I1 = Vref / R (2) Thus, the inverting input terminal (-) of the differential amplifier OP1
When a constant voltage Vref (Vcc-Vref) with reference to the power supply voltage Vcc is used for the above, the constant current I1 can be made independent of the fluctuation of the power supply voltage Vcc.

The same voltage as that of the MOSFET Q1 is supplied to the gate of the N-channel MOSFET Q2, so that, for example, if the size (W / L) is the same as that of the MOSFET Q1, the same constant current I1 is caused to flow, or the equal ratio of both MOSFETs Q1 and Q2. According to the above, a constant current will flow. A P-channel MOSFET Q3 is connected in series to the drain of the MOSFET Q2. In order to make the current I2 flowing through this MOSFET Q3 equal to the constant current I1 flowing through the above MOSFET Q2, the drain of MOSFET Q3 (connection point between MOSFETs Q3 and Q2)
The voltage is supplied to the non-inverting input terminal (+) of the differential amplifier circuit OP2 similar to the above. The midpoint voltage (Vcc / 2) of the operating voltage Vcc supplied between the sources of the MOSFETs Q2 and Q3 is supplied to the inverting input terminal (-) of the differential amplifier circuit OP2.

Due to the negative feedback effect of the differential amplifier circuit OP2 provided in the MOSFET Q3, the current I2 of the MOSFET Q3 is balanced so as to be equal to the constant current I1 of the MOSFET Q2. For example, if both currents have a relation of I2> I1, the drain voltage of the MOSFET Q3 is made higher than the midpoint voltage Vcc / 2, and therefore the output voltage of the differential amplifier circuit OP2 is made high. This enables P-channel MOSFET
Since Q3 is biased shallowly, its drain current I2 is reduced. On the other hand, if both currents have a relation of I1> I2, the above MO
Since the drain voltage of SFETQ3 is lower than the midpoint voltage Vcc / 2, the output voltage of the differential amplifier circuit OP2 is lowered. As a result, the P-channel MOSFET Q3 is deeply biased, so that its drain current I2 is increased. Due to the negative feedback operation of the differential amplifier circuit OP2, MOSFETs Q3 and Q3
The potential at the connection point of 2 (drain potential of MOSFETs Q2 and Q3) is always equal to the midpoint potential Vcc / 2 as the above reference. In other words, the current I2 flowing through the P-channel MOSFET Q3 flows through the N-channel MOSFET Q2. Control so that it becomes equal to the constant current I1.

In this embodiment, the positive and negative polar small constant currents ΔI
Constant current I1 (= I2) formed by the current balance circuit as described above is output via N-channel output MOSFETs Q4 ', Q4 "and P-channel MOSFET Q5. For example, P-channel MOSFET Q5. Is set to have the same size (W / L) as MOSFET Q3 (1: 1), so that the same current I2 flows.
Channel MOSFETs Q4 'and Q4 "have MOSF sizes
It is formed so as to differ from ETQ2 by ΔW / L. That is, the size of the MOSFET Q4 ′ that forms the positive minute current + ΔI is smaller than that of the MOSFET Q4 by ΔW / L, and the size of the MOSFET Q4 ″ for forming the negative minute current −ΔI is smaller than that of the MOSFET Q4. Is formed larger by ΔW / L.

Further, in order to form these minute signals at required timing, the source of the P-channel MOSFET Q5 has a low level such as the ground potential of the circuit formed by the CMOS inverter circuit N3 which receives the timing signal ▲ ▼ and the power supply voltage Vcc. Such a high level is supplied. Also,
The same high level and low level of the CMOS inverter circuit N1 that receives the timing signal UP are supplied to the source of the MOSFET Q4 ′, and the same high level of the CMOS inverter circuit N2 that receives the timing signal DW is supplied to the source of the MOSFET Q4 ″. Levels and low levels are supplied.

For example, when the timing signal (up signal) UP is set to the high level, the output signal of the inverter circuit N1 is set to the low level and the output signal of the inverter circuit N3 is set to the high level during that time, so that the currents in the MOSFETs Q5 and Q4 'are increased. I2 and I
1'flows. Since the size of the MOSFET Q4 ′ is smaller by ΔW / L, it is smaller than the current I2 of the MOSFET Q5 (current I1 of the MOSFET Q2) by ΔI according to the size. This allows
ΔI charges the capacitor C and raises its voltage Vc. On the other hand, when the timing signal (down signal) DW is set to the high level, the output signal of the inverter circuit N2 is set to the low level and the output signal of the inverter circuit N3 is set to the high level during that time, so that the currents in the MOSFETs Q5 and Q4 ″ respectively. I2 and
I1 ″ flows. The size of the MOSFET Q4 ″ is ΔW / L.
Is larger, so only ΔI according to its size is MOSFETQ5
Is larger than the current I2 (current I1 of MOSFET Q2). This causes ΔI to discharge the capacitor C and reduce its voltage Vc.

If the timing signals UP and DW are generated according to the reference time, the voltage Vc controlled stepwise can be formed. Such a voltage can be used as a voltage signal for canceling the line echo component in, for example, an A / D or D / A conversion circuit or an automatic equalizer for a digital telephone as described later.

FIG. 2 shows a block diagram of an embodiment in which the present invention is applied to a decision feedback type automatic equalizer in a line equalizer for a digital telephone.

The input signal BTIN including the echo component is applied to one input of the adder / subtractor circuit. A ternary level determination circuit LV is provided at the output of the adder / subtractor circuit to determine a positive pulse / negative pulse in order to identify a voice signal converted into a pulse signal of both positive and negative polarities. The output of the level determination circuit LV is used as an equalization signal output on the one hand and is taken in the shift register SR on the other hand.

The output signals of each stage delayed by the shift register SR are voltage generation circuits VG1 to V corresponding to the multi-order echo components.
Used to control G5. That is, since the echo component is generated only when a positive or negative pulse is input, if the content of the shift register SR is logical "1", each generates a voltage V1 to V5 approximated to the above echo component. . That is, as shown in FIG. 3, detection of multi-order echo components E1 to E5 (code interference) generated with respect to the main pulse M is performed in advance using, for example, a recursive filter. Then, the voltage approximated to the echo components E1 to E5 of each order
V1 to V5 are respectively formed using the minute constant current circuit shown in FIG.

Now, as shown in FIG. 3, when the main pulse M is a positive pulse and first becomes "1" and then continuously becomes "0", the shift register SR causes the "1" Since the signal is delayed, the echo component E1 of the input signal BTIN above
.. to E5, the voltage generating circuits (tap) sequentially operate to form the approximate voltages V1 to V5. Then, by subtracting the voltages V1 to V5 from the input signal BTIN by the adder / subtractor circuit, the echo components E1 to
The equalization operation for removing E5 will be performed.

For the negative input signal, the input sign (+, −) of the adder / subtractor circuit is switched, in other words, the voltages V1 to V5 are added to the input signal BTIN, thereby substantially The same equalization operation is performed.

In this embodiment, in the voltage generating circuit VG5 such as the fifth tap, the corresponding echo component E5 is naturally
Since the level of V5 becomes as small as several tens of mV, it is possible to form a highly accurate voltage V5, etc., which is approximated to high accuracy, by using the voltage generation circuit that uses the above-mentioned highly accurate minute current, so that highly accurate equalization operation is performed. Is something that can be done.

〔effect〕

(1) Using a differential amplifier circuit, a first conductivity type constant current MOSF
By controlling the gate voltage of the second conductivity type MOSFET so that the drain voltage of the second MOSFET directly connected to ET becomes equal to the midpoint potential of the operating voltage, the currents of both MOSFETs are made equal. it can. An effect that an output MOSFET having a size ratio different from those of the above MOSFETs is provided and a highly accurate constant current corresponding to the size ratio can be obtained is obtained.

(2) By setting the difference between the size ratios of both MOSFETs corresponding to the above (1) to be small, it is possible to obtain an effect that a minute constant current set with high accuracy can be obtained.

(3) Since it is possible to form a highly accurate minute current by the above (2), it is possible to form a voltage having high resolution by charging or discharging the capacitor. .

(3) As the first conductivity type constant current MOSFET, a differential amplifier circuit is used to form a reference constant current by controlling the gate voltage so that the drain voltage becomes a constant constant voltage. It is possible to obtain the effect of being able to obtain a constant current set with high accuracy in terms of value.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, in FIG. 1, the voltage supplied to the resistor R for forming the reference constant current may be a predetermined constant voltage other than the power supply voltage Vcc.
The resistor R may be an external component of the semiconductor integrated circuit device. In addition, P-channel MOSFET and N-channel MOSFET
You may reverse and. In this case, the polarity of the operating voltage may be reversed. The circuit that forms the reference constant current may be any circuit other than the circuit that uses the feedback circuit of the differential amplifier circuit. In addition, in Fig. 1, when a steady constant current is obtained, the source of MOSFET Q5 is set to the power supply voltage.
Connected to Vcc, one of MOSFET Q4 'or Q4 "is selectively provided and its source is connected to the ground potential of the circuit.
The size ratio of the MOSFETs Q3 and Q5 and the size ratio of Q2 and Q4 ', Q4 "are variously changed according to the constant current to be output.

The output voltage shown in FIG. 1 can be used for offset cancellation of the operational amplifier circuit. Normally, in the operational amplifier circuit, an output signal is generated even if the pair of input levels are equal to each other. This occurs because, for example, the operational amplifier circuit includes a differential amplifier circuit, and the characteristics of pair elements, such as MOSFETs, that constitute the differential amplifier circuit do not match due to variations in manufacturing conditions. For such offset removal, the output voltage Vn shown in FIG. 1 can be used. That is, since the offset is usually a minute voltage of several tens of mV, a minute voltage corresponding to this offset voltage is formed and supplied to the input terminal to which the reference potential of the operational amplifier circuit is supplied. As a result, the offset can be offset.

[Field of application]

The present invention can be widely used as a circuit that forms a constant current.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a constant current circuit showing an embodiment of the present invention, and FIG. 2 is an embodiment when the present invention is applied to a decision feedback automatic equalizer in a line equalizer for digital telephones. FIG. 3 is a block diagram showing an example, and FIG. 3 is a waveform diagram for explaining the operation. OP1, OP2, OP3 ... Operational amplifier circuit, VC ... Voltage comparison circuit, L
V: 3-value level judgment circuit, SR: shift register, VG1
~ VG5 ... Voltage generator

Claims (1)

(57) [Claims] 1. A constant current circuit provided in an equalizer for removing an echo component included in a transmission signal based on a voltage corresponding to the echo component, and for forming the voltage by charging and discharging a capacitor. , A first conductivity type first MOSFET (Q1) having a drain connected to the resistance means (R), the drain of the first MOSFET (Q1) is connected to the non-inverting input terminal, and the reference voltage is supplied to the inverting input terminal. And a differential amplification output connected to the gate of the first MOSFET (Q1) so that the current flowing through the resistance means (R) becomes a constant current. A circuit (OP1) and a second MOS of the first conductivity type having a gate and a source connected to the gate and the source of the first MOSFET (Q1), respectively.
A second conductive type third MOSFET (Q3) having a drain connected to the drain of the second MOSFET (Q2), a drain of the third MOSFET (Q3) connected to a non-inverting input terminal, The source of the above-mentioned MOSFET and the above-mentioned
The midpoint voltage of the power supply voltage supplied to the source of the 3MOSFET (Q3) is supplied, and the differential amplification output is output from the 3rd MOSFET (Q3).
3) A second differential amplifier circuit (OP2) connected to be supplied to the gate of the second MOSFET (Q2), and a gate and a source connected to the gate and the source of the second MOSFET (Q2), respectively. Q
2) 1st conductivity type 4th MOSFET (Q
4 ′) and a gate and a source connected to the gate and the source of the third MOSFET (Q3), respectively.
3) A fifth MOSFET (Q5) of the second conductivity type having the same size, and a gate and a source connected to the gate and the source of the second MOSFET (Q2), respectively.
2) Larger size of 1st conductivity type 6th MOSFET (Q
4 ″) and the first timing signal (UP) for forming a minute current to the input terminal, and the output terminal connected to the source of the fourth MOSFET (Q4 ′), the first inverter circuit (N1), The second timing signal (DW) for forming a minute current is supplied to the input terminal, the output terminal is connected to the source of the sixth MOSFET (Q4 ″), and the second inverter circuit (N2) is connected to the input terminal. An inverted signal of the sum of the first timing signal (UP) and the second timing signal (DW) is supplied, and the output terminal is connected to the source of the fifth MOSFET (Q5).
An inverter (N3) is provided, and the drain of the fourth MOSFET (Q4 '), the drain of the fifth MOSFET (Q5) and the sixth MOSFET (Q
4 ″) charging and discharging of the capacitor coupled to a common connection node with the drain of the first timing signal (UP)
And a constant current circuit characterized by being controllable based on the second timing signal (DW).