JPS6229315A - Switch circuit - Google Patents

Abstract

PURPOSE:To reduce the DC on-resistance by providing a CMOS inverter inputting a logic signal to the pre-stage and a resistive impedance whose one end is connected to the output of the post-stage of the CMOS inverter and whose other end is connected to an output terminal. CONSTITUTION:Both positive and negative power terminals of CMOS inverters connected in ascade are connected to different stabilized reference power supplies VREF1-VREF4, a logic signal L is inputted to the pre-stage and one end of a resistive impedance Z is connected to the output of the post-stage and a signal V0 is outputted from the other terminal of the resistive impedance Z. At least one of positive and negative terminals of the CMOS inverters is connected to a different stabilized power supply. Thus, a switch circuit having a sufficiently small DC on-resistance while having a minimum operating power voltage the same degree as that of a conventional circuit and transistors with a realistic size is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention uses a switch circuit, particularly a CMOS inverter, to connect one end of a resistive impedance to one end of a positive or negative regulated reference power supply according to a logic input signal, and connect the other end to a positive or negative regulated reference power supply. This invention relates to a switch circuit that takes out an output signal from an end.

[Conventional technology]

Conventionally, this type of switch circuit has been constructed as shown in FIG. In this circuit, the resistors R1 to Rn are connected to the positive power source Votz or the stabilized power source V according to the logic input signals Lt to Ln.
*tp*, and the level of Va, that is, the level of Vo, is determined by the combination of the logic input signal L+''Lx.For example, when the logic input signal 1 is high (low) level, one end of the resistor R1 is connected to the positive power supply. Voo (Stabilized power supply V*
tpa). The same applies to the resistance RTI. When the logic input signal L1 is at a high level, L1=1, and when it is at a low level, L+=O (the same applies to other logic input signals), then the voltage vO is expressed by the following equation.

(1) Normally, an emitter follower bipolar transistor B1 is added to take power from the output Vo, and the output Vout is taken out from its emitter node. In reality, the resistors R1 to Rn are connected to the P-channel MOS transistor P4 depending on whether the logic input signal L+"Ln is 1 or O.
．． P6 or N-channel MO3) transistor N4.
The on-resistance of N6 is added in series. The DC on-resistance ROM of the MoS transistor is expressed by the following equation.

(Non-saturation region)...(2) Here, Vas is the gate-to-source voltage, Vos is the drain-source voltage, β is the current gain, and V is the threshold voltage. (2) As can be seen from equation (3), DC on-resistance RO
M changes greatly with the gate-source voltage VG5.

DC on-resistance ROM due to fluctuations in power supply voltage Voo
N-channel MO5) transistor N3. N4. The sources of NS and N6 are connected to the stabilizing reference voltage @ VRAN EF 4. As a result, N-channel and P-channel MOS transistors 23 to P6. Gate-source voltage va of N3 to N6
When s is on, I Vas l = l VDn −
VREF l = 2 VBE (Vnghahe-7,
The voltage between the a x me and the 7 terminals is stabilized.

[Problems to be Solved by the Invention] The conventional switch circuit described above has the following drawbacks. In this circuit, it is necessary that VREF4 > VBEI under the condition that the output VOOT is not clamped to ground, and therefore the minimum operating power supply voltage jf Vo
o=”i*tpa+Vatz+VBE3=
VBEI +Vng2+ VBE3 == 3 Va
If it is made smaller (Vat) - VREF4), the minimum operating power supply voltage will be lowered.

On the other hand, when the transistors are turned on, the transistors 23 to P6
．． Gate-source voltage IVC of N3 to N6! + is (V
aD-VREF 4) From equations (2) and (3), when the gate-to-source voltage 1Vasl is reduced, the DC on-resistance RoN increases, and the error with respect to the output Vo increases. In severe cases, a device that should originally operate in a non-saturated region enters the saturated region, or even turns off, and ceases to function as a switch. Generally speaking, the current gain β of a P-channel transistor is smaller than that of an N-channel transistor, and the controllability of the threshold voltage Vt is poor, so the DC on-resistance RO
The minimum value of (Voo −VII+tp 4) resulting from the limit of M is determined from the P-channel transistor. Also,
To reduce (VDD - VRtp a) to some extent,
The size W/L of the P-channel transistor becomes unrealistically large, leading to an increase in chip area when integrated into an IC.

In order to reduce the DC on-resistance ROM of the P-channel transistor, it is possible to increase (Van - VREpa), but in that case, the minimum operating reference voltage will increase. If a power supply is used, the minimum operating power supply voltage will be as high as 4 VBE.

[Means for solving problems]

In the switch circuit of the present invention, an input terminal to which a logic signal is input and an output terminal are connected in cascade, at least one of the positive or negative power supplies is connected to a different stabilizing reference power supply, and the logic signal is input to the previous stage. One end is connected to the CMOS inverter and the output of the latter stage of the CMOS inverter,
The other end has a resistive impedance connected to the output terminal.

In this way, by connecting at least one of the positive or negative power supplies of a CMOS inverter to a different stabilized power supply, when the logic input signal is at one level, the gate-source voltage increases and the DC on-resistance RON increases. becomes smaller.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1, FIG. 2, and FIG. 3 respectively show the first switch circuit of the present invention. FIG. 4 is a circuit diagram of second and third embodiments.

In the first embodiment, a cascaded CMO
Before the S inverter (P channel transistor Pl
and an N-channel transistor Ml), and a stabilized reference power supply vIIεPI which is different from the positive power supply and negative power supply of the subsequent stage (consisting of a P-channel transistor P2 and an N-channel transistor N2).

VREF2, ``l*tp3. .

In a second embodiment, a cascaded CMO
Only the negative power supply of the S inverter, and in the third embodiment only the positive power supply, is connected to the stabilized reference power supply.

FIG. 4 is a specific circuit diagram of the second embodiment.

The positive power supply of the CMOS inverter is connected to the common power supply Voo. The reference power supply has two stabilized reference potentials VRgp.
3 and ``It wry 4, and the negative supply before the cascaded inverter is connected to a low reference voltage source vR.
In the third stage, the negative power supply of the subsequent stage is a high reference voltage source V* EP a
It is connected to the.

In this circuit, the P-channel transistor P4 of the inverter in the subsequent stage. When PK is on, the previous stage N-channel transistor N3. MS is on, and P-channel transistor P4. The gate-source voltage of PK is l Vcs l = Vng2+ Vsv, 3+V
BE4 = 3 Vnt tear, conventional circuit cy) lV
DC on-resistance RO is sufficient compared to asl = 2Vm.
M can be made smaller. On the other hand, N-channel transistor
Ha.

The gate-source voltage IVasi when NG is on is the same as the conventional circuit, but compared to a P-channel MOS transistor, the current gain β is larger and the threshold voltage V
By stably controlling τ to a low value, a sufficiently small DC on-resistance ROM can be obtained. The minimum operating power supply voltage for this circuit is 3 VB! It is.

Note that the resistive impedance Z does not necessarily have to be a pure resistance, and may of course be one having an appropriately biased source-drain characteristic Vos/IDs of a MOS transistor.

〔Effect of the invention〕

As explained above, by connecting at least one of the positive or negative power supply of a CMOS inverter to a different stabilized power supply, the present invention has a minimum operating power supply voltage comparable to that of conventional circuits and transistors of realistic size. However, it has the effect of realizing a switch circuit with a DC on-resistance that is sufficiently smaller than that of conventional circuits.

[Brief explanation of the drawing]

1, 2, and 3 are circuit diagrams of the first, second, and third embodiments of the switch circuit of the present invention, respectively, and FIG. 4 is the circuit diagram of the second embodiment of the switch circuit of the present invention.
FIG. 5 is a circuit diagram of a conventional example. Voo...Positive power supply, Vss...Negative power supply, VREPI, VREF2, Thzp3. Vo
ip4...Stabilized power supply, L, L+ -Ln...Input terminal. Vo, Vo+yt - output terminal. P+ "PK...P channel MOS transistor, N+" NG...N channel MOS transistor, 81~B4...Bipolar NPN) transistor, P+
"Rn, RL - resistance. Z... resistive impedance. Patent applicant NEC Corporation Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] An input terminal to which a logic signal is input, an output terminal, a CMOS inverter which is cascade-connected, at least one of the positive or negative power supplies is connected to a different stabilized reference power supply, and a logic signal is input to the previous stage; A switch circuit that has a resistive impedance with one end connected to the output of the subsequent stage and the other end connected to the output terminal.