JPS63241955A - Manufacture of resin-reinforced lsi mounting structure - Google Patents
Manufacture of resin-reinforced lsi mounting structureInfo
- Publication number
- JPS63241955A JPS63241955A JP7409387A JP7409387A JPS63241955A JP S63241955 A JPS63241955 A JP S63241955A JP 7409387 A JP7409387 A JP 7409387A JP 7409387 A JP7409387 A JP 7409387A JP S63241955 A JPS63241955 A JP S63241955A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- lsi
- mounting structure
- mounting board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000011347 resin Substances 0.000 claims abstract description 60
- 229920005989 resin Polymers 0.000 claims abstract description 60
- 239000007788 liquid Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 35
- 238000001514 detection method Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 230000008569 process Effects 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004744 fabric Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000011342 resin composition Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000003749 cleanliness Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000007872 degassing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、LSI実装構造体の製造方法に係り、特に、
フリップチップ実装され、樹脂補強されてなる実装構造
体の改良された製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing an LSI mounting structure, and in particular,
The present invention relates to an improved method of manufacturing a mounting structure that is flip-chip mounted and reinforced with resin.
LSIチップを実装基板上に複数個の電気的接合点を介
して実装してなるLSI実装構造体は、チップ上の集積
回路数の増加に伴なって、多数の接合点を有する様にな
っている。そのため、第4面に示す様に、LSIチップ
面全体に亘って接合点を形成し得るフリップチップ接合
されたLSI実装構造体が検討されている。この場合、
接合点は、低触点合金いわゆる半田柱が用いられるが、
これら合金類は腐食や酸化が比較的起り易いためこれら
から保護するための手段が用いられるのが普通である。LSI mounting structures, which are formed by mounting an LSI chip on a mounting board via a plurality of electrical junctions, have come to have a large number of junctions as the number of integrated circuits on the chip increases. There is. Therefore, as shown in the fourth page, a flip-chip bonded LSI mounting structure that can form bonding points over the entire LSI chip surface is being considered. in this case,
The connection point is a low contact point alloy so-called solder pillar,
Since these alloys are relatively susceptible to corrosion and oxidation, it is common to take measures to protect them from corrosion and oxidation.
その場合、この様な実装構造体全体をハーメチックなパ
ッケージに収納して保護する手段を取る以外は、樹脂に
よる保護に頼らざるを得ない。樹脂による保護は非常に
簡便であり、比軟的適正な価格でこの種実装構造体を提
供し得る点で有用である。In that case, unless the entire mounting structure is housed and protected in a hermetic package, protection by resin must be relied upon. Protection with resin is very simple and is useful in that this type of mounting structure can be provided at a relatively reasonable price.
しかるに、防食、酸化防止を目的とする以上、接合点が
点在しているLSIチップと実装基板とで作る間隙には
、樹脂を完全に充填する必要があるものかわからず、多
くの場合に、完全な充填が出来ない状態が生ずる。However, since the purpose is to prevent corrosion and oxidation, it is not clear whether it is necessary to completely fill the gap between the LSI chip and the mounting board, which are dotted with bonding points, with resin, and in many cases , a situation occurs where complete filling is not possible.
これまで提案されてきた例を以下に紹介するがいずれも
プロセスが煩雑であったり、特定のデバイスにのみ適用
可能であるなど実用性の点で多くの問題を残している。Examples of the methods proposed so far are introduced below, but all of them have many problems in terms of practicality, such as complicated processes or being applicable only to specific devices.
まず、第3図の様に実装基板側のLSIチップと対向す
る面内に貫通孔を設け、そこから液状樹脂を注入、充填
する方法の提案がある。しかし、高集積化されたLSI
チップでは、接合点も高密度にチップ全面に分布するこ
とになり、所望の貫通孔を実装基板上に設けることが実
質上難しくなる。また、実装基板も高密度の多層化され
た配線群を有するため、それを避けて貫通孔を設けるこ
とには大きな困難が伴なう。従って、この方法は、接合
点の少ないLSIチップを実装した場合に限って適用し
得る。但し、ガラス基板などの場合は。First, a method has been proposed in which a through hole is provided in the surface facing the LSI chip on the mounting board side as shown in FIG. 3, and liquid resin is injected and filled through the through hole. However, highly integrated LSI
In a chip, the junction points are also distributed at high density over the entire surface of the chip, making it substantially difficult to provide desired through holes on the mounting board. Furthermore, since the mounting board also has a group of high-density multilayer wiring, it is very difficult to avoid this and provide through holes. Therefore, this method is applicable only when an LSI chip with few junctions is mounted. However, in the case of glass substrates, etc.
貫通孔がガラスクラックの発生点になるなどの不都合が
生ずる為実用性に乏しい。This method is impractical because the through hole becomes a point where glass cracks occur.
次に、間隙に充てんする困難さを回避するため、第4図
の様に、LSIチップ実装前に、実装基板上に液状樹脂
を載置し、その上からLSIチップを押し付けて、接合
させる方法が提案されている。Next, in order to avoid the difficulty of filling the gap, as shown in Figure 4, before mounting the LSI chip, liquid resin is placed on the mounting board, and the LSI chip is pressed onto it to bond it. is proposed.
この方法は、接合に用いられる半田の接合温度で樹脂が
著しく変質しないことが前提条件となる。The prerequisite for this method is that the resin does not change significantly at the bonding temperature of the solder used for bonding.
LSIチップ接合に汎用されている95%pb−5%S
nあるいは60%Pb−40%Sn合金は、最高温度2
00〜300℃で用いられる。この温度は、多くの未硬
化の樹脂にとっては苛酷であり変質の回避は困難である
。また、用いる樹脂によっては、フリップチップ接合特
有のセルファライン機能を阻害する恐れもあり、位置合
せなどに新たな困難が伴なうことになる。95%pb-5%S commonly used for LSI chip bonding
n or 60%Pb-40%Sn alloy has a maximum temperature of 2
Used at 00-300°C. This temperature is harsh for many uncured resins, and it is difficult to avoid deterioration. Moreover, depending on the resin used, there is a possibility that the self-line function peculiar to flip-chip bonding may be inhibited, and new difficulties will arise in alignment and the like.
これに対し、比較的オーツドックスな方法として、第5
図の様に、フリップチップ接合後、チップ端面から、毛
細管現象を利用して充てんして行く方法が特開昭60−
147140号公報にて提案された。On the other hand, as a relatively orthodox method, the fifth
As shown in the figure, after flip-chip bonding, there is a method of filling the chip from the end surface using capillary action.
It was proposed in Publication No. 147140.
この方法は、上述の2案よりは実用性が高いものの樹脂
によっては満足した結果が得られないことも多い。特に
、無機粉末などを多量に配合した高粘度の樹脂では流動
性に乏しく充てん不良が生ずることが多く、適用樹脂が
限られてしまうことになる。また、LSIチップ及び実
装基板の清浄度に左右される要素が多く、プロセス条件
に余裕が乏しく、充てん完了までにかなりの時間がかか
るなど量産に適用するには多くの困難が伴なう。またチ
ップサイズが大きくなればなるどボイドのない充てんを
行なうことが難しくなる。Although this method is more practical than the above two methods, it often does not provide satisfactory results depending on the resin. In particular, high viscosity resins containing a large amount of inorganic powder etc. have poor fluidity and often cause filling defects, which limits the range of applicable resins. In addition, there are many factors that depend on the cleanliness of the LSI chip and the mounting board, there is little margin for process conditions, and it takes a considerable amount of time to complete filling, making it difficult to apply to mass production. Furthermore, as the chip size increases, it becomes more difficult to perform void-free filling.
本発明は、これら従来技術の欠点を克服すべくなされた
もので、より簡便な樹脂充てん法を提供しようとするも
のである。The present invention has been made to overcome these drawbacks of the prior art, and is intended to provide a simpler resin filling method.
上記従来技術は、いずれも実用プロセスとして適用する
に足るだけの要件をすべて備えておらず何らかの欠点を
有している。これらの中では、毛細管現象を利用して充
てんする第3の方法が、従来汎用されてきたLSIチッ
プ、実装基板をそのま\使泪できる点、従来の実装構造
体製造プロセスを踏襲できる点で最も有用と考えられる
。しかし乍ら、充てんに時間を要する、樹脂の流動性に
関する物性の制約がある、LSIチップ及び実装基板の
清浄度の影響を受は易いなどの問題があり。None of the above-mentioned conventional techniques has all the requirements sufficient to be applied as a practical process and has some drawbacks. Among these, the third method of filling using capillary action has the advantages of being able to use conventionally widely used LSI chips and mounting boards as they are, and of being able to follow the conventional mounting structure manufacturing process. Considered the most useful. However, there are problems such as the time it takes to fill, the physical property restrictions regarding the fluidity of the resin, and the fact that it is easily affected by the cleanliness of the LSI chip and the mounting board.
量産性に乏しい面をもっている。It has the disadvantage of not being suitable for mass production.
これら従来技術の持つ欠点を克服し、真に量産性にすぐ
れた樹脂充てんLSI実装構造体の製造方法を提供する
のが本発明の主たる目的である。The main object of the present invention is to overcome these drawbacks of the prior art and to provide a method for manufacturing a resin-filled LSI mounting structure that is truly suitable for mass production.
また、樹脂充てんの良否を樹脂硬化前にチェックし得る
充てん検査工程を含む製造プロセスを提供することも本
発明の目的である。Another object of the present invention is to provide a manufacturing process that includes a filling inspection step in which the quality of resin filling can be checked before resin curing.
上記した本発明の目的は1次の様にして達成される。 The above objects of the present invention are achieved in the following manner.
まず、通常の工程でシリコンチップ(1)を実装用基板
(2)上にフリップチップ実装され実装構造体(5)を
得る。しかる後に、硬化後に所望の特性を示す液状の樹
脂(3)が、第1図(a)。First, a silicon chip (1) is flip-chip mounted on a mounting substrate (2) in a normal process to obtain a mounting structure (5). Thereafter, a liquid resin (3) exhibiting desired properties after curing is produced as shown in FIG. 1(a).
(b)の如く、シリコンチップ(1)周辺に切れ目なく
供給、載置される。この工程は非常に重要で、樹脂は、
シリコンチップ(1)周縁部と実装用基板(2)のシリ
コンチップが実装されている周辺部とに接触しシリコン
チップと実装用基板(2)とが作る間隙を完全に閉じて
いることが肝要である。供給される樹脂はあらかじめ脱
気しておいても良い。As shown in (b), the silicon chip (1) is supplied and placed around the silicon chip (1) seamlessly. This step is very important, and the resin
It is important that the periphery of the silicon chip (1) and the periphery of the mounting substrate (2) on which the silicon chip is mounted come into contact with each other to completely close the gap created between the silicon chip and the mounting substrate (2). It is. The resin to be supplied may be degassed in advance.
次に、これを第1図(c)の様に回転真空ポンプ(7)
のついた減圧容器(9)に入れ減圧状態を作る。回転真
空ポンプ(7)で達成し得る減圧状態で十分であるが、
具体的には20〜10Torr。Next, connect this to the rotary vacuum pump (7) as shown in Figure 1(c).
Place it in a vacuum container (9) with a mark to create a vacuum state. Although a reduced pressure state that can be achieved with a rotary vacuum pump (7) is sufficient,
Specifically, 20 to 10 Torr.
好ましくは10ミリTorr以下がよい。この工程で、
#脂からの脱気及びシリコンチップと実装用基板(2)
が作る間隙からの脱気が行なわれる。Preferably it is 10 milliTorr or less. In this process,
# Deaeration from fat, silicon chip and mounting board (2)
Air is removed from the gap created by the
間隙からの脱気を容易にするため、樹脂の粘性を下げる
目的で実装構造体(5)全体が熱体(8)によって加温
されることもあるが、この際の加温条件は50〜80℃
が適当である。In order to facilitate degassing from the gap, the entire mounting structure (5) may be heated by a heating element (8) in order to lower the viscosity of the resin, but the heating conditions at this time are 50 to 50℃. 80℃
is appropriate.
次に、回転真空ポンプ(7)を止め、加圧する工程に入
る。加圧するための媒体としては空気。Next, the rotary vacuum pump (7) is stopped and a pressurizing process begins. Air is used as a pressurizing medium.
窒素ガス、アルゴンガス、ヘリウムガスなど不活性なガ
スを用いるのが適当である。この工程により1間隙と外
部との圧力差からチップ周辺部の樹脂が間隙に押し込ま
れ、樹脂充てんが完了する。It is appropriate to use an inert gas such as nitrogen gas, argon gas, or helium gas. Through this process, the resin around the chip is pushed into the gap due to the pressure difference between the gap and the outside, and resin filling is completed.
その後ただちに加熱硬化することも出来るが、その前に
充てん状態をチェックする工程をとるのが望ましい。若
し充てんが完全でなければ、工程をとめ、不良品を作り
続けることを未然に防止できるからである。勿論すべて
の実装構造体(5)について充てん状態をチックする必
要はない。ロット毎あるいは樹脂のロットが変わる毎に
数個チェックすれば十分である。充てん状態のチェック
には超音波探傷法が最も有効である。樹脂充てん後の実
装構造体(5)を水あるいは不活性なフッ素系媒体中に
浸せきし、超音波探傷を行なう。しかるのち、バッチ炉
あるいはベルト炉を用いて加熱硬化しLSI実装構造体
が完成する6〔作用〕
本発明におけるLSI実装構造体製造プロセスによって
、ボイドのない樹脂充てんを可能とするのは、LSIチ
ップと実装基板とが作る間隙を減圧状態に保ちながら樹
脂充てんを行なう点にありかつ減圧状態を充てんすべき
樹脂によって保ちながら充てんを完了する点にある。こ
の作用により樹脂の流動性が悪い場合でもボイドが残ら
ない樹脂充てんが確実に行なわれる。Although it is possible to heat and harden immediately after that, it is preferable to take a step to check the filling state before that. This is because if the filling is not complete, the process can be stopped and the continued production of defective products can be prevented. Of course, it is not necessary to check the filling state of all mounting structures (5). It is sufficient to check several items for each lot or each time the resin lot changes. Ultrasonic flaw detection is the most effective way to check the filling condition. The mounting structure (5) filled with resin is immersed in water or an inert fluorine-based medium, and ultrasonic flaw detection is performed. Thereafter, the LSI mounting structure is completed by heating and curing using a batch furnace or belt furnace.6 [Function] The LSI mounting structure manufacturing process of the present invention enables void-free resin filling of the LSI chip. The purpose of this method is to perform resin filling while maintaining a reduced pressure state in the gap formed between the mounting board and the mounting board, and to complete the filling while maintaining the reduced pressure state with the resin to be filled. This action ensures resin filling without leaving any voids even when the fluidity of the resin is poor.
例えば、樹脂充てんにより、実装構造体の冷熱サイクル
特性が向上するのは、樹脂の熱膨張係数が少なくとも接
合に用いている半田の熱膨張係数程度に小さいからであ
る。この場合、無機フィラーが重量比で樹脂成分のほぼ
2倍量加えられ、かなり粘稠な樹脂組成物となる。この
様な樹脂組成物を従来の方法で充てんしようとすると、
かなりの時間を要する上、温度管理などに厳しい条件を
設定しなけれればらず、それでも完全な充てんを行なえ
ない場合も生ずる。For example, filling with resin improves the thermal cycle characteristics of the mounted structure because the coefficient of thermal expansion of the resin is at least as small as the coefficient of thermal expansion of the solder used for bonding. In this case, the inorganic filler is added in an amount that is approximately twice the weight of the resin component, resulting in a fairly viscous resin composition. When attempting to fill such a resin composition using conventional methods,
Not only does it take a considerable amount of time, strict conditions such as temperature control must be set, but even then, complete filling may not be possible.
以下、本発明の効果を具体的に示すため、−実施例を第
1図に基づいて説明する。Hereinafter, in order to concretely demonstrate the effects of the present invention, an embodiment will be described based on FIG. 1.
〔実施例1〜12〕
接合用の半田接続部(4)を設けたシリコンチップ(1
)を通常の方法でアルミナ製の実装用基板(2)上にフ
リップチップ実装する。チップサイズは10nw++X
10nwn、厚さ0.55 mm、実装用基板(2)は
2Q +nm X 20閣、厚さ1mである。チップと
基板の間隙はほぼ100μmである。半田接続部(4)
はチップ面全体に分布し、224個存在する。これに、
第1表に示す組成の液状の樹脂(3)をそれぞれ第1図
(a)、(b)に示された如くに実装構造体(5)に裁
置する。次にこれらを第1図(c)の様な構成からなる
減圧装置(6)にセットし1回転真空ポンプ(7)を用
いて減圧容器(9)内で1ミリT orr程度まで減圧
にする。その際の加温条件は60℃程度とする。[Examples 1 to 12] A silicon chip (1) provided with a solder joint (4) for joining
) is flip-chip mounted onto an alumina mounting board (2) using a normal method. Chip size is 10nw++X
The mounting board (2) has a size of 2Q + nm x 20 mm and a thickness of 1 m. The gap between the chip and the substrate is approximately 100 μm. Solder connection (4)
are distributed over the entire chip surface, and there are 224 of them. to this,
Liquid resin (3) having the composition shown in Table 1 is placed on a mounting structure (5) as shown in FIGS. 1(a) and (b), respectively. Next, these are set in a pressure reducing device (6) constructed as shown in Fig. 1(c), and the pressure is reduced to about 1 milliTorr in the pressure reducing container (9) using a one-rotation vacuum pump (7). . The heating conditions at that time are approximately 60°C.
あらかじめ熱板(8)を加熱しておき、回転真空ポンプ
(7)を始動させる前に60℃程度の雰囲気となるよう
にしておく6回転真空ポンプ(7)で5〜10分脱気後
、バルブ(10)を閉じ、リークバルブ(11)を徐々
に開いて、常圧まで戻して行く。常圧まで戻す時間は1
〜3分程度である。Heat the hot plate (8) in advance and create an atmosphere of about 60°C before starting the rotary vacuum pump (7). After degassing for 5 to 10 minutes with the 6-rotation vacuum pump (7), Close the valve (10) and gradually open the leak valve (11) to return to normal pressure. Time to return to normal pressure is 1
It takes about 3 minutes.
完全に常圧に戻したのち、脱気槽から樹脂布てん実装構
造体(5)をとり出し1周辺の余分な樹脂を除去したの
ち、超音波探傷装置A T −5000(日立建機製)
を用い、充てん状態のチェックを行なう。水中に浸せき
し、25 M H’zの超音波探傷子を用いて測定する
。After completely returning to normal pressure, take out the resin fabric mounting structure (5) from the deaeration tank and remove excess resin around 1, then use ultrasonic flaw detection equipment A T-5000 (manufactured by Hitachi Construction Machinery).
Use to check the filling status. It is immersed in water and measured using a 25 MHz ultrasonic flaw detector.
そのあと、空気循環恒温槽を用いて、110℃で10時
間加熱した後、200℃で10時間加熱して樹脂硬化を
行ない、樹脂補強型実装構造体(5)が完成する。それ
ぞれ、10個ずつ作成し、樹脂布てん良品率を第1表に
示した。Thereafter, the resin is cured by heating at 110° C. for 10 hours and then at 200° C. for 10 hours using an air circulation constant temperature bath, thereby completing the resin-reinforced mounting structure (5). Ten pieces of each were made, and the quality of the resin fabrics is shown in Table 1.
〔比較例1〜12〕
実施例1〜12で用いたと同じ組成について、特開昭6
0−147140号公報に開示されている方法による樹
脂布てんを試みた。その結果、充てん良品率は第2表に
示す如くであった。[Comparative Examples 1 to 12] Regarding the same composition as used in Examples 1 to 12,
An attempt was made to produce resin cloth using the method disclosed in Japanese Patent No. 0-147140. As a result, the filling good product rate was as shown in Table 2.
実施例と比較例の対比から明らかな様に1本発明による
樹脂補強型LSI実装構造体は、すべての樹脂組成にお
いて高い良品率が得られており。As is clear from the comparison between Examples and Comparative Examples, the resin-reinforced LSI mounting structure according to the present invention has a high yield rate for all resin compositions.
公知の方法とは全く異なる機構によって樹脂布てんがな
されていることを示すものである。This shows that resin cloth tents are made by a mechanism completely different from known methods.
尚1本発明の目的を達成する類似の方法として。In addition, as a similar method to achieve the object of the present invention.
あらかじめ実装構造体(5)を減圧容器(9)内に設置
し、別途シリンダなどに充てんしておいた液状樹脂減圧
状態を維持したま−、チップ周辺部に切れ目なく供給し
たのち、常圧に戻すという工程をとることも可能である
が、若干装置が複雑になる。また、LSI実装構造体(
5)としては。The mounting structure (5) is placed in a vacuum container (9) in advance, and the liquid resin, which has been filled in a separate cylinder or the like, is maintained in a vacuum state, and after being seamlessly supplied around the chip, the pressure is reduced to normal pressure. It is also possible to take the step of returning it, but the equipment becomes somewhat complicated. In addition, the LSI mounting structure (
As for 5).
第7図の様に、チップ背面に放熱板(14)などの付加
物が付いたものに対しても本発明の方法は適用可能であ
る。As shown in FIG. 7, the method of the present invention is also applicable to a chip having an additional element such as a heat sink (14) on the back surface of the chip.
以上述べてきた様に、本発明の樹脂充てん法によれば、
歩留り良く樹脂補強型LSI実装構造体が得られ、低価
格で信頼性の高いLSI実装構造体を供給できることに
なる。As described above, according to the resin filling method of the present invention,
A resin-reinforced LSI mounting structure can be obtained with a good yield, and a highly reliable LSI mounting structure can be supplied at a low price.
第1図は本発明の製造方法を示すための図、第1図(a
)は実装構造体の平面図、第1図(b)は実装構造体の
立面図、第1図(Q)は減圧工程及び常圧工程を説明す
るための装置模式図、第2図は実装構造体の断面図、第
3図、第4図、第5図はいずれも従来の樹脂充てん法を
示すための説明図、第6図は本発明の製造方法の工程フ
ロー図。
第7図の本発明を適用した実装構造体の断面図である。
1・・・シリコンチップ、2・・・実装用基板、3・・
・樹脂、4・・・半田接続部、5・・・実装構造体、6
・・・減圧装置、7・・・回転真空ポンプ、8・・・熱
板、9・・・減圧容器。
10・・・バルブ、11・・・リークバルブ、12・・
・ノズ第1 図
茅4 固FIG. 1 is a diagram for showing the manufacturing method of the present invention, FIG.
) is a plan view of the mounted structure, FIG. 1(b) is an elevational view of the mounted structure, FIG. 1(Q) is a schematic diagram of an apparatus for explaining the depressurization process and the normal pressure process, and FIG. 3, 4, and 5 are all explanatory diagrams showing the conventional resin filling method, and FIG. 6 is a process flow diagram of the manufacturing method of the present invention. FIG. 8 is a sectional view of the mounting structure to which the present invention of FIG. 7 is applied. 1... Silicon chip, 2... Mounting board, 3...
・Resin, 4...Solder connection part, 5...Mounting structure, 6
... Pressure reduction device, 7 ... Rotary vacuum pump, 8 ... Hot plate, 9 ... Pressure reduction container. 10... Valve, 11... Leak valve, 12...
・Nozu No. 1 Fig. 4 Hard
Claims (1)
に係わる複数個の接合体が形成されてぃるLSIチップ
と実装基板とがフリツプチツプ接合されてなるLSI実
装構造体において、LSIチップと実装基板が作る間隙
に以下に示す工程を含む液状樹脂充填手段により樹脂を
充填してなることを特徴とする樹脂補強型LSI実装構
造体の製造方法。 (1)LSIチップと実装基板とをフリツプチツプ接合
する工程 (2)液状樹脂を該LSIチップの縁辺に沿つて全周に
該実装基板及び該LSIチップに接触する様に載置する
工程 (3)液状樹脂が載置された実装構造体を10ミリTo
rr以下の減圧状態に保つておく工程 (4)常圧以上の状態に戻す工程。 2、集積回路が形成され、かつ実装基板との電気的接合
に係わる複数個の接合体が形成されているLSIチップ
と実装基板とがフリツプチツプ接合されてなるLSI実
装構造体において、LSIチップと実装基板が作る間隙
に以下に示す工程を含む液状樹脂充填手段により樹脂を
充填してなることを特徴とする樹脂補強型LSI実装構
造体の製造方法。 (1)LSIチップと実装基板とをフリツプチツプ接合
する工程 (2)液状樹脂を該LSIチップの縁辺に沿つて全周に
該実装基板及び該LSIチップに接触する様に載置する
工程 (3)液状樹脂が載置された実装構造体を10ミリTo
rr以下の減圧状態に保つておく工程(4)常圧以上の
状態に戻す工程 (5)樹脂の充填状態を非破壊的に検査する工程。 3、樹脂の充填状態を検査する手段が超音波を用いた探
傷法である特許請求の範囲第2項記載の樹脂補強型LS
I実装構造体の製造方法。[Claims] 1. An LSI mounting structure in which an LSI chip on which an integrated circuit is formed and a plurality of bonded bodies related to electrical connection with the mounting board are flip-chip bonded to the mounting board. 1. A method for manufacturing a resin-reinforced LSI mounting structure, characterized in that a gap formed between an LSI chip and a mounting board is filled with resin by a liquid resin filling means that includes the following steps. (1) Step of flip-chip bonding the LSI chip and the mounting board (2) Step of placing liquid resin along the edge of the LSI chip so as to contact the mounting board and the LSI chip all around (3) The mounting structure on which the liquid resin is placed is 10 mm
Step (4) of maintaining the reduced pressure below rr; (4) returning the pressure to normal pressure or above; 2. In an LSI mounting structure in which an LSI chip on which an integrated circuit is formed and a mounting board is flip-chip bonded to a mounting board, on which a plurality of bonded bodies related to electrical connection with the mounting board are formed, the LSI chip and the mounting board are bonded together. A method for manufacturing a resin-reinforced LSI mounting structure, characterized in that a gap formed by a substrate is filled with resin by a liquid resin filling means including the following steps. (1) Step of flip-chip bonding the LSI chip and the mounting board (2) Step of placing liquid resin along the edge of the LSI chip so as to contact the mounting board and the LSI chip all around (3) The mounting structure on which the liquid resin is placed is 10 mm
Step of maintaining the reduced pressure below rr (4) Returning the pressure to normal pressure or above (5) Non-destructively inspecting the filling state of the resin. 3. The resin-reinforced LS according to claim 2, wherein the means for inspecting the filling state of the resin is a flaw detection method using ultrasonic waves.
I. Method for manufacturing a mounting structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62074093A JP2607877B2 (en) | 1987-03-30 | 1987-03-30 | Method for manufacturing resin-reinforced LSI mounting structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62074093A JP2607877B2 (en) | 1987-03-30 | 1987-03-30 | Method for manufacturing resin-reinforced LSI mounting structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63241955A true JPS63241955A (en) | 1988-10-07 |
JP2607877B2 JP2607877B2 (en) | 1997-05-07 |
Family
ID=13537225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62074093A Expired - Fee Related JP2607877B2 (en) | 1987-03-30 | 1987-03-30 | Method for manufacturing resin-reinforced LSI mounting structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2607877B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
US5892289A (en) * | 1996-04-22 | 1999-04-06 | Nec Corporation | Bare chip mounting structure and manufacturing method therefor |
US6094354A (en) * | 1996-12-03 | 2000-07-25 | Nec Corporation | Chip component mounting board, chip component mounting structure, and method of manufacturing chip component mounting board |
US6674178B1 (en) | 1999-09-20 | 2004-01-06 | Nec Electronics Corporation | Semiconductor device having dispersed filler between electrodes |
JP2011040512A (en) * | 2009-08-10 | 2011-02-24 | Murata Mfg Co Ltd | Method of manufacturing circuit board |
USRE43404E1 (en) * | 1996-03-07 | 2012-05-22 | Tessera, Inc. | Methods for providing void-free layer for semiconductor assemblies |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5411696A (en) * | 1977-06-27 | 1979-01-27 | Toshiba Corp | Sealing method of electronic components |
JPS58107641A (en) * | 1981-12-21 | 1983-06-27 | Seiko Keiyo Kogyo Kk | Sealing method for semiconductor device |
-
1987
- 1987-03-30 JP JP62074093A patent/JP2607877B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5411696A (en) * | 1977-06-27 | 1979-01-27 | Toshiba Corp | Sealing method of electronic components |
JPS58107641A (en) * | 1981-12-21 | 1983-06-27 | Seiko Keiyo Kogyo Kk | Sealing method for semiconductor device |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
USRE43404E1 (en) * | 1996-03-07 | 2012-05-22 | Tessera, Inc. | Methods for providing void-free layer for semiconductor assemblies |
US5892289A (en) * | 1996-04-22 | 1999-04-06 | Nec Corporation | Bare chip mounting structure and manufacturing method therefor |
US6094354A (en) * | 1996-12-03 | 2000-07-25 | Nec Corporation | Chip component mounting board, chip component mounting structure, and method of manufacturing chip component mounting board |
US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
US6163463A (en) * | 1996-12-06 | 2000-12-19 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection |
US6674178B1 (en) | 1999-09-20 | 2004-01-06 | Nec Electronics Corporation | Semiconductor device having dispersed filler between electrodes |
JP2011040512A (en) * | 2009-08-10 | 2011-02-24 | Murata Mfg Co Ltd | Method of manufacturing circuit board |
Also Published As
Publication number | Publication date |
---|---|
JP2607877B2 (en) | 1997-05-07 |
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