JPS63240040A - Manufacture of sample wafer - Google Patents

Manufacture of sample wafer

Info

Publication number
JPS63240040A
JPS63240040A JP7528087A JP7528087A JPS63240040A JP S63240040 A JPS63240040 A JP S63240040A JP 7528087 A JP7528087 A JP 7528087A JP 7528087 A JP7528087 A JP 7528087A JP S63240040 A JPS63240040 A JP S63240040A
Authority
JP
Japan
Prior art keywords
wafer
film
protrusions
group
dust
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7528087A
Other languages
Japanese (ja)
Inventor
Kazunari Ishikawa
一成 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP7528087A priority Critical patent/JPS63240040A/en
Publication of JPS63240040A publication Critical patent/JPS63240040A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To contrive to be able to obtain a group of protrusions of artificially adhered dust of a desired size, a desired number of pieces and in a uniform distribution state, by a method wherein, after a thin film consisting of an artificially adhered dust material and a resist film are laminatedly formed and patterned, the thin film is etched to form the group of protrusions. CONSTITUTION:Such a thin film 11 is an oxide film consisting of SiO2 and so on or a nitride film consisting of Si3N4 and so on is formed by coating on a wafer 10 by deposition and sputtering and a resist film 12 is formed on the film 11 to arrange and pattern a mask 13 having a fine tile-shaped pattern. After that, the desired sites of the film 11, which correspond to window opening sites 14, 14... of the film 12, are peeled and removed be an etching treatment and the remained resist film 12 is removed with an organic solvent and so on to form a group 15 of protrusions, which consist of the film 11, of a desired size, a desired number of pieces and in a uniform distribution state on the wafer 10. Thereby, sample waters 17 that the protrusions 16, 16... of the groups 15 of protrusions on the wafer 10 correspond to artificially adhered dust can be obtained.

Description

【発明の詳細な説明】 崖]ユj1)月l見 本発明はサンプルウェーハの製造方法に関し、詳しくは
半導体装置の製造において半導体つ工−ハ上に付着した
ゴミを検査する装置に使用されるサンプルウェーハの製
造方法に関するものである。
[Detailed Description of the Invention] The present invention relates to a method for manufacturing a sample wafer, and more specifically, to a method for manufacturing a sample wafer, and more specifically, to a method for manufacturing a sample wafer, and more specifically, a method for manufacturing a sample wafer, and more specifically, a method for manufacturing a sample wafer. The present invention relates to a wafer manufacturing method.

従漣ヱlL医 各種半導体装置は、単結晶シリコンからなる半導体ウェ
ーハ上に多数の半導体素子を一括して形成し、その後各
種工程を経て製造されるのが一般的である。このような
半導体装置の製造では、上記半導体ウェーハ上にゴミが
付着することは種々の支障をきたす原因となって好まし
くなく、定期的に半導体ウェーハ上のゴミ検査を行う必
要がある。
BACKGROUND OF THE INVENTION Various semiconductor devices are generally manufactured by forming a large number of semiconductor elements all at once on a semiconductor wafer made of single-crystal silicon, and then going through various steps. In the manufacture of such semiconductor devices, the adhesion of dust on the semiconductor wafer is undesirable as it causes various problems, and it is necessary to periodically inspect the semiconductor wafer for dust.

上記半導体装置の製造で使用されるゴミ検査装置は、散
乱光検出方式を採用しているものが一般的である。この
散乱光検出方式によるゴミ検査装置は、検査すべき半導
体ウェーハ上に一定波長の光、例えばレーザ光を照射し
、このレーザ光の照射により半導体ウェーハ上のゴミで
生じた散乱光を検出して、その散乱状態に基づいて上記
半導体ウェーハ上でのゴミの有無及びその状態を検知す
るものである。ところで、この種ゴミ検査装置では、半
導体ウェーハ上のゴミの状態に応じて所定の検出信号を
得るために初期条件を設定したり、或いは光学系装置の
経時的劣化を防止して検査感度を一定に維持するために
定期的に更正したりする必要がある。
The dust inspection apparatus used in the manufacture of the semiconductor devices described above generally employs a scattered light detection method. This dust inspection device using the scattered light detection method irradiates the semiconductor wafer to be inspected with light of a certain wavelength, such as laser light, and detects the scattered light generated by the dust on the semiconductor wafer by the irradiation of the laser light. The presence or absence of dust on the semiconductor wafer and its state are detected based on the scattering state of the dust. By the way, in this type of dust inspection equipment, initial conditions are set to obtain a predetermined detection signal depending on the state of dust on the semiconductor wafer, or inspection sensitivity is kept constant by preventing deterioration of the optical system equipment over time. It is necessary to periodically update it to maintain it.

そこで上記ゴミ検査装置では、初期条件の設定や更正に
ゴミ検査の標準とするサンプルウェーハなるものを使用
する。このサンプルウェーハは、半導体素子を形成して
いないが表面を鏡面研磨したウェーハ上に、ゴミ検査の
標準となる疑似的なゴミを付着させたもので、上記サン
プルウェーハの製造方法の従来例を第6図乃至第8図を
参照しながら説明する。まず第6図に示すように半導体
素子を形成していない単結晶シリコンのウェーハ(1)
を用意する。そして第7図に示すようにポリビニルトル
エン等の有機材料からなる粒径の均一な標準粒子(2)
(2)・・・をイソプロピルアルコール等の有機溶媒(
3)に定量混入した塗布液(4)を、上記ウェーハ(1
)にエアブラシ(5)により吹付ける。これにより第8
図に示すように疑似的なゴミとなる標準粒子(2)(2
)・・・をウェーハ(1)上に付着させたサンプルウェ
ーハ(6)が得られる。
Therefore, in the above-mentioned dust inspection apparatus, a sample wafer, which is a standard for dust inspection, is used for setting and correcting initial conditions. This sample wafer is a wafer on which no semiconductor elements are formed, but whose surface has been polished to a mirror finish, with simulated dust attached to it, which is the standard for dust inspection. This will be explained with reference to FIGS. 6 to 8. First, as shown in Figure 6, a single crystal silicon wafer (1) on which no semiconductor elements are formed.
Prepare. As shown in Figure 7, standard particles (2) of uniform particle size made of an organic material such as polyvinyltoluene
(2)... in an organic solvent such as isopropyl alcohol (
The coating liquid (4) mixed in a certain amount with the wafer (1) is applied to the wafer (1).
) with an airbrush (5). As a result, the 8th
As shown in the figure, standard particles (2) (2) become pseudo-dust.
)... is deposited on the wafer (1) to obtain a sample wafer (6).

(°シよ゛と る  占 ところで、半導体装置の製造でのゴミ検査において上述
したサンプルウェーハ(6)に要求される条件としては
、ウェーハ(1)上に付着する標準粒子(2)(2)・
・・の個数を容易に制御し得ること、上記標準粒子(2
)(2)・・・の分布状態が均一であること、及び標準
粒子(2)(2)・・・以外の異物が付着しないこと等
である。
By the way, the conditions required for the above-mentioned sample wafer (6) in dust inspection in the manufacture of semiconductor devices include standard particles (2) (2) attached to the wafer (1).・
The number of the standard particles (2) can be easily controlled.
)(2)... should be uniformly distributed, and foreign matter other than the standard particles (2)(2)... should not be attached.

しかし、前述したサンプルウェーハ(6)の従来製法で
は、エアブラシ(5)によるウェーハ(1)への塗布液
(4)の吹付は時、塗布液(4)の吹付は距離・角度・
噴出量や、上記塗布液(4)を組成する標準粒子(2)
(2)−・・と有機溶媒(3)との混合比等によって標
準粒子(2)(2)・・・のウェーハ(1)上での個数
及びその分布状態がばらついて再現性が低く、またエア
ブラシ(5)による吹付は時に周囲から異物を巻込んで
この異物がウェーハ(1)上に付着することがあり、前
述したサンプルウェーハ(6)に要求される条件を満足
させることは容易なことではなかった。
However, in the conventional manufacturing method of the sample wafer (6) described above, the coating liquid (4) is sprayed onto the wafer (1) by the airbrush (5) at a certain time, and the coating liquid (4) is sprayed at a distance, angle, or
Spray amount and standard particles (2) that compose the coating liquid (4)
The number and distribution state of standard particles (2) (2)... on the wafer (1) vary depending on the mixing ratio of (2) -... and the organic solvent (3), resulting in low reproducibility. In addition, spraying with an airbrush (5) sometimes involves foreign matter from the surroundings, and this foreign matter may adhere to the wafer (1), making it difficult to satisfy the conditions required for the sample wafer (6) described above. That wasn't the point.

また、標準粒子(2)(2)・・・を付着させるのはウ
ェーハ(1)の全面とは限らず、用途に応じては上記ウ
ェーハ(1)の一部、例えば半面のみに標準粒子(2)
(2)・・・を付着させてサンプルウ1−ハ(6)を作
製したい場合もあるが、この場合は、エアブラシ(5)
による塗布液(4)の吹付けでサンプルウェーハ(6)
を製作する従来方法では非常に困鰭であったという問題
もあった。
In addition, the standard particles (2) (2)... are not necessarily attached to the entire surface of the wafer (1), but depending on the application, the standard particles (2) (2)... may be attached to only a part of the wafer (1), for example, only one half of the wafer (1). 2)
(2) You may want to make sample wa 1-ha (6) by attaching..., but in this case, airbrush (5)
Sample wafer (6) is sprayed with coating liquid (4) by
The conventional method of producing fins also had the problem of extremely difficult fins.

そこで本発明の目的は、サンプルウェーハに要求される
条件を容易に満たす簡便な手段によるサンプルウェーへ
の製造方法を提供するにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing sample wafers using simple means that easily satisfies the conditions required for sample wafers.

m  “ ための一 本発明は前記問題点に鑑みて提案されたもので、表面を
鏡面研磨加工したウェーハ上に疑似的付着ゴミ材質の薄
膜及びレジスト膜を1aWI形成し、マスキングにより
このレジスト膜をパターン化した後、上記薄膜をエツチ
ングして所望の大きさ、個数及び分布状態の突起群を形
成したことにより前記目的を達成しようとするサンプル
ウェーハの製造方法である。
The present invention has been proposed in view of the above-mentioned problems, and involves forming a thin film of a pseudo-attached dust material and a resist film 1aWI on a wafer whose surface has been mirror-polished, and removing this resist film by masking. This is a method of manufacturing a sample wafer which attempts to achieve the above object by etching the thin film after patterning to form a group of protrusions of a desired size, number and distribution.

在且 本発明方法によれば、半導体装置製造におけるフォトリ
ソグラフィー技術によるバターニングを用いてウェーハ
上に形成した突起群が所望設定寸法の疑似的なゴミとな
り、この突起群での各突起の大きさ及び個数の制御が容
易で、且つ上記各突起の分布状態の設定が任意に行える
According to the method of the present invention, a group of protrusions formed on a wafer using patterning using photolithography technology in semiconductor device manufacturing becomes pseudo-dust with a desired set size, and the size of each protrusion in this group of protrusions is The number of protrusions can be easily controlled, and the distribution state of each of the protrusions can be arbitrarily set.

爽簸週 本発明に係るサンプルウェーハの製造方法の一実施例を
第1図乃至第5図を参照しながら説明する0本発明方法
の特徴は半導体装置の製造におけるフォトリソグラフィ
ー技術によるパターニングを使用したことにある。
An embodiment of the method for manufacturing a sample wafer according to the present invention will be explained with reference to FIGS. 1 to 5.The feature of the method of the present invention is that patterning by photolithography technology is used in the manufacture of semiconductor devices. There is a particular thing.

まず第1図に示すように半導体素子を形成していない単
結晶シリコンで、鏡面研磨処理したウェーハ(10)上
に、8102等の酸化膜やSi3N4等の窒化膜などの
薄ffl (1))を蒸着やスパッタリングにより被着
形成する。次に第2図に示すように上記薄膜(II)上
に感光性レジスト材を塗着させてレジスト膜(12)を
形成しパターニングする。このレジスト膜(12)のパ
ターニングは、第3図に示すようにレジストIll (
12)の上方に所望の例えば微小タイル状パターンを有
するマスク(13)を配置し、この状態で紫外線を照射
する。〕とにより上記レジス+−膜(12)をマスク(
]3)のパターンに応じて露光し、その上でレジス1−
膜(12)を現像処理することにより、未露光或いは露
光した所望部位を剥離することによって行われる。その
後第4図に示すようにレジスト膜(12)の窓明は部位
(14)  <14)・・・と対応する薄膜(1))の
所望部位・おエツチング処理により剥離除去し、更に残
存したレジスト膜(12)を有機溶剤等で除去して第5
図に示すようにパターン化した上記!股(1))からな
る所望の大きさ、個数及び分布状態の突起群(15)が
ウェーハ(10)上に形成される。このようにして、ウ
ェーハ(10)上の突起# (15)の各突起 (16
)  (16)・・・が疑似的な付着ゴミに相当するサ
ンプルウェーハ(17)が得られる。
First, as shown in Figure 1, a thin ffl film (1) such as an oxide film such as 8102 or a nitride film such as Si3N4 is coated on a mirror-polished wafer (10) made of single crystal silicon on which no semiconductor elements are formed. is deposited by vapor deposition or sputtering. Next, as shown in FIG. 2, a photosensitive resist material is applied onto the thin film (II) to form a resist film (12) and patterned. The patterning of this resist film (12) is performed as shown in FIG.
A mask (13) having a desired, for example, micro tile-like pattern is placed above the mask (12), and ultraviolet rays are irradiated in this state. ] The above resist+- film (12) is masked (
] 3), and then resist 1-
This is done by developing the film (12) and peeling off desired areas that are unexposed or exposed. Thereafter, as shown in Fig. 4, the window light of the resist film (12) was peeled off and removed by etching the desired part of the thin film (1) corresponding to the part (14) <14)... and the remaining part was removed. The resist film (12) is removed using an organic solvent, etc., and the fifth
The above patterned as shown in the figure! A group of protrusions (15) having a desired size, number and distribution are formed on the wafer (10). In this way, each protrusion (16) of protrusion # (15) on the wafer (10)
) (16)... is obtained as a sample wafer (17) corresponding to pseudo-attached dust.

皇皿勿班来 本発明方法によれば、マスクによるパターニングでウェ
ーハ上に形成した突起群の各突起の大きさ及び個数の制
御が容易に行え、且つ上記各突起の分布状態の設定が任
意に行えるので、所望の大きさ、個数及び均一な分布状
態の疑似的付着ゴミである突起群が得られ、また製造中
に異物が巻込まれることを可及的に抑制することができ
て9、サンプルウェーハとして要求される条件を簡便な
手段で容易に満たし得る。更に上記突起群の形成領域を
ウェーハ上でその全面或いは半面等と容易に設定するこ
とが可能で、サンプルウェーハの用途に応じて充分対応
し得る。このように本発明方法によるサンプルウェーハ
を使用すれば、適正なゴミ検査が実現される。
According to the method of the present invention, the size and number of each protrusion in a group of protrusions formed on a wafer by patterning using a mask can be easily controlled, and the distribution state of each of the protrusions can be arbitrarily set. As a result, it is possible to obtain protrusions of the desired size, number, and uniform distribution, which are pseudo-attached dust, and to suppress as much as possible the inclusion of foreign matter during manufacturing. The conditions required for wafers can be easily met by simple means. Furthermore, it is possible to easily set the formation region of the protrusion group on the entire surface or half of the wafer, which can be sufficiently adapted to the use of the sample wafer. As described above, by using the sample wafer according to the method of the present invention, proper dust inspection can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至築5図は本発明に係るサンプルウェーハの製
造方法の一実施例を説明するための各工程を示すウェー
ハ各断面図である。 第6図乃至第8図はサンプルウェーハの製造方法の従来
例を説明するための各工程を示すウェーハ各断面図であ
る。 (10)−・−ウェーハ、     (1)) −薄膜
、(12)・・・レジスト膜、    (15)・−・
突起群、(171−−サンプルウ一−ハ。 特 許 出 願 人  関西日本電気株式会社1′ 第1図 第2z 第3図 第4図
FIGS. 1 to 5 are cross-sectional views of each wafer showing each step for explaining an embodiment of the method for manufacturing a sample wafer according to the present invention. FIGS. 6 to 8 are wafer cross-sectional views showing each process for explaining a conventional method for manufacturing a sample wafer. (10)--Wafer, (1))-Thin film, (12)...Resist film, (15)--
Group of protrusions, (171--Sample wafer. Patent applicant: Kansai NEC Corporation 1' Figure 1, Figure 2z, Figure 3, Figure 4)

Claims (1)

【特許請求の範囲】[Claims] (1)ウェーハ上に疑似的付着ゴミ材質の薄膜及びレジ
スト膜を積層形成し、マスキングによりこのレジスト膜
をパターン化した後、上記薄膜をエッチングして所望の
大きさ、個数及び分布状態の突起群を形成することを特
徴とするサンプルウェーハの製造方法。
(1) After forming a thin film of pseudo-attached dust material and a resist film on a wafer, patterning this resist film by masking, etching the thin film to obtain a group of protrusions of desired size, number, and distribution state. A method for manufacturing a sample wafer, the method comprising: forming a sample wafer;
JP7528087A 1987-03-27 1987-03-27 Manufacture of sample wafer Pending JPS63240040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7528087A JPS63240040A (en) 1987-03-27 1987-03-27 Manufacture of sample wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7528087A JPS63240040A (en) 1987-03-27 1987-03-27 Manufacture of sample wafer

Publications (1)

Publication Number Publication Date
JPS63240040A true JPS63240040A (en) 1988-10-05

Family

ID=13571658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7528087A Pending JPS63240040A (en) 1987-03-27 1987-03-27 Manufacture of sample wafer

Country Status (1)

Country Link
JP (1) JPS63240040A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0727659A2 (en) * 1995-02-14 1996-08-21 Seiko Instruments Inc. Method and apparatus for analyzing minute foreign substances, and process for manufacturing semiconductor or LCD elements

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0727659A2 (en) * 1995-02-14 1996-08-21 Seiko Instruments Inc. Method and apparatus for analyzing minute foreign substances, and process for manufacturing semiconductor or LCD elements
EP0727659A3 (en) * 1995-02-14 1998-03-04 Seiko Instruments Inc. Method and apparatus for analyzing minute foreign substances, and process for manufacturing semiconductor or LCD elements
US6124142A (en) * 1995-02-14 2000-09-26 Seiko Instruments, Inc. Method for analyzing minute foreign substance elements
US6355495B1 (en) 1995-02-14 2002-03-12 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for analyzing minute foreign substance, and process for semiconductor elements or liquid crystal elements by use thereof

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