JPS58122726A - Manufacture of semiconductor element by close control of resist dimension - Google Patents
Manufacture of semiconductor element by close control of resist dimensionInfo
- Publication number
- JPS58122726A JPS58122726A JP57004035A JP403582A JPS58122726A JP S58122726 A JPS58122726 A JP S58122726A JP 57004035 A JP57004035 A JP 57004035A JP 403582 A JP403582 A JP 403582A JP S58122726 A JPS58122726 A JP S58122726A
- Authority
- JP
- Japan
- Prior art keywords
- exposure time
- center
- resist pattern
- width
- exposure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70058—Mask illumination systems
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
この発明は、IC−?LSI等の半導体素子の製造方法
に関し、さらに詳しくは微細加工を行うフォトリングラ
フィ(光蝕刻法)の工程に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention This invention relates to IC-? The present invention relates to a method for manufacturing semiconductor devices such as LSI, and more specifically to a photolithography process for performing microfabrication.
発明の技術的背景
最近のフォ) IJソグラフィは、素子の集積度向上の
ためにパターンの微細化が進み、解像度や寸法精度が重
要視されるか→につれて、使用されるフォトレジストは
ネガ型からポジ型に移行し、露光装置はコンタクト方式
やl:1グロジエクシ。Technical Background of the Invention Recently, in IJ lithography, patterns have become finer to improve the degree of integration of devices, and as resolution and dimensional accuracy become more important, the photoresists used have changed from negative to negative type. The shift was to positive type, and the exposure equipment used was contact type and l:1 grossiex.
ン方式に加えてステップアンドリピート方式が注目され
るようになった。In addition to the step-and-repeat method, the step-and-repeat method has started to attract attention.
また現偉装置は、ディ、プ方式とスプレ一方式に大別さ
れるが、ディップ方式はウェハ面内及びウェハ間の現偉
むらやレジスト残り等の不良が発生しやすく、また自動
化し難いという欠点があるので、スプレ一方式の自動化
装置が使用される場合が多いようである。In addition, coating equipment can be roughly divided into a dip method and a spray method, but the dip method is prone to defects such as uneven coating and resist residue within the wafer surface and between wafers, and is difficult to automate. Because of these drawbacks, automated spray-only equipment is often used.
背景技術の問題点
しかしながら、スプレ一方式の現儂の場合には、ウェハ
の中央部と周縁部とでレジストパターンの幅寸法が異な
るという問題がある。すなわち、ポジ型レジストの場合
周縁部に比べて中央部のレジストパターンの幅寸法は、
残しパターンの幅寸法が小さくなり、穴あけパターンの
幅寸法が大きくなる。Problems with the Background Art However, in the case of the current one-spray method, there is a problem in that the width dimension of the resist pattern is different between the center portion and the peripheral portion of the wafer. In other words, in the case of a positive resist, the width of the resist pattern at the center compared to the periphery is
The width dimension of the remaining pattern becomes smaller, and the width dimension of the punching pattern becomes larger.
この問題は次の(i) (ii)の現象と密接な関係が
あると考えられている。This problem is considered to be closely related to the following phenomena (i) and (ii).
(i)スプレ一方式では、一般にウエノ・を回転させな
から現像液を散布しているのでウェハ中央部が周縁部に
比べてより多くの現像液に当り、中央部の現像速度が速
くなること。(i) In the spray type, the developer is generally sprayed without rotating the wafer, so the center of the wafer is exposed to more developer than the periphery, and the development speed in the center is faster. .
(if)現像液温を一定に保つために室温より高くず・
ることか多いが、この場合周縁部では中央部に比べて温
度が下がり易く、周縁部の現像速度が遅くなること。(if) In order to keep the developer temperature constant, it should not be higher than room temperature.
In this case, the temperature at the periphery tends to drop more easily than at the center, and the developing speed at the periphery becomes slower.
このように現像速度が異なって幅寸法がばらつくという
ことは、特に微細なパターンの場合、素子の歩留り低下
の大きな原因となる。なかんづく、ポジ型レジストはネ
ガ型レジストより現像速度が現像条件によって影響を受
けやすいので、ポジ型レジストを使用した場合特に大き
な問題となっている。This variation in width due to different development speeds is a major cause of a decrease in device yield, especially in the case of fine patterns. In particular, since the development speed of positive resists is more susceptible to development conditions than that of negative resists, this poses a particularly serious problem when positive resists are used.
第1図は従来の製造方法(すなわちポジ型レジスト塗布
後、ウニ・・全面を同一露光時間で露光したものを、ス
プレ一方式で現像する方法)によりす図である。同図に
おいて横軸はウェハ中心からの距離d(m)i、縦軸は
レジストパターンの幅寸法t(μmyt表わす。この図
から、従来の製造方法によると、中央部は相対的に現像
速度が速く、一方周縁部は相対的に現像速度が遅く、レ
ジストパターンの幅寸法がばらつくことがわかる。FIG. 1 is a diagram showing a conventional manufacturing method (that is, after applying a positive resist, the entire surface of the sea urchin is exposed for the same exposure time, and then developed using a spray method). In the figure, the horizontal axis represents the distance d(m)i from the center of the wafer, and the vertical axis represents the width dimension t (μmyt) of the resist pattern. From this figure, it can be seen that according to the conventional manufacturing method, the development speed is relatively low in the central part. On the other hand, the developing speed at the peripheral edge portion is relatively slow, and it can be seen that the width dimension of the resist pattern varies.
発明の目的
この発明の目的は、スプレ一方式(シャワ一方式を含む
)の現像において形成されるレジストパターンの幅寸法
のばらつきを解消する新規な半導体素子の製造方法を提
供することにある〇発明の概要
この発明の半導体素子の製造方法は、レジストパターン
の幅寸法が露光時間増減によって変化することに着目し
てなされたものである。即ちレジスト塗布工程において
被塗布面にほぼ均一に塗布されたフォトレジスト膜がス
プレー又はシャワ一方式の現像工程によってレジストパ
ターンに形成されるが、そのレジストパターンの幅寸法
のばらつきを、霧光工程において被塗布面の周縁部から
中央部に向かって徐々に露光時間を変えたステップアン
ドリピート露光を行うことにより補償して、そのばらつ
きを解消しようとするものである。Purpose of the Invention An object of the present invention is to provide a novel semiconductor device manufacturing method that eliminates variations in the width dimension of resist patterns formed in one-way spray development (including one-way shower development). Summary of the Invention The method for manufacturing a semiconductor device of the present invention was developed by focusing on the fact that the width of a resist pattern changes depending on an increase or decrease in exposure time. In other words, in the resist coating process, a photoresist film that is almost uniformly applied to the surface to be coated is formed into a resist pattern by a spray or shower development process, but variations in the width of the resist pattern are removed in the fog light process. This is an attempt to compensate and eliminate the variation by performing step-and-repeat exposure in which the exposure time is gradually changed from the periphery to the center of the surface to be coated.
レジストパターンの幅寸法と露光時間との関係はレジス
トの種類材質によって異なる。例えばポジ型レジストの
場合、第2図のグラフ〔横軸は露光時間T(see)
、縦軸はレジストパターンの幅寸法t(μm)を表わす
〕K示、すように、露光時間が長くなるにつれてレジス
トパターンの幅寸法は減少するので、この事実を利用し
て現像によってレジストパターンの幅寸法が小となるウ
ェハ中央部については露光時間を少なりシ、レジストパ
ターンの幅寸法が大となるウェハ周縁部については露光
時間を多くするようにすれば、ウェハ全面にわたってレ
ジストパターンの幅寸法を一定にすることができる。ネ
ガ型レジストの場合にはこの逆にすればよい。The relationship between the width dimension of the resist pattern and the exposure time differs depending on the type and material of the resist. For example, in the case of a positive resist, the graph in Figure 2 [the horizontal axis is the exposure time T (see)]
, the vertical axis represents the width t (μm) of the resist pattern] As shown in K, the width of the resist pattern decreases as the exposure time increases, and this fact can be utilized to increase the width of the resist pattern by development. By reducing the exposure time for the center of the wafer, where the width is small, and increasing the exposure time for the periphery of the wafer, where the width of the resist pattern is large, the width of the resist pattern can be reduced over the entire wafer. can be kept constant. In the case of a negative resist, this process may be reversed.
ところで、ステップアンドリピート方式の露光は、被露
光面を、縮少投影された露光面積で分割し、繰返し露光
の機構を持たせたものであるが、従来社解像力を高め、
欠陥数を減少させ、位置合せや焦点補正をして精度を向
上させるように使われていただけであって、この発明の
ようにステップ毎に露光時間を変えてレジストパターン
の幅寸法のばらつきをなくすように使用されたことはな
かった。By the way, in the step-and-repeat method of exposure, the exposed surface is divided into reduced projected exposure areas and a mechanism for repeated exposure is provided.
It was only used to reduce the number of defects and improve accuracy by correcting alignment and focus, and as in this invention, the exposure time is changed for each step to eliminate variations in the width dimension of the resist pattern. It had never been used like that.
この発明においては、フォトレジストを被塗布面にほぼ
均一に塗布する。塗布膜厚の変動によりレジストパター
ンの幅寸法の変動が招来される力;、この原因によるレ
ジスしくターンの幅寸法のばらつきも通常ウエノ・管回
転させて塗布するのでウェハ周縁部から中央部に向かっ
て徐々に発生しているから、この発明によって補償され
る。In this invention, the photoresist is applied almost uniformly to the surface to be coated. The force that causes variations in the width dimension of the resist pattern due to variations in the coating film thickness; the variation in the width dimension of the resist pattern due to this cause is usually applied by rotating the wafer/tube, so the resist pattern width varies from the periphery to the center of the wafer. Since this phenomenon occurs gradually, it can be compensated for by this invention.
この発明における現像工程は、スプレー又はシャワ一方
式による。これら方式の特徴は被現像体が回転すること
におる。通常スプレ一方式とは、N2ガスなどによって
現像液が霧吹かれ、またシャワ一方式はN2ガスなどで
加圧されることによって現像液がノズルから噴出し、被
現像体に吹き付けられる。The developing step in this invention is carried out by spraying or showering. A feature of these methods is that the object to be developed rotates. Normally, in the spray type, the developer is sprayed with N2 gas or the like, and in the shower type, the developer is pressurized with N2 gas or the like, so that the developer is spouted from a nozzle and sprayed onto the object to be developed.
また、半導体素子製造におけるフォトリングラフィとは
、光蝕刻法が適用される工程を意味し、半導体ウェハ上
に適用される場合以外にも、マスクブランク上に適用さ
れる場合などを含むものと解されなければならない。In addition, photolithography in semiconductor device manufacturing refers to a process in which photolithography is applied, and can be understood to include cases in which it is applied not only to semiconductor wafers but also to mask blanks. It must be.
次にこの発明の一実施例とその具体的な効果について説
明する′。Next, one embodiment of the present invention and its specific effects will be explained.
発明の実施例
厚さ4000Xの酸化膜を有する直径100ffのシリ
コンウェハに1.5声の厚さでポジ型フォトレジストヲ
塗布したのち、90℃・1o分間のプリベーキングを行
った。次に露光工程では10M×101nIのステップ
ピッチで′ウェハ中心部のチップに対しては0.2秒の
露光時間で、またウェハ周縁部のチップに対しては0,
4秒の露光時間となるようにウェハ周縁部からウェハ中
央部に向かうにつれて徐々に露光時間を減少させつつ縮
少投影型露光装置でステップアンドリピート式に露光を
行った。そして露光後のウェハをスプレ一方式により現
像をした後、該レジストパターンの幅寸法の分布を測定
したところ、ウェハ中心部と周縁部の幅寸法の差はわず
か0.06μm以下であった。また、同一のテストを統
計的に信頼性のある大きさの母集団につき行った幅寸法
測定値を、従来方法(すなわち全面同一露光時間のステ
ップアンドリピート方式)による幅寸法測定値と比較し
たところ、標準偏差が従来法の場合0.10/IWiで
あるのに対して、この発明の方発明の効果
以上のように、この発明によれば、ウエノ・全面にわた
って均一なパターン寸法が得られ、その結果チップ歩留
りを改善することができる新規な半導体素子の製造方法
が提供される。またこの発明によれば、現像装置やレジ
スト塗布装置などの根本的改良を必要としないうえ、現
に使用されている縮少型投影露光装置を使用できるので
、改善効果の大きな割りには改善投資額が不要であり、
従って大きな費用対比効果が得られる。EXAMPLE OF THE INVENTION A silicon wafer having a diameter of 100 ff and having an oxide film having a thickness of 4000× was coated with a positive photoresist to a thickness of 1.5 tones, and then prebaked at 90° C. for 10 minutes. Next, in the exposure process, with a step pitch of 10M x 101nI, the exposure time was 0.2 seconds for the chips at the center of the wafer, and 0.2 seconds for the chips at the periphery of the wafer.
Exposure was carried out in a step-and-repeat manner using a reduced projection type exposure apparatus while gradually decreasing the exposure time from the wafer periphery toward the wafer center so that the exposure time was 4 seconds. After the exposed wafer was developed using a spray method, the width distribution of the resist pattern was measured, and it was found that the difference in width between the center and peripheral portion of the wafer was only 0.06 μm or less. In addition, the width measurement values obtained by performing the same test on a population of statistically reliable size were compared with the width measurement values obtained using the conventional method (i.e., step-and-repeat method with the same exposure time on the entire surface). , the standard deviation is 0.10/IWi in the conventional method, whereas the present invention has a uniform pattern size over the entire surface of the wafer, as described above. As a result, a novel semiconductor device manufacturing method is provided that can improve chip yield. Furthermore, according to this invention, it is not necessary to fundamentally improve the developing device or the resist coating device, etc., and the currently used reduced-size projection exposure device can be used. is not necessary,
Therefore, a large cost-effectiveness can be obtained.
第1図は従来の製造方法によって得られるウェハ上のレ
ジストパターン幅寸法の分布を示す図、第2図はこの発
明の基礎となる事実を示した図であるO
特許出願人 東京芝浦電気株式会社Fig. 1 is a diagram showing the distribution of resist pattern width dimensions on a wafer obtained by a conventional manufacturing method, and Fig. 2 is a diagram showing the facts that form the basis of this invention.Patent applicant: Tokyo Shibaura Electric Co., Ltd.
Claims (1)
り、レジスト電布工程においてはフォトレジストを被塗
布面に塗布し、露光工程においては被塗布面の周縁部か
ら中央部に向かって徐々に露光時間を変えてステップア
ンドリピート露光現俸を行うことを特徴とする半導体素
子の製造方法。1 In photolithography in semiconductor device manufacturing, photoresist is applied to the surface to be coated in the resist coating process, and in the exposure process, the exposure time is gradually changed from the periphery to the center of the surface to be coated. A method for manufacturing a semiconductor device, characterized by performing and-repeat exposure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57004035A JPS58122726A (en) | 1982-01-16 | 1982-01-16 | Manufacture of semiconductor element by close control of resist dimension |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57004035A JPS58122726A (en) | 1982-01-16 | 1982-01-16 | Manufacture of semiconductor element by close control of resist dimension |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58122726A true JPS58122726A (en) | 1983-07-21 |
JPS6219049B2 JPS6219049B2 (en) | 1987-04-25 |
Family
ID=11573701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57004035A Granted JPS58122726A (en) | 1982-01-16 | 1982-01-16 | Manufacture of semiconductor element by close control of resist dimension |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58122726A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5943550A (en) * | 1996-03-29 | 1999-08-24 | Advanced Micro Devices, Inc. | Method of processing a semiconductor wafer for controlling drive current |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01159559U (en) * | 1988-04-23 | 1989-11-06 |
-
1982
- 1982-01-16 JP JP57004035A patent/JPS58122726A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5943550A (en) * | 1996-03-29 | 1999-08-24 | Advanced Micro Devices, Inc. | Method of processing a semiconductor wafer for controlling drive current |
Also Published As
Publication number | Publication date |
---|---|
JPS6219049B2 (en) | 1987-04-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH0669114A (en) | Formation method of photoresist film on semiconductor substrate, photoresist solution used for it and surface antireflection film | |
US7824846B2 (en) | Tapered edge bead removal process for immersion lithography | |
TWI391779B (en) | Mask blanks and a transfer mask | |
US6610616B2 (en) | Method for forming micro-pattern of semiconductor device | |
US4738910A (en) | Method of applying a resist | |
US20060134559A1 (en) | Method for forming patterns on a semiconductor device | |
US5902716A (en) | Exposure method and apparatus | |
JPH09106081A (en) | Resist pattern forming method | |
JPS58122726A (en) | Manufacture of semiconductor element by close control of resist dimension | |
JPH01142721A (en) | Positive type photosensitive pattern forming material and pattern forming method | |
JP2000277423A (en) | Manufacture of semiconductor device | |
JPS61102738A (en) | Method of forming pattern for resist film | |
US5891749A (en) | Process for forming photoresist pattern in semiconductor device | |
CN116430690A (en) | Photoetching developing method and semiconductor structure | |
JPH06140297A (en) | Resist applying method | |
JPH0425114A (en) | Resist pattern forming method | |
JPS60106132A (en) | Formation of pattern | |
KR20040061442A (en) | Method and apparatus of removing edge bead for a substrate | |
JPH03149808A (en) | Method of forming resist pattern | |
JPH0419697B2 (en) | ||
JPS61112321A (en) | Flattening method of surface | |
Leonard et al. | New Positive Resist Designed For Use In The Mid Ultraviolet | |
JPH0745498A (en) | Formation of antireflection and antiinterference resin film | |
JPS5852639A (en) | Formation of resist pattern | |
JPH03231419A (en) | Exposure of resist pattern |