JPS63239938A - Manufacturing apparatus for semiconductor device - Google Patents

Manufacturing apparatus for semiconductor device

Info

Publication number
JPS63239938A
JPS63239938A JP7346887A JP7346887A JPS63239938A JP S63239938 A JPS63239938 A JP S63239938A JP 7346887 A JP7346887 A JP 7346887A JP 7346887 A JP7346887 A JP 7346887A JP S63239938 A JPS63239938 A JP S63239938A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor substrate
port
reactor
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7346887A
Other languages
Japanese (ja)
Inventor
Toshio Shoji
東海林 利夫
Akemichi Yonekura
米倉 明道
Tsunehisa Ueno
上野 恒久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7346887A priority Critical patent/JPS63239938A/en
Publication of JPS63239938A publication Critical patent/JPS63239938A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To block the intrusion of outer air into a reaction furnace sufficiently when semiconductor substrates are carried into and out of the reaction furnace without a large amount of inactive gas, by specifying the gas jetting direction of each gas jetting port, which jets the inactive gas toward the semiconductor substrates that are carried into and out of a semiconductor substrate inputting port. CONSTITUTION:A reaction furnace 21, which heats semiconductor substrates 24, is provided in a semiconductor-device manufacturing apparatus. Jetting ports 31A, which jet inactive gas toward the semiconductor substrates 24 that are carried into and out of a semiconductor- substrate inputting port 23, are provided in the vicinity of the outer parts of the semiconductor- substrate inputting port 23 of the reaction furnace 21. The gas jetting direction of each gas jetting port 31A is set at an angle in the range of about 5-about 80 degrees toward the outside of the semiconductor-substrate inputting port 23, with the opening plane of the semiconductor-substrate inputting port 23 as a reference. For example, two or more shower nozzles 31 are attached to the outside of the semiconductor-substrate inputting port 23 of a vertical type pressure reduced CVD apparatus. The inactive gas is jetted to the semiconductor substrates 24, which are carried into and out of the reaction furnace 21 accompanied by the up and down movement of an elevator 28, through the above described gas jetting ports 31A.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は拡散装置、CVD装置等のような半導体基板が
加熱状態に置かれる反応炉を備えた半導体装置の製造装
置に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device manufacturing apparatus equipped with a reaction furnace in which a semiconductor substrate is heated, such as a diffusion device or a CVD device. .

(従来の技術) 拡散装置、CVD装置等のような半導体基板が加熱状態
に置かれる反応炉を備えた半導体装置の製造装置では、
半導体基板を反応炉内に搬出入する際に半導体基板搬入
口から外気が反応炉内に混入し易く、半導体基板に自然
酸化膜を生じさせていた。
(Prior Art) In a semiconductor device manufacturing apparatus equipped with a reaction furnace in which a semiconductor substrate is heated, such as a diffusion device or a CVD device,
When carrying semiconductor substrates into and out of the reactor, outside air tends to enter the reactor through the semiconductor substrate loading port, causing a natural oxide film to form on the semiconductor substrates.

例えば、選択酸化を用いた素子間分離工程では、第5図
(A)に示されるように、ポリシリコン層3上に酸化マ
スクとして窒化シリコン層4を形成する。その際、ポリ
シリコン層3上に、自然酸化膜5が形成される。
For example, in an element isolation process using selective oxidation, a silicon nitride layer 4 is formed as an oxidation mask on a polysilicon layer 3, as shown in FIG. 5(A). At this time, a natural oxide film 5 is formed on the polysilicon layer 3.

次にフォトリングラフイーとドライエツチングにより、
窒化シリコン層4をパターニングし、Fjcld酸化の
前処理を行なうが、この時ポリンリコン層3上の自然酸
化膜5が窒化ンリコン層4のドまでエツチングされ、第
5図(B)のようになる。このような状態で、フィール
ド酸化を行なうと、窒化シリコン層4のマスクとしての
実効幅が小さくなり、第5図(C)に示されるように、
フィールド酸化膜6と窒化シリコン層4とのパターン変
換差ΔWが異常に大きくなってしまう。これは高密度回
路を形成する]二で不都合なことである。
Next, by photophosphorography and dry etching,
The silicon nitride layer 4 is patterned and pre-processed for Fjcld oxidation, but at this time the native oxide film 5 on the polygon silicon layer 3 is etched down to the depths of the silicon nitride layer 4, as shown in FIG. 5(B). If field oxidation is performed in such a state, the effective width of the silicon nitride layer 4 as a mask becomes smaller, as shown in FIG. 5(C).
The pattern conversion difference ΔW between the field oxide film 6 and the silicon nitride layer 4 becomes abnormally large. This creates a high density circuit, which is disadvantageous.

第6図には、自然酸化膜5の厚さとパターン変換差ΔW
との関係が示されているが、この図からも自然酸化膜5
の厚さを減らせばパターン変換差ΔWも減ることが分か
る。
FIG. 6 shows the thickness of the natural oxide film 5 and the pattern conversion difference ΔW.
This figure also shows that the natural oxide film 5
It can be seen that if the thickness is reduced, the pattern conversion difference ΔW is also reduced.

また、自然酸化膜5は拡散工程では拡散不純物のバリア
として作用するので、拡散不純物量の制御を困難にさせ
ることになる。
Furthermore, since the natural oxide film 5 acts as a barrier to diffused impurities during the diffusion process, it becomes difficult to control the amount of diffused impurities.

そこで、このような自然酸化膜の発生の原因となる外気
の反応炉内への混入を減らすために、反応炉の半導体基
板搬入口の近傍に前記半導体基板微人口より搬出入され
る半導体基板に向かって不活性気体を噴射する気体噴射
口が設けられ、この気体噴射口からの気体噴出により外
蓋の侵入をυF除しようとする装置が既に知られている
Therefore, in order to reduce the intrusion of outside air into the reactor, which causes the formation of such a natural oxide film, the semiconductor substrates being carried in and out of the semiconductor substrate micro-port are placed near the semiconductor substrate loading entrance of the reactor. There is already known a device that is provided with a gas injection port that injects an inert gas toward the container, and attempts to prevent the intrusion of the outer lid by υF by ejecting gas from the gas injection port.

第7図にはこのような従来装置が示されている。FIG. 7 shows such a conventional device.

図中、ヒータ7に囲まれた反応炉8の平導体J!仮搬入
口9の周囲近傍にはシャワーノズル10が設けられ、反
応炉8内に搬入される半導体基板12に向かって気体噴
射口10Aから不活性気体が噴射される。
In the figure, a flat conductor J! of a reactor 8 surrounded by a heater 7! A shower nozzle 10 is provided near the periphery of the temporary loading port 9, and inert gas is injected from the gas injection port 10A toward the semiconductor substrate 12 being loaded into the reactor 8.

(発明か解決しようとする問題点) ところが、このような従来装置における半導体基板12
の搬入時に混入される外気(酸素)のl農度と気体噴射
口10Aから噴射する不活性気体(窒素)の濃度との関
係を調べたところ、第8図に示されるように、酸素濃度
を減らすためには窒素の噴出量を多量なものとしなけれ
ばならないことが分かった。
(Problem to be solved by the invention) However, in such a conventional device, the semiconductor substrate 12
When we investigated the relationship between the concentration of the inert gas (nitrogen) injected from the gas injection port 10A and the concentration of the outside air (oxygen) mixed in when the gas was brought in, we found that the oxygen concentration was It was found that in order to reduce this, it was necessary to increase the amount of nitrogen emitted.

上記事情に鑑み、本発明は、多瓜の不活性気体を要する
ことなく、半導体基板の反応炉内への搬出入時における
外気の反応炉内への混入を十分に阻11.することので
きる半導体装置の製造装置を提1共することを目的とす
る。
In view of the above circumstances, the present invention sufficiently prevents outside air from entering the reactor when semiconductor substrates are carried into and out of the reactor, without requiring a polygonal inert gas.11. The purpose of the present invention is to provide a semiconductor device manufacturing apparatus that can perform the following steps.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) 上記目的を達成するため、本発明による半導体装置の製
造装置は、反応炉の半導体基板搬入口の周囲近傍に、′
+−導体基板搬入口より搬出入される半導体基板に向か
って不活性気体を噴射する気体噴射口を設けられ、この
気体噴射口の気体噴出方向が゛(6導体基板搬入ロ而を
基準にして半導体基板搬入口の外方側に向かって約5度
から約80度の範囲内の角度に向けたことを特徴とする
(Means for Solving the Problems) In order to achieve the above object, the semiconductor device manufacturing apparatus according to the present invention has a
+ - A gas injection port is provided that injects inert gas toward semiconductor substrates being carried in and out from the conductor substrate loading port, and the gas injection direction of this gas injection port is It is characterized in that it is oriented at an angle within a range of about 5 degrees to about 80 degrees toward the outside of the semiconductor substrate loading port.

(作 用) 気体噴射口の気体噴出方向を1−記の範囲内の角度に設
定することにより、多皿の不活性気体を噴出させなくと
も外気の反応炉内への混入を十分にIIH市することが
できる。
(Function) By setting the gas jetting direction of the gas jetting port to an angle within the range described in 1-1, it is possible to sufficiently prevent outside air from entering the reactor without jetting out multiple plates of inert gas. can do.

(実施例) 本発明の一実施例による縦型減圧CVD装置を第1図に
示す。
(Embodiment) FIG. 1 shows a vertical reduced pressure CVD apparatus according to an embodiment of the present invention.

反応炉21は縦向きに配置された石英チューブより構成
され、その底部にはフランジ部22が配置され、このフ
ランジ部22の底部に半導体基板搬入口23が設けられ
ている。半導体基板搬入口23から反応炉21内に搬入
・排出される半導体1λ仮24は、一枚一枚が水平方向
に向けられ且つ互いの間に所定の間隔を置いた状態で、
縦h゛向に曵数枚積層されて石英ボート25に着脱可能
に保持されている。この石英ボート25は石英ボート支
持台26に支持され、この石英ボート支持台26にはフ
ランジ部27か取付けられている。また、石英ボート支
持台はエレベータ28に取り付けられ、エレベータ28
はエレベータ支柱29に沿って縦方向に移動出来るよう
になっている。
The reactor 21 is composed of a vertically arranged quartz tube, and a flange portion 22 is disposed at the bottom of the reactor 21, and a semiconductor substrate loading port 23 is provided at the bottom of the flange portion 22. The semiconductor 1λ temporary 24 carried into and discharged from the semiconductor substrate loading port 23 into the reactor 21 is oriented horizontally one by one and with a predetermined interval between them.
Several sheets are stacked vertically and held in a quartz boat 25 in a removable manner. The quartz boat 25 is supported by a quartz boat support 26, and a flange portion 27 is attached to the quartz boat support 26. Additionally, the quartz boat support is attached to the elevator 28, and the quartz boat support is attached to the elevator 28.
can move vertically along the elevator support column 29.

半導体基板搬入口23の周囲には少なくとも2つのシャ
ワーノズル31か取り付けられており、これらシャワー
ノズル31の気体噴射口31Aからは、エレベータ28
の上下動に伴って半導体基板搬入口23から反応炉21
に搬出入する半導体基板24に向かって不活性気体が噴
射されるようになっている。気体噴射口31Aの気体噴
出方向は、半導体基板搬入口23の開口面を基準にして
半導体基板搬入口の外方側(即ち、鉛直下側)に向かっ
て約5度から約80度の範囲内の角度に向けれている。
At least two shower nozzles 31 are installed around the semiconductor substrate loading port 23, and from the gas injection port 31A of these shower nozzles 31, the elevator 28
Due to the vertical movement of the reactor 21 from the semiconductor substrate loading port 23,
Inert gas is injected toward the semiconductor substrate 24 being carried in and out. The gas injection direction of the gas injection port 31A is within a range of about 5 degrees to about 80 degrees toward the outside of the semiconductor substrate loading port (i.e., vertically downward) based on the opening surface of the semiconductor substrate loading port 23. It is oriented at an angle of .

また、反応炉21の周囲にはヒータ32が設けられてお
り、反応炉21内の半導体基板24が加熱されるように
なっている。
Further, a heater 32 is provided around the reactor 21 so that the semiconductor substrate 24 inside the reactor 21 is heated.

次に、本実施例の作用につき説明する。Next, the operation of this embodiment will be explained.

半導体基板24をセットした石英ボート25をエレベー
タ28によりに昇させて反応炉21内に搬入するとき、
半導体基板搬入口23を通過する半導体基板24にシャ
ワーノズル31から不活性気体を前述の方向に吹き付け
る。これにより、石英ボート25にセットされた1夏数
の半導体基板24相互間の隙間に残存していた外気がパ
ージされる。また、シャワーノズル31からの不活性気
体がガスカーテンをつくり、石英ボート25と半導体基
板搬入口23との隙間からの外気の巻き込みによる反応
炉21内への混入を阻止する。また、反応炉21の周囲
にはヒータ32が設けられている。
When the quartz boat 25 in which the semiconductor substrate 24 is set is raised by the elevator 28 and carried into the reactor 21,
Inert gas is blown in the aforementioned direction from the shower nozzle 31 onto the semiconductor substrate 24 passing through the semiconductor substrate loading port 23 . As a result, the outside air remaining in the gaps between the semiconductor substrates 24 set in the quartz boat 25 is purged. Further, the inert gas from the shower nozzle 31 forms a gas curtain to prevent outside air from entering the reactor 21 due to entrainment from the gap between the quartz boat 25 and the semiconductor substrate loading port 23. Furthermore, a heater 32 is provided around the reactor 21 .

第2図には、気体噴射口31Aの気体噴出方向θと反応
炉21内の酸素7a度との関係が示されている。この図
から、気体噴射口31Aの気体噴出方向が約5度から約
80度の範囲内の角度に向けられているときには反応炉
21内の酸素濃度が低く、なかでも約30度から約60
度の範囲内の角度であるときに酸素濃度の低下が著しい
ことが分かる。
FIG. 2 shows the relationship between the gas jetting direction θ of the gas jetting port 31A and the oxygen 7a degrees inside the reactor 21. From this figure, when the gas injection direction of the gas injection port 31A is oriented at an angle within the range of about 5 degrees to about 80 degrees, the oxygen concentration in the reactor 21 is low, and especially at an angle of about 30 degrees to about 60 degrees.
It can be seen that the oxygen concentration decreases markedly when the angle is within the range of 100°.

このように本実施例によれば、多量の不活性気体を噴射
させなくとも、半導体基板24の反応炉21内への搬入
時における外気の反応炉内への混入を十分に阻11−す
ることができる。
According to this embodiment, it is possible to sufficiently prevent outside air from entering the reactor 21 when the semiconductor substrate 24 is carried into the reactor 21 without injecting a large amount of inert gas. Can be done.

また、半導体基板24を半導体基板搬入口23から反応
炉21外へと搬出するときにも前述の角度で気体噴射口
31Aから不活性気体を噴出させることにより、反応炉
21内で高温に加熱された半導体基板24を炉外への搬
出後直ちに外気に接触させることのないように不活性気
体で一定の時間だけ覆うことができる。その結果、炉外
での自然酸化膜の形成が抑えられ、史には、半導体基板
24に対する冷却効果により酸化速度を低下させること
もできるので、この点からも炉外での自然酸化膜の形成
を抑えることができる。
Furthermore, when the semiconductor substrate 24 is carried out of the reactor 21 from the semiconductor substrate loading port 23, inert gas is ejected from the gas injection port 31A at the above-mentioned angle, so that the semiconductor substrate 24 is heated to a high temperature inside the reactor 21. After the semiconductor substrate 24 is taken out of the furnace, it can be covered with an inert gas for a certain period of time so that it does not come into contact with the outside air immediately. As a result, the formation of a natural oxide film outside the furnace is suppressed, and the cooling effect on the semiconductor substrate 24 can also reduce the oxidation rate. can be suppressed.

また、半導体基板24を冷却することができるので次に
続く製造工程に早く移ることができ、生産性も向上する
Further, since the semiconductor substrate 24 can be cooled, the next manufacturing process can be started quickly, and productivity is also improved.

次に本発明の他の実施例による横型炉を第3図、第4図
に示す。
Next, a horizontal furnace according to another embodiment of the present invention is shown in FIGS. 3 and 4.

反応炉41は横向きに配置された石英チューブより構成
され、その水平方向の一端側にはフランジ部42が配置
され、このフランジ部42に半導体基板搬入口43が設
けられている。半導体基板24は、一枚一枚が鉛直方向
に向けられ且つ互いの間に所定の間隔を置いた状態で、
横方向に複数枚並べられて石英ボート45に着脱可能に
保持されている。この石英ボート45はポート出し入れ
用石英フォーク461−に着脱自在に保持されている。
The reactor 41 is composed of a quartz tube arranged horizontally, and a flange portion 42 is arranged at one end in the horizontal direction, and a semiconductor substrate loading port 43 is provided in the flange portion 42 . The semiconductor substrates 24 are each oriented vertically and are spaced apart from each other by a predetermined distance.
A plurality of sheets are arranged in a horizontal direction and are detachably held in a quartz boat 45. This quartz boat 45 is detachably held by a quartz fork 461- for taking in and out of the port.

フランジ部42にはフランジ扉47が開閉可能に取り付
けられているとともに半導体基板搬入口43の周囲には
少なくとも2つのンヤワーノズル48が取り付けられて
おり、これらシャワーノズル48の気体噴射口48Aか
らは、ボート出し入れ用石英フォーク46に乗せられて
半導体基板搬入口43から反応炉41に搬出入する半導
体基板24に向かって不活性気体が噴射されるようにな
っている。気体噴射口48Aの気体噴出方向は、半導体
基板搬入口43の開口面を基準にして半導体基板搬入口
43の外方側(即ち、図中水平方向左側)に向かって約
5度から約80度の範囲内の角度に向けられている。
A flange door 47 is attached to the flange portion 42 so as to be openable and closable, and at least two shower nozzles 48 are attached around the semiconductor substrate loading port 43. An inert gas is injected toward the semiconductor substrate 24 that is carried in and out of the reactor 41 from the semiconductor substrate loading port 43 on a quartz fork 46 for loading and unloading. The gas injection direction of the gas injection port 48A is approximately 5 degrees to approximately 80 degrees toward the outside of the semiconductor substrate loading port 43 (i.e., to the left side in the horizontal direction in the figure) with respect to the opening surface of the semiconductor substrate loading port 43. oriented at an angle within the range of

このような横型炉の場合にも前記縦型炉の場合と同様の
効果がある。
Even in the case of such a horizontal furnace, the same effects as in the case of the vertical furnace can be obtained.

また、本発明が適用されるのはCVD装置に限らず、拡
散炉等の加熱処理を含む他の半導体装置の製造装置であ
ってもよい。
Furthermore, the present invention is applicable not only to CVD apparatuses but also to other semiconductor device manufacturing apparatuses that include heat treatment such as a diffusion furnace.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明によれば、多量の不活性気体を要
することなく、半導体基板の反応炉内への搬入時におけ
る外気の反応炉内への混入を十分に阻止することができ
る。
As described above, according to the present invention, it is possible to sufficiently prevent outside air from entering the reactor when carrying the semiconductor substrate into the reactor, without requiring a large amount of inert gas.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による縦型減圧CVD装置を
示す断面図、第2図は同縦型減圧CVD装置における気
体噴射口の角度と反応炉内の酸素の濃度との関係を示す
グラフ、第3図及び第4図は本発明の他の実施例による
横型炉を示す断面図、第5図は反応炉内に混入した外気
により形成された自然酸化膜がフィールド酸化膜の形成
工程において及ぼす影響を示す断面図、第6図は自然酸
化膜の厚さとパターン変換差ΔWとの関係を示すグラフ
、第7図は従来の半導体装置の製造装置を示す断面図、
第8図は従来の装置における反応炉内の酸素濃度とシャ
ワーノズルからの窒素の噴射量との関係を示すグラフで
ある。 21.41・・・反応炉、22.42・・・フランジ部
、23.43・・・半導体基板搬入口、24・・・半導
体基板、25.45・・・石英ボート、27.47・・
・フランジ部、31.48・・・シャワーノズル、31
A。 48A・・・気体噴射口、32.33・・・ヒータ。 出願人代理人  佐  藤  −雄 65 図 bμ」演4tqlrr;!Iン(ム) 匹6 区 乳7 図 X ’!A ”* t−f (j/m1n)昆8 図
Fig. 1 is a sectional view showing a vertical reduced pressure CVD apparatus according to an embodiment of the present invention, and Fig. 2 shows the relationship between the angle of the gas injection port and the concentration of oxygen in the reactor in the same vertical reduced pressure CVD apparatus. Graphs, FIGS. 3 and 4 are cross-sectional views showing horizontal reactors according to other embodiments of the present invention, and FIG. 5 shows a process in which a natural oxide film formed by outside air mixed into the reactor becomes a field oxide film. 6 is a graph showing the relationship between the thickness of the native oxide film and the pattern conversion difference ΔW. FIG. 7 is a sectional view showing the conventional semiconductor device manufacturing apparatus.
FIG. 8 is a graph showing the relationship between the oxygen concentration in the reactor and the amount of nitrogen injected from the shower nozzle in a conventional apparatus. 21.41... Reactor, 22.42... Flange portion, 23.43... Semiconductor substrate loading port, 24... Semiconductor substrate, 25.45... Quartz boat, 27.47...
・Flange part, 31.48...Shower nozzle, 31
A. 48A...Gas injection port, 32.33...Heater. Applicant's agent Mr. Sato 65 Figure bμ'' Performance 4tqlrr;! Iin (mu) 6 wards milk 7 Figure X'! A ”* t-f (j/m1n)Kon8 Figure

Claims (1)

【特許請求の範囲】 1、半導体基板を加熱する反応炉を備えた半導体装置の
製造装置において、前記反応炉の半導体基板搬入口の周
囲近傍に、前記半導体基板搬入口より搬出入される半導
体基板に向かって不活性気体を噴射する気体噴射口が設
けられ、この気体噴射口の気体噴出方向が、前記半導体
基板搬入口の開口面を基準にして前記半導体基板搬入口
の外方側に向かって約5度から約80度の範囲内の角度
に向けられていることを特徴とする半導体装置の製造装
置。 2、特許請求の範囲第1項記載の半導体装置の製造装置
において、前記反応炉は半導体基板搬入口が底部に設け
られた縦型反応炉であることを特徴とする半導体装置の
製造装置。
[Scope of Claims] 1. In a semiconductor device manufacturing apparatus equipped with a reaction furnace for heating semiconductor substrates, a semiconductor substrate that is carried in and out from the semiconductor substrate loading port is placed near the semiconductor substrate loading port of the reactor. A gas injection port is provided for injecting an inert gas toward the semiconductor substrate, and the gas injection direction of the gas injection port is directed toward the outside of the semiconductor substrate loading port with reference to the opening surface of the semiconductor substrate loading port. A semiconductor device manufacturing apparatus characterized in that the apparatus is oriented at an angle within a range of about 5 degrees to about 80 degrees. 2. The semiconductor device manufacturing apparatus according to claim 1, wherein the reactor is a vertical reactor having a semiconductor substrate loading port provided at the bottom.
JP7346887A 1987-03-27 1987-03-27 Manufacturing apparatus for semiconductor device Pending JPS63239938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7346887A JPS63239938A (en) 1987-03-27 1987-03-27 Manufacturing apparatus for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7346887A JPS63239938A (en) 1987-03-27 1987-03-27 Manufacturing apparatus for semiconductor device

Publications (1)

Publication Number Publication Date
JPS63239938A true JPS63239938A (en) 1988-10-05

Family

ID=13519134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7346887A Pending JPS63239938A (en) 1987-03-27 1987-03-27 Manufacturing apparatus for semiconductor device

Country Status (1)

Country Link
JP (1) JPS63239938A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4962726A (en) * 1987-11-10 1990-10-16 Matsushita Electric Industrial Co., Ltd. Chemical vapor deposition reaction apparatus having isolated reaction and buffer chambers
US6302962B1 (en) * 1998-06-23 2001-10-16 Samsung Electronics Co., Ltd. Diffusion system having air curtain formation function for manufacturing semiconductor devices and method of controlling the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4962726A (en) * 1987-11-10 1990-10-16 Matsushita Electric Industrial Co., Ltd. Chemical vapor deposition reaction apparatus having isolated reaction and buffer chambers
US6302962B1 (en) * 1998-06-23 2001-10-16 Samsung Electronics Co., Ltd. Diffusion system having air curtain formation function for manufacturing semiconductor devices and method of controlling the same

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