JPS63239862A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To accelerate a writing without increasing manufacturing steps by providing a first word line extended from the gate electrode of MISFET of a memory cell and a second word line separately from the first line, and forming wirings for supplying a stationary potential at the same layer as the second line. CONSTITUTION:A memory cell is formed of a flip-flop circuit and transfer MISFETs Qt1, Qt2 connected between a pair of input/output terminals and complementary data lines DL, DL'. The source regions of driving MISFETs Qd1, Qd2 are connected to wirings 12A for supplying a reference voltage Vss to the memory cell. A first word line WL5 is formed by integrating and extending the gate electrodes of MISFETs Qt1, Qt2 of a plurality of memory cells. A second word line WL12B is extended in parallel with a first word line WL5. The line WL12 is composed of the same level layer as reference voltage wirings 12A. Thus, the resistance of the word line can be reduced by the formation of the second line 12B, and the stationary potential supply wirings 12A and the second line 12B to the memory cell are formed of the same layer, thereby reducing the manufacturing steps.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular, a technology that is effective when applied to a semiconductor integrated circuit device (hereinafter referred to as SRAM) equipped with a single static random access memory. It is related to.

[Conventional technology]

An SRAM memory cell, for example, includes two high-resistance load elements and two driving MISFETs (Metal
Insulator Sem1conductor F
It is composed of a flip-flop circuit composed of a field effect transistor) and two transfer MISFETs connected to a pair of input/output terminals of the flip-flop circuit. The high resistance load element is made of a polycrystalline silicon film formed integrally with the power supply voltage wiring in order to reduce the memory cell area and achieve high integration. Such an SRAM is described in, for example, Japanese Patent Laid-Open No. 130461/1983.

[Problem that the invention seeks to solve]

The present inventor has studied improvements in reliability, high speed, and high integration in SRAMs typified by high resistance load types.

In order to increase the speed, it is preferable to use wiring with even lower resistance, such as an aluminum layer, as the word line. In addition, in order to increase the write/read margin of memory cells and prevent information inversion (soft errors) due to alpha rays, etc., wires with low resistance are used as wires for supplying ground potential to memory cells. For example, it is preferable to use an aluminum layer. Furthermore, it is preferable to avoid increasing the number of wiring lines, decreasing the degree of integration, and complicating the manufacturing process in order to simultaneously satisfy these requirements.

An object of the present invention is to increase the speed of a semiconductor memory device such as an SRAM.

Another object of the present invention is to improve the reliability of semiconductor memory devices such as SRAM.

Another object of the present invention is to provide a technique that can achieve the above object without reducing the degree of integration.

Another object of the present invention is to reduce power consumption of a semiconductor memory device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

A first word line formed by extending the gate electrode of the MISFET of the memory cell and a second word line separate from this.
A word line is provided. On the other hand, the same layer as the second word line forms a wiring for supplying a fixed potential such as a ground potential to the memory cell.

[Effect]

According to the above means, the resistance of the word line can be lowered by forming the second word line, and the fixed potential supply wiring to the memory cell and the second word line are formed in the same layer.・There is less increase in the manufacturing process.

〔Example〕

FIG. 1A shows a circuit of an SRAM memory cell according to a first embodiment of the present invention.

As shown in FIG. 1A, one memory cell MC of the SRAM is connected to a pair of complementary data lines DL, DL and a first word line W.
It is provided at the intersection with L(5).

The memory cell includes a flip-flop circuit and a transfer (memory cell selection) MISFETQt connected between a pair of input/output terminals thereof and complementary data lines DL, DL.
, ,Qt,. A first word line W L (5) is connected to the gates of the MISFETs Qt, , Qt. The flip-flop circuit (latch circuit) is a high-resistance element R8 as a load element and a MISFETQ for driving R11.
It is formed by cross-coupling (mutually supplying one input to the other output) two inverter circuits consisting of d1 and Qat. The input and output of the flip-flop circuit are common. One end of the high resistance element R is connected to a wiring 10B for supplying power supply voltage Vcc to the memory cell, and the other end is connected to the drain region of the driving MISFET Qd. The source region of the driving MI8FETQd is connected to a wiring 12A for supplying a ground potential (reference voltage) Vss to the memory cell.

For example, the power supply voltage (operating voltage) Vcc (=5V) of the circuit is applied to the power supply voltage wiring 10B, and the reference voltage wiring 1
2A, for example, the circuit ground voltage Vs+a (=QV)
is supplied.

The first word line W L (5) is connected to M of a plurality of memory cells.
The gate electrodes of ISFETs Qt, , Qt, are integrated and extended. First word line W L (5
) A second word line WL (13) extends parallel to the second word line WL (13).

The second word line WL (according to the present invention, it is formed of a layer at the same level as the reference voltage wiring 12A).

As shown in FIG. 1B, a plurality of first word lines WL(5)
A memory array M-ARY is constituted by a plurality of complementary data lines DL, DL, and a plurality of memory cells MC corresponding to their intersections.

In this embodiment, the first and second word lines WL(5) and WL(13 are short-circuited to each other at both outer ends of the memory array M-ARY. In other words, one first word line W
L (5) is shunted by one second word line WL (15) to reduce its resistance.
In this embodiment, the same word line selection signal is applied to the second word lines WL(5) and WL(13).

The memory cell of the SRAM which is the first embodiment of the present invention is
It is shown in Fig. A (plan view), and Fig. 3 (sectional view) is a cross section taken along the line ■--■ in Fig. 2A. FIG. 2B is a schematic diagram showing the outline of this embodiment, and corresponds to FIG. 2A.

4 to 6 are plan views showing a part of one memory cell in order to make it easier to understand the shape of each conductive layer shown in FIG. 2A, and correspond to FIG. 2A. In FIG. 2A and FIGS. 4 to 6, insulating films other than the field insulating film provided between each conductive layer are not shown in order to make the structure of this embodiment easier to understand, and data lines DL, A part of DL is omitted.

In FIGS. 2A, 2B, and 3, 1 is a p-type semiconductor substrate (or well region) made of single crystal silicon.
It is. 2 is a field insulating film, and 3 is a p-type channel stopper region.

As shown in FIGS. 2, 3, and 4, the field insulating film 2 is formed on the upper main surface of the semiconductor substrate 1 so as to surround the formation region of MISf"ETQt, Qd and define its shape. The field insulating film 2 is provided at the MI
sFETQt, (or Qt and Qat (or Qctt)
) are defined so that they can be arranged diagonally and separated from each other in a memory cell formation region having a substantially rectangular shape. The field insulating film 2 is MISFE
TQt! (or Qt, ) and Qat (or Qd,) are defined so that they can be integrally formed and arranged on a diagonal line that intersects the diagonal line.

In FIG. 2A, one memory cell is defined by the X--X line on its upper and lower sides, and the Y--Y line on its left and right sides. The memory cells adjacent to the left and right are Y
- Line symmetric with respect to Yiiil, and arranged <Silver. For example, memory cells MC0O and MC shown in FIG.
0I is symmetrical about the Y-Y line. Vertically adjacent memory cells are connected to the reference voltage line 12A or the power supply voltage line 1.
They are arranged so as to share 0B. 2A, a point-symmetrical memory cell is connected to the memory cell in FIG. 2A and the reference voltage line 1 with respect to the point XA at
2A (and source region 8). For example, 1B
Memory cells MC0O and MCl0 shown in the figure have this relationship. These two memory cells are arranged as one unit in a staggered manner in the vertical direction.

According to the above combing rules, the field insulating film 2
and other patterns are formed.

The channel stopper region 3 is provided on the main surface of the semiconductor substrate 1 under the field insulating film 2 .

The field insulating film 2 and channel stopper region 3 electrically isolate semiconductor elements.

As shown in FIG. 4, on the main surface of the semiconductor substrate 1 in the region surrounded by the field insulating film 2, MI8FETs Qd, , Qd, constituting a memory cell are formed.

Qt, ,Qt, are provided. That is, MI8F
ETQd, , Qd, , Qt, , Qt, are semiconductor substrate 1
, a gate insulating film 4, a gate electrode 5, a pair of n-type semiconductor regions 6 serving as source or drain regions, and a pair of n+-type semiconductor regions 8.

The gate insulating film 4 is composed of a silicon oxide film formed on the main surface of the semiconductor substrate 1 by thermal oxidation.

The gate electrode 5 is made of a polycrystalline silicon film formed by CVD and a refractory metal silicide (MoSi, Taxit, TiSi, etc.) formed by sputtering on top of the polycrystalline silicon film.

It is composed of a polycide film consisting of a WSi, ) film. Impurities (As and/or P) are introduced into the polycrystalline silicon film to reduce the resistance value. The gate electrode 5 is made of a polycrystalline silicon film, a high melting point metal (Mo, T
a, T i , W) film or a single layer film of a high melting point metal silicide film, or a composite film in which a high melting point metal film is provided on a polycrystalline silicon film. In other words, it consists of a conductor skin containing a high melting point metal and/or silicon.

The gate electrode 5 of MI8FETQd is a trap as shown in FIG.
MI8FETQt is electrically connected to the - semiconductor region 8 through the MI8FETQt. One end and the other end of the gate electrode 5 of MISFETQd are electrically connected to the semiconductor region 8 of one of MI8FETQt and MISFETQd through the respective connection holes 4A. That is, 2
Gate electrode 5 is used as a wiring for cross-coupling two inverters, and other wiring layers are not used.

A word line (WL) 5 is made of the same conductive material and the same conductive layer as the gate electrode 5. That is, the word line 5 is MI8FETQt,,Qt.

is formed integrally with the gate electrode 5 of the field insulating film 2.
It is provided by rolling the upper part of the cloth in the column direction.

The semiconductor region 8 is configured to constitute a high impurity concentration region of a source region or a drain region. This semiconductor region 8 is formed by introducing impurities using an ion implantation technique using a self-aligned mask (sidewall spacer or sidewall insulating film) 7 on the side of the gate electrode 5. constitutes a low impurity concentration region of the source region or drain region. Although the semiconductor region 6 is omitted in FIG. 4, it is a MI8FETQt.

A known LDD (Lightly Doped Dr.
ain) structure MISFET is configured. These MI
SFET is 8ingle drain, double
Drain and other known structures.

Reference numeral 7A denotes an insulating film, which is provided above the gate electrode 5, word line 5, and semiconductor region 8. The insulating film 7A is made of, for example, a silicon oxide film formed by CVD or thermal oxidation.

An insulating film 9 is provided on the insulating film 7A so as to cover J, MISFE'rQt, and Qd. The insulating film 9 is
For example, it is made of a silicon oxide film formed by CVD. Reference numeral 9A denotes a contact hole, which is provided by removing insulating films 7 and 9 above a predetermined semiconductor region 8.

The high resistance element (R,,R,) IOA is shown in FIG.

As shown in Fig. 3 and Fig. 5 (plan view), the code 10A
It is provided on the insulating film 9 within a region surrounded by a chain double-dashed line. t#), a chain double-dashed line 10A indicates the shape of a mask made of a photoresist film when introducing impurities for forming a wiring 10B, which will be described later. double-dot chain filO
No impurities are introduced into A. The high resistance element 10A is
One end is electrically connected to the semiconductor region 8 through the conductive layer 10B and the connection hole 9A, and the other end is electrically connected to the power supply voltage wiring 10B extending on the insulating film 1. The power supply voltage arrangement 110B is made of the same conductive material and the same conductive layer as the high resistance element 10A.

The high-resistance element 10A and the power supply voltage wiring 10B are composed of polyjunction≦silicon film (semiconductor).

That is, the high resistance element 10A is made of a polycrystalline silicon film into which no impurity to reduce the resistance value is introduced, as shown by hatching in FIG. Power supply voltage distribution
1ll OB, to reduce the resistance value, for example, nf
It is composed of a polycrystalline silicon film into which i impurities (As, P) are introduced. The power supply voltage wiring 10BK is, for example, a 5X polycrystalline silicon film into which no impurities are introduced.
Arsenic (A
s) by introducing it using ion implantation technology.

As is clear from FIGS. 2A, 3, and 5, the resistive element R8°R1 is formed substantially on the gate electrode 5 in order to reduce the size of the memory cell. As a result, a parasitic MI consisting of the gate electrode 5, gate insulating film 9, source or drain region 10B, and channel region 10A is created in the memory cell.
If there are 8 FETs, then This first parasitic MI8
The FET is effective in stabilizing the state of the flip-flop circuit constituting the memory cell and in performing a write operation at high speed.

Note that the high resistance element 10A and the power supply voltage wiring 10B may be formed of a single crystal silicon film or an amorphous silicon film on the insulating film 9.

11 is, for example, a silicon oxide film made by CVDK,
This is an insulating film that covers the high resistance element 10A and the power supply voltage wiring 10B. This insulating film 11 includes MISFETQd and Q
Insulating film 7A, 9.11 above the other semiconductor region 8 of t
' is removed to provide a connection hole 11A.

The reference voltage queen ls12A passes through the connection hole 11A and connects to the MI
It is electrically connected to the semiconductor region 8 which is the source of the 8FETQd, and is provided extending above the insulating film 11 in the same direction as the word line 5. In this embodiment, the reference voltage wiring 12A is connected to a high resistance element (R5゜"2) IOA as shown in FIGS. 2A, 2B (indicated by dotted lines), FIGS. 3 and 6, although not particularly limited thereto. At least the power supply voltage wiring 10 of
It is configured to cover the side connected to B. That is, as will be described later, the wiring 12A functions as a wiring for supplying the reference voltage of the memory cell (for example, the circuit ground potential Vss=OV), and serves as a wiring for supplying the reference voltage of the memory cell (for example, the circuit ground potential Vss=OV), and as a wiring for supplying the resistive element 10A with other wiring layers (for example, , data #JDL.

It functions as a shield layer to block (reduce) the electric field from DL).

In this embodiment, the reference voltage wiring 12A is made of, for example, an aluminum film or an aluminum film containing an additive (8i, Cu).

In this way, by providing the wiring 12A to which a fixed potential is applied so as to cover most of the high resistance element 10A, the influence of the electric field effect from the layer above the wiring 12A (data m> is reduced (shielding effect)). In this case, the second parasitic MI8FET, which uses the data line as the gate electrode and the high resistance element 10A as the channel formation region, is not turned on, and the resistance value of the high resistance can be kept high and stable.

The second parasitic MISFET has a gate insulating film as an insulating film 1.
1 (and 13), the gate electrode is connected to the data line DL.

The DL (14) and the power supply voltage wiring 10B are configured as a drain region and the conductive layer 10B as a source region. In addition, the threshold voltage is the voltage applied to the data lines DL and DL, which are the gate electrodes of the parasitic MI8FET (for example, O
(v~sV) can also be set to a high value. Therefore, it is possible to prevent the formation of a channel in the high resistance load element 10A due to the electric field effect of the data lines DL and DL, and to reduce the fluctuation (increase) in the amount of current flowing through this high resistance element 10AK. Power consumption can be reduced.

Due to the wiring 12A, only the data lines DL and DL (,
The influence of high electric field effects from outside the SRAM device can also be reduced.

A reference voltage Vss is applied to the wiring 12A, and even if the potential of the data line fluctuates, the potential can be stably maintained, so that fluctuations in the threshold voltage of the parasitic MI8FET can be reduced.

By configuring the reference voltage wiring 12A with a conductive material with a small specific resistance value such as an aluminum film, it is possible to increase the extraction speed (information clearing speed) of information stored in the memory cells. It is possible to speed up the write operation. Also, for the same reason, it is possible to speed up the extraction of information stored in the memory cell, so that information "1" (high level 'approximately 4V) and ff information "0"
(low level: 0■), that is, the information “1” or ′
0'' judgment margin can be increased.

Therefore, malfunctions in information read operations can be prevented, and the electrical reliability of the SRAM can be improved.

By making the wiring layer 12A perform the two functions described above, the line width can be formed extremely wide. Therefore, the resistance of the wiring layer 12A can be almost ignored, and the above-mentioned effect becomes even greater when viewed as a reference voltage supply line for memory cells.

Note that the threshold voltage of the second parasitic MI8FET is
It is determined by the pinch-off point near the drain region. Therefore, as mentioned above, the reference voltage wiring 12A is
It is sufficient to provide it so as to cover at least the high resistance element 10A on the side of the power supply voltage wiring 10B.

As shown in FIG. 6, a second word line (WL) 12B and a conductive layer 12C are provided in the same conductive material and layer as the reference voltage wiring 12A.

827-)'', 1112B are provided on the insulating film 11, extending in the same direction as the reference voltage queen [12A and the first word line 5.
Consists of multiple aluminum layers.

In this way, when the first word line 5 is connected (shunted) to the second word line 12B, which has a smaller specific resistance value, the resistance value of the word line as a whole can be made smaller. Therefore, it is possible to speed up the information writing and reading operations.

Since the second word line 12B is made of layers at the same level as the reference voltage line 12A, the manufacturing process is not complicated.

The second word line 12B is provided at a position that does not overlap with the first word [5] to prevent a short circuit with the conductive layer 12C. To do this without increasing the memory cell area, the second word line 12B is placed over the conductive layer 10B and the resistor 10A.

In order to realize this arrangement, the wiring layer 12A as a shield layer is not formed on a part of the resistor 10A.

Note that the second word line 12B is connected to the memory array M-ABY.
Each memory cell arranged in the column direction or each predetermined number (for example, 8, 16, or 32) of memory cells is short-circuited to the first word line 5 through a connection hole provided in the insulating film 11. Good too.

The conductive layer 12C has one end passed through the connection hole 11A
It is electrically connected to the other semiconductor region 8 of ISFETQt, and the other end portion extends above the insulating film 11. This conductive layer 12C is a data line DL made up of the other semiconductor region 8 of the MISFET Qt and a second aluminum layer, which will be described later.

Electrically connect with DL. That is, the conductive layer 12C is formed to reduce the step difference in the connection hole connecting the two and to improve the step coverage of the data lines DL and DL made of aluminum.

Reference numeral 13 is an insulating film made of, for example, a silicon oxide film formed by CVD, and is provided to cover the reference voltage wiring 12A, the word line 12B, and the conductive layer 12C.

13A is a connection hole, and an insulating film 13 on top of the conductive layer 12C
It is provided by removing the .

Reference numeral 14 denotes data lines (DL, DL), which are electrically connected to the conductive layer 120 through the contact hole 13A, and are provided on the insulating film 13 so as to extend in the row direction.

The data line 14 is made of, for example, the same conductive material (aluminum film) as the reference voltage queen @12A.

In this way, the 8RAM of this embodiment is composed of two layers of low-resistance wiring made of aluminum film. The first layer of low resistance wiring includes a reference voltage wiring 12A and a word line 12B.
and the conductive layer 12C, and the second layer low resistance wiring is
It constitutes the data line 14.

FIG. 7 shows another embodiment of the present invention in which the influence of field effects from data lines and the like is significantly reduced and the word line resistance is reduced in an SRAM memory cell.

The differences between the memory cell of FIG. 7 and that of FIG. 2A will be explained below.

In the memory cell shown in FIG. 7, the second word line 12B is provided at a position substantially overlapping with the first word line 5, and the second word line
The reference voltage wiring 12A1 is configured to extend to a region not short-circuited with B. One side of the conductive layer 12C (
In this embodiment, the data line DL side) extends to the side opposite to the first word line 5. That is, in the memory cell of FIG. 2A, the conductive layer 12C extending over the first word line 5 is formed on the opposite side. As a result, the reference voltage wiring 12A
However, the high resistance load element (R, tRl) can be formed so as to cover substantially the entire area of the IOA.

In this way, by providing the reference voltage queen @12A so as to cover almost the entire area of the high resistance element 10A, the influence of the electric field effect from the data line 14 or the outside of the device can be reduced. Prevents malfunction of internal circuit and 8R
AM power consumption can be reduced.

Note that in this embodiment, the conductive layer 12C on the data line DL side
Therefore, the memory cell area is increased compared to the memory cell of FIG. 2A.

According to the new technology disclosed in this application, the effects described below can be obtained.

(1) By connecting the second word IiI in parallel with the first word line, the resistance of the word line as a whole can be reduced. In particular, a great effect can be obtained by forming the second word line from a material that has a smaller resistance than the material for the first word line, such as aluminum.

(2) Since the second word line is formed above the memory cell, the speed can be increased without increasing the memory cell area.

(3) Since the reference voltage wiring is formed even on the elements constituting the memory cell, the width of the wiring can be increased. This, in conjunction with the use of low resistance materials such as aluminum, results in extremely low resistance wiring. Therefore, it becomes unnecessary to reduce the resistance by connecting (shunting) other wiring layers.

(4) Since the second word line and the reference voltage wiring are composed of layers at the same level (layers formed by the same manufacturing process), the manufacturing process is not complicated.

(5) SR equipped with a memory cell having a semiconductor resistance element
In AM, since a conductive layer (shield layer) that reduces the influence of electric field effects such as data lines is provided to cover the semiconductor resistance element, it is possible to reduce fluctuations in the amount of current flowing through the semiconductor resistance element. This makes it possible to reduce the increase in the amount of current flowing through the semiconductor resistance element, thereby reducing power consumption.

(6) Since the fixed potential applied to the shield layer is the reference potential, the potential of the shield layer can be stabilized.

(7) Since the shield layer consists of the reference voltage wiring, the shield layer and the wide reference voltage wiring can be formed without increasing the memory cell area.

(8) Since the reference voltage wiring is wide and made of a material with a low resistance value, the reference voltage wiring can draw out the charge of the S storage node quickly, which speeds up the information writing operation. can be achieved. As a result, the margin for determining information can be increased, thereby preventing malfunctions in the information reading operation and improving electrical reliability.

(9) Since the data line, word line, and reference voltage wiring are made of aluminum, which is a conductive material with a small specific resistance value, it is possible to speed up information writing and reading operations.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

The second word lines may be formed not in correspondence with the first word lines but in correspondence with 2.4, 8.16, etc. of the first word lines. At this time, the second word line is formed in a region not above the memory cell.

FIGS. 8A and 8B show an example in which one second word line is formed for four first word lines.

As shown in FIG. 8A, the second word line 12B made of the second aluminum layer is not formed on the memory cell.

Utilizing this fact, the reference voltage wiring 12A formed in the same layer as the second word line is made to have the same shape as the example shown in FIG.

That is, this reference voltage wiring 12A is connected to a high resistance element (R
+, Rt) is provided so as to cover substantially the entire area of the IOA. By providing the reference voltage wiring 12A so as to cover almost the entire area of the high resistance element 10A, the influence of the electric field effect from the data line 14 or the outside of the device can be greatly reduced, thereby preventing malfunction of the internal circuit. At the same time, it is possible to reduce the power consumption of the SRAM. On the other hand, the conductive layer 12C has the same shape as the example of FIG. 2A (FIG. 6), taking advantage of the absence of the second word line. This does not mean that the memory cell area increases as in the example of FIG. 7 in order to reduce power consumption.

On the other hand, the relationship between the first word line 5 and the second word line (12B) made of the second aluminum layer, which is not shown in FIG. 8A, is shown in FIG. 8B. In FIG. 8B, the first word line is shown as a sub-word line or divided word line DWL to distinguish it from the second word line WL. Memory cells MC are formed corresponding to the intersections of the first word line DWL and the complementary data lines DL, DL.

A 1jg20 decoder (not shown) forms a selection signal for the second word line WL based on signals excluding 2 bits of the row address signal. 10th Udecoder XDCR
I forms a selection signal for the first word @DWL based on the selection signal for the second word line WL and the 2-bit lock address signals axo and axl. The 27th word line 1iWL, which is the main word line, is used as a common signal for the plurality of 10th word line decoders. Since the second word line has a low resistance value and the parasitic capacitance added to it is small,
Speed can be increased.

The second word line and the reference voltage wiring may be formed of a layer other than the first aluminum layer.

The second word line and the reference voltage wiring may be made of a second aluminum layer. In this case, the data line is formed by the first aluminum layer. A conductive layer for connecting the data line and the semiconductor region 8 is not formed or is formed by the conductive layer 10B. On the other hand, in order to connect the reference voltage wiring and the semiconductor region 8, it is desirable to form a conductive layer made of the first aluminum layer in the same manner as the conductive layer 12G.

On each side of FIGS. 2A, 7, 8A, and 10, a conductive layer for connecting the data line to the semiconductor region 8 may not be formed.

The present invention may be applied to an 8RAMK having 7 lip-flop circuits composed of complementary MISFETs and having 9 memory cells. %Ks When a p-channel MI8FET is formed using a (polycrystalline) silicon film formed on a substrate, a reference voltage is applied to cover the film to reduce the influence of electric field effects from data lines, etc. Just configure the wiring.

The present invention 8A may be applied to an SRAM having a memory cell configured such that a high resistance load element is embedded in a pore provided in a semiconductor substrate. In this case, the power supply voltage may be supplied to the memory cell from the semiconductor substrate side, and the second word line and reference voltage wiring may be formed of a conductive layer (such as an aluminum film) having a small specific resistance value.

The present invention provides resistances R, , R in the circuit of FIG.

It can also be applied to 8RAM having memory cells without. The shape of the memory cell in this case is similar to the memory cell of FIG. 9 plus a data line (shown in FIG. 2A). In this case, the resistances R,,R.

Since there is no need for a connection area between the area 8 and the area 8, the area can be reduced accordingly.

In the present invention, peripheral circuits such as a decoder and a human output buffer may be composed of a so-called Bi-0M08 circuit composed of a bipolar transistor and a complementary MISFET.

In particular, bipolar transistors are used in ECL to increase speed.
When operating at the (emitter coupled logic) level, the power supply voltage Vcc and the ground potential Vss on each side mentioned above are replaced by the ground potential Vss and the negative power supply potential VEX, respectively.

It is also possible to use a combination of the embodiments described above. For example, in the example of FIG. 8A, the data line may be formed from the first aluminum layer, and the second word line and the reference potential line may be formed from the second aluminum layer.

Various modifications can be made to circuit elements such as MISFETs and resistors that constitute memory cells.

The present invention is applicable not only to SRAM but also to semiconductor memory devices having word lines and reference voltage lines for memory cells, such as mask type ROM (Read Only Memory), E
electrically programmable R
It can be widely applied to OM (E P ROM), etc.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the MISF of the static RAM memory cell
It has a first word line formed by extending the gate electrode of ET and a second word line separate from this, and is grounded to the memory cell in the same layer as the second word line. By forming a wiring that supplies a fixed potential such as a potential, speeding up can be achieved without increasing the number of manufacturing steps.

[Brief explanation of the drawing]

FIG. 1A is a circuit diagram of an SRAM memory cell according to a first embodiment of the present invention, FIG. 1B is a conceptual diagram of a memory array of an SRAM according to the present invention, and FIGS. 2A and 2B are a circuit diagram of a memory cell of an SRAM according to the present invention. One example is S
A plan view and a conceptual diagram of a RAM memory mole, FIG. 3 is a sectional view taken along the line ■-■ in FIG. 2A, and FIGS. FIG. 7 is a plan view showing a part of the cell; FIG. 7 is a plan view of an SRAM memory cell according to another embodiment of the present invention; FIGS. 8A and 8B are diagrams showing other embodiments of the present invention. . In the figure, 1... semiconductor substrate, 4... gate insulating film, 5
...Gate electrode or word line, 6,8...Semiconductor region, IQA, R...High resistance load element (semiconductor resistance element), 10B, Vcc...Power supply voltage wiring, 12A, Vs
s...Reference voltage wiring, 12B, WL...Word line,
12C...Petestal conductor kN, 14. DL: data line, Qd: MISFBT for driving, Qt: MISFET for transfer. Figure 2 B Ku○'' - ○ times sweet l Figure 4 Figure 5 Figure 6 Figure 10, Vcc 'IIA Figure 7 Figure 8 A Figure 8 B

Claims (1)

[Claims] 1. A plurality of first word lines extending in a first direction; and a plurality of first word lines extending in the first direction and provided corresponding to the plurality of first word lines. two word lines, a plurality of data lines extending in a second direction, a plurality of memory cells arranged corresponding to the intersections of the first word line and the data line; A semiconductor memory device comprising: a second word line for supplying a reference voltage to the second word line;