JPS63239698A - Auxiliary test circuit for semiconductor storage device - Google Patents

Abstract

PURPOSE:To simplify a test pattern for fixing a compared result at a constant value and comparing the value with a response result by inputting an input sequence repeating '1' and '0' to a prescribed address, inputting the output data of adjacent 2 bits in the serial data to a comparator and comparing these inputs. CONSTITUTION:The values of scanning registers SRbn, SRb(n-1) of a scanning path through a parallel output terminal 5b are set as two input parts. Test data '0101-01' or '1010-10' are inputted to a RAM 8 through a scanning path 7a, its response result is obtained again in the scanning path 7a and then the response result of the RAM 8 is transferred while shifting the result every bit in the scanning registers SRb(n-1), SRbn in the scanning path 7b. When the RAM 8 is normal, two input parts of an exclusive OR gate 10 become '0' and '1' without fail, so that the value of an output terminal 11 is fixed on '1'. Consequently, the test pattern can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test auxiliary circuit for a semiconductor memory device for facilitating testing of a semiconductor memory device built into, for example, a large-scale integrated circuit.

(Prior Art) FIG. 3 is an explanatory diagram of the configuration of a scan canvas used in a conventional RAM test auxiliary circuit.

In the figure, SR1 to SR are scan registers, each connected in series to form a shift register. 1.2.3 are a serial input terminal, a serial output terminal, and a serial shift clock terminal, respectively. When a predetermined clock is input to the serial shift clock terminal 3, the contents of the scan register SRo are output from the serial output terminal 2. , the contents of scan registers SR to SR are shifted to scan registers SR2 to SRo, and input data from serial input terminal 1 is transferred to scan register SR.
1.

4.5.6 are a parallel input terminal, a parallel output terminal, and a parallel input clock terminal, respectively. When a predetermined clock is input to the parallel input clock terminal 6, it is input from the parallel input IF-4 to the scan registers SR1 to SRo. Ingest data in parallel. In addition, parallel output terminal 5
The contents of the scan registers SR1 to SRo are always outputted from the registers SR1 to SRo.

Since the scan path has the above-mentioned performance, serial test data is taken into the serial registers SR1-SR1 from the serial input terminal 1, and the test data of the circuit under test such as RAM is input through the parallel output terminal 5. Input test data in parallel from the data input terminal.

After that, the response result of the circuit under test is sent to the serial register SR in parallel from the data output terminal of the circuit under test.
1 to SRo, serially take out the data from the serial output terminal 2, and compare it with a test pattern which is an expected value series to be compared with the response result, thereby making it possible to test the circuit under test. This method is widely used because it requires fewer terminals for testing than the method of directly outputting test data to external terminals, and has the advantage that the conductor device can be configured in a balanced manner.

FIG. 4 is a circuit diagram of a conventional RAM test auxiliary circuit using the scan path shown in FIG. In the same figure, 7a and 7b are the scan paths shown in FIG. 3, SR to SR, SJ, 1ai an to S Rbn are the scan registers of the scan paths 7a and 7b, respectively, and 8 is the RAM to be tested, 9 is RAM
This is the data output terminal. Note that 2a, 3a, 4a, 6a
are the serial output terminal, serial shift clock terminal, parallel input terminal, and parallel input clock terminal of the scan path 7a, and 1b, 2b, and 3b are the serial input terminal, serial output terminal, and serial shift clock terminal of the scan path 7b, respectively. be.

The RAM 8 has already been input with predetermined test data, and by inputting a predetermined clock from the parallel input clock terminal 6a to the scan pass 6a, the response result is sent from the data output terminal 9 to the scan pass 6a via the parallel input terminal 4a. Take it into 7a. Next is the serial shift clock terminal 3a.

3b, a predetermined Otsuku is sent to the bus 7a.

7b, the response result of RAM 8 stored in the scan path 7a is shifted one bit at a time and is sequentially output from the serial output terminal 2a, and is sequentially input from the serial input ill (l) of the scan path 7b. be done.

By continuing this operation, the response result of RAM 8 is read bit by bit from the serial output terminal P2b of scan path 7b, and compared with the test pattern.
Conduct the test.

By using the S1 bus in this manner, the number of external terminals required for testing can be reduced, regardless of the number of data output terminals of the RAM 8.

In addition, although FIG. 4 shows an example in which the scan paths 7a and 7b are connected in series for reasons such as conducting the restoration RAM test in parallel, it is also possible to connect the scan paths 7a and 7b in series. , RAM 8 bit by bit from serial output terminal 2a
Of course, the RAM 8 can be tested by reading out the response results.

[Problem that the invention seeks to solve]

In the conventional test auxiliary circuit for semiconductor memory devices such as RAMs described above, rolol...
01J (binary number) and "1010...10" (binary number) input series are often used, but in such cases, the test pattern is also rolol...Oll, rlol.
For example, if the data configuration unit of a semiconductor memory device is 8 bits, it is necessary to prepare 8 patterns such as rlolololoJ or rololololJ, and there is a problem that the efficiency of the test pattern cannot be improved. .

This invention was made to solve the above-mentioned problems, and rolol...01J, rl.

10...10" is used as test data for a semiconductor memory device, the purpose is to simplify the test pattern to be compared with the response result of the semiconductor memory device.

[Means for solving problems]

The test auxiliary circuit for a semiconductor memory device according to the present invention includes:
When testing semiconductor memory devices, “1” and “
0'' is input to a predetermined address of the semiconductor memory device, the response result of the semiconductor memory device is taken in as serial data from the data output term f, and the instantaneous 2-bit output data of the serial data is The data is input to a comparator circuit, and the semiconductor memory device is tested according to the comparison result in the comparator circuit.

[Effect]

Since the comparator circuit in this invention inputs adjacent 2-bit output data of the semiconductor memory device, if the tested conductive memory device is normal, the two input parts are always 0" and "1". As a result, the comparison circuit can set the comparison result to a constant value of "0" or "1".

〔Example〕

FIG. 1 is a circuit diagram showing a RAM test auxiliary circuit according to an embodiment of the present invention. 1 to 9 in the same figure.
SR-, -8R, 5Rb1-sRb.

al an is the same as before, so its explanation will be omitted. 1o is exclusive OR
(hereinafter referred to as rEOR gate), and uses the values of scan registers 5Rbo and 5Rb (.-1) of scan path 7b as two input parts via parallel output term F 5 b. The output terminal 11 of this EOR gate 10 becomes the serial output section of this RAM test auxiliary circuit.

In such a configuration, the test data “0101.
. . 01'' or rlolo . . . 10'' is input into the RAM 8 by the scan path 7a, the response result is again obtained in the scan path 7a, and then the scan register 5Rb (.-1) of the scan path 7b.

While being shifted by 1 bat to S Rb, RAM8
The above response results are transferred. At this time, if the RAM 8 is normal, the two input parts of the EOR gate 10 are always "0" and "1", so the value of the output terminal 11 is constant at "1". That is, it is sufficient to prepare "1" (one pattern) as a test pattern, and if the value obtained from the output terminal 11 is "O", it can be considered that the RAM 8 is defective.

Note that the two input parts of the FOR gate 10 are scan registers S R and (.-1) of the scan canvas 7a.

S.R. , the parallel output terminal 5a of the scan register SR of the scan canvas 7a, and the parallel output terminal 5b of the scan register 5Rb1 of the scan canvas 7b, or any two adjacent bits of the scan canvas 7b. Register S R, S
The same effect can be obtained by connecting to 2i parallel output terminals 5b of Rb(1+1)(i"l to n-13. However, the scan registers S Ran'SR, . . .
Regarding the contents of serial output terminal 2a.

It can also be taken out from 2b. Also EOR gate 10
Instead, for example, in an exclusive NOR gate, if the two input values are rOJ and "1", and in other cases (rO
A similar effect can be achieved by using a circuit whose output results are different for JrOJ or rlJrlJ).

FIG. 2 is a circuit diagram of a RAM test auxiliary circuit according to another embodiment of the present invention. In the same figure, SR-8R,
5Rb1 to 5Rbo and 1 to 11 are the same as in FIG. 1, so the explanation will be omitted. 12 is AND
This gate is inserted as one input of the EOR gate 10. One input of the AND gate 12 is obtained from the parallel output terminal 5b of the scan register 5Rb (.-1) of the scan canvas 7b, and the other input is obtained from the external control terminal 13.
I'm getting more. By inserting the AND gate 12 in this way, if "1" is given to the control terminal 13, it becomes equivalent to the RAM test auxiliary circuit of FIG. 1, and if "0" is given to the control terminal 13, the circuit shown in FIG. This is equivalent to the conventional RAM test auxiliary circuit. In other words, while leaving the previous functionality as is,
Furthermore, the function of the RAM test auxiliary circuit shown in FIG. 1 is added.

Note that the AND gate 12 may be inserted into either input section of the EOR gate 10. Furthermore, any circuit that can switch between the two functions described above using the fl and 1Jlil terminals 13 can be used in place of an AND gate.

Although the RAM test auxiliary circuit has been described in these embodiments, it goes without saying that the present invention can also be applied to test auxiliary circuits for other semiconductor memory devices.

〔Effect of the invention〕

As described above, according to the present invention, when the semiconductor memory device is normal, the comparison result by the comparator circuit becomes a constant value, so that the test pattern to be compared with the response result of the semiconductor memory device can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a RAM test auxiliary circuit which is an embodiment of the present invention, FIG. 2 is a circuit diagram of a RAM test auxiliary circuit which is another embodiment of the invention, and FIG. FIG. 4, which is an explanatory diagram of the campus configuration, is a circuit configuration diagram of a conventional r<AM test auxiliary circuit. In the figure, 7a and 7b are scan paths, 8 is RAM,
10 is FOR gate, 12$, tAND gate, SR
~SR, SR-8R, 5Rb1~1 n
alan S Rbn is a scan register. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 7a, 7b-m-Sukidanbasu 9 --- RAM 1O-EOR Eid 5Ra1~5Ran' -++ People, 〉,,. 5Rb1~5Rbn Figure 2 Ka12-ANDIT-To Figure 3 SR1~5Rn---Ski v>t, Jis 7 Figure 4 Procedural amendment (voluntary) Showa year, month, day 1, case indication Patent application 1986 -073339@2,
Name of the invention: Semiconductor storage device test auxiliary circuit 3, Person making the correction Representative Moriya Shiki 4 Name of agent (7375) Patent attorney Masuo Oiwa L'F: (Contact information 03 (213) 3421 Patent Department)'・, . 5. Target of correction: Akirat@♂ 6. Contents of correction (1) Correct "built-in" in the first line of page 2 of the specification field to "built-in."that's all

Claims (2)

[Claims] (1) When testing a semiconductor memory device, a repeated input series of "1" and "0" is input to a predetermined address of the semiconductor memory device, and the response results of the semiconductor memory device are serially output from the data output terminal. A test auxiliary circuit for a semiconductor memory device, characterized in that the output data of adjacent two bits of the serial data is input to a comparison circuit, and the semiconductor memory device is tested according to the comparison result in the comparison circuit. (2) inserting a gate circuit into one input of the comparison circuit;
2. The test auxiliary circuit for a semiconductor memory device according to claim 1, wherein one input of the gate circuit is one of the two adjacent output data, and the other input is a gate opening/closing control signal.