JPS63236360A - Gate turn-off thyristor - Google Patents

Gate turn-off thyristor

Info

Publication number
JPS63236360A
JPS63236360A JP6889187A JP6889187A JPS63236360A JP S63236360 A JPS63236360 A JP S63236360A JP 6889187 A JP6889187 A JP 6889187A JP 6889187 A JP6889187 A JP 6889187A JP S63236360 A JPS63236360 A JP S63236360A
Authority
JP
Japan
Prior art keywords
gate
ring
gate electrode
shaped
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6889187A
Other languages
Japanese (ja)
Inventor
Yukimasa Sato
佐藤 行正
Tsutomu Yao
勉 八尾
Isamu Sanpei
三瓶 勇
Arata Kimura
新 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6889187A priority Critical patent/JPS63236360A/en
Publication of JPS63236360A publication Critical patent/JPS63236360A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42308Gate electrodes for thyristors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744Gate-turn-off devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To obtain a gate turn-off thyristor (GTO) having a gate electrode structure suitable for the improvement of a breaking strength by a method wherein plural pieces of ring-shaped gate current collecting electrode plates are provided in such a way as to adjoin each of the multiple rings of cathode emitter layers arranged on a circular semiconductor substrate and a plurality of regions extended radially to the periphery of the substrate from its central part are provided in such a way that the gate current collecting electrode plates are mutually coupled with a gate electrode. CONSTITUTION:N-type cathode emitter layers 2 are arranged on a circular semiconductor substrate 1 in a sextuple ring-shaped radial form and a gate electrode is provides on a P-type cathode base layer to be exposed on their peripheries in such a way as to encircle the layers 2. The gate electrode has ring-shaped gate current collecting electrode plates 10 adjacent to each ring of the layers 2, regions 11 extended radially to the periphery part of the substrate 1 from its central part in such a way that the electrode plates 10 are mutually coupled with the gate electrode and a gate current collecting electrode plate 12 on the central part of the substrate. According to this structure, the resistance of the gate electrode can be uniformized in the whole within the surface of a large-diameter GTO element. Therefore, as the numerous unit GTOs are operated uniformly, the breaking strength can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はゲートターンオフサイリスタ(以下GT○と略
記)に係り、特に遮断耐量向上に好適な素子構造に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a gate turn-off thyristor (hereinafter abbreviated as GT○), and particularly to an element structure suitable for improving cut-off withstand capability.

〔従来の技術〕[Conventional technology]

GTOは一般に多数の単位GT○が配列された半導体基
体を有する。遮断耐量を向上するには全ての単位GTO
を均一に動作させなければならず、その為にはGTO素
子面内におけるゲート電極抵抗を均一化し各単位GTO
へのゲート信号の供給を一様にする必要がある。これに
有効な従来技術として、大電流GTOにおいては特開昭
59−86260号公報に記載のように、円形半導体基
体に配列されたカソードエミツタ層の多重リングの中間
にリング状のゲート集電電極板を設けた構造が提案され
ている。
GTO generally has a semiconductor substrate in which a large number of units GT◯ are arranged. To improve the cut-off withstand capacity, all units GTO
It is necessary to operate the GTO uniformly, and in order to do this, the gate electrode resistance within the GTO element plane must be made uniform, and each unit GTO
It is necessary to uniformly supply gate signals to the As a conventional technique effective for this purpose, in a large current GTO, as described in Japanese Patent Application Laid-Open No. 59-86260, a ring-shaped gate current collector is installed in the middle of multiple rings of cathode emitter layers arranged on a circular semiconductor substrate. A structure including an electrode plate has been proposed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術では、ゲート集電電極板を中心にして最も
中心側の単位GTOと最も外周側の単位GT’Oにおけ
るゲート集電電極板との距離の差が小さくなり、従って
ゲート電極抵抗の不均一が低減できる。しかしこの従来
技術を用いても直径701II11以上の大口径GTO
になると素子面内におけるゲート電極抵抗の不均一が大
きくなり遮断耐量の向上が困難であった。
In the above-mentioned conventional technology, the difference in distance between the gate current collector electrode plate in the centermost unit GTO and the outermost unit GT'O with respect to the gate current collector electrode plate becomes small, so that the difference in gate electrode resistance is reduced. Uniformity can be reduced. However, even if this conventional technology is used, large-diameter GTOs with a diameter of 701II11 or more cannot be used.
In this case, the non-uniformity of the gate electrode resistance within the device surface becomes large, making it difficult to improve the cut-off withstand capability.

本発明の目的は遮断耐量の向上に好適なゲート電極構造
を有するGTOを提供することにある。
An object of the present invention is to provide a GTO having a gate electrode structure suitable for improving cut-off withstand capability.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、円形半導体基体に配列されたカソードエミ
ツタ層の多重リングの各々に隣接するように複数個のリ
ング状のゲート集電電極板を設け、かつゲート電極に上
記ゲート集電電極板を互いに連結するように円形半導体
基体の中央部から周辺へ放射状に伸びた複数の領域を設
けることにより達成される。
The above object is to provide a plurality of ring-shaped gate current collector electrode plates adjacent to each of the multiple rings of cathode emitter layers arranged on a circular semiconductor substrate, and to attach the gate current collector electrode plate to the gate electrode. This is achieved by providing a plurality of regions extending radially from the center of the circular semiconductor substrate to the periphery so as to be connected to each other.

〔作用〕[Effect]

上記構造によれば、大口径GTOの素子面内全体におい
てゲート電極抵抗を均一化できるため、多数の単位GT
Oが均一に動作するので、遮断耐量を向上することがで
きる。
According to the above structure, the gate electrode resistance can be made uniform throughout the device plane of the large-diameter GTO, so that a large number of unit GT
Since O operates uniformly, the cut-off withstand capability can be improved.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

以下の図面中の同一物、相当物には同じ符号を付けた。Identical or equivalent parts in the drawings below are given the same reference numerals.

第1図は本発明を実施したGTOのカソード側平面図で
あり、円形GT○の1/4について示したものである。
FIG. 1 is a cathode side plan view of a GTO embodying the present invention, and shows one-fourth of a circular GT○.

円形半導体基体1にn型カソードエミツタ層2が6重リ
ング放射状に配列され、その周囲に露出するp型カソー
ドベース層にはカソードエミツタ層2を取り囲むよすに
ゲート電極が設けられている。ゲート電極は、エミツタ
層2の各リングに隣接するリング状のゲート集電電極板
1o、上記集@電極板10(以下リングゲートと記す)
を連結するように円形半導体基体1の中央部から周辺部
へ放射状に伸びた領域11(以下放射ゲートと記す)、
並びに円形半導体基体中央部のゲート集電電極板12(
以下センタゲートと記す)を有する。
N-type cathode emitter layers 2 are arranged radially in a six-fold ring on a circular semiconductor substrate 1, and a gate electrode is provided on the p-type cathode base layer exposed around the base layer so as to surround the cathode emitter layers 2. . The gate electrode includes a ring-shaped gate current collector electrode plate 1o adjacent to each ring of the emitter layer 2, and the above-mentioned collector@electrode plate 10 (hereinafter referred to as ring gate).
A region 11 (hereinafter referred to as a radiation gate) extending radially from the center to the periphery of the circular semiconductor substrate 1 so as to connect the
In addition, the gate current collector electrode plate 12 (
(hereinafter referred to as center gate).

第2図は本実施例の動作を説明する為の等価回路である
。一点鎖線で囲んだ部分がカソードエミツタ層2の多重
リングの一つを示し、GT○記号は単位GTOを表わす
。図を簡略化するため、リング数2個、一つのリング中
の単位GT○を2個としたが、以下の説明はリング数及
び単位GTO数が多数の場合にも適用できる。なお、セ
ンタゲートを外部ゲート端子Gに接続するものとする。
FIG. 2 is an equivalent circuit for explaining the operation of this embodiment. The part surrounded by a dashed line indicates one of the multiple rings of the cathode emitter layer 2, and the GT◯ symbol indicates a unit GTO. In order to simplify the diagram, the number of rings is two and the unit GT○ in one ring is two, but the following explanation can also be applied to a case where the number of rings and the number of unit GTOs are large. It is assumed that the center gate is connected to the external gate terminal G.

rG 、rRはそれぞれセンタゲート、放射ゲートの電
極抵抗、rRlとrQ2はリングゲートの電極抵抗、r
t、rz 、rl2は上記各ゲート以外の領域のゲート
電極の抵抗を示し、rQ、rR,rRl及びrQ2はr
l、rz、rl2に比べ十分小さな値となるように電極
パターンを設計する。ゲート端子から単位GTOa、b
、c、dのゲートに到るゲート電極の抵抗をそれぞれ、
ra、 rb、rc、 rdとして各抵抗とraとの差
を求めると、リングゲート及び放射ゲートを設けた場合
には lrb  ral=rRt l rC−ral = l rr+−ralI ra 
−ra l = l ru+ rRz −rGi設けな
い場合には l rb  ral=r’1 1 r’Cra l = rr+ rxzl ra−r
al =r1+rtz+rzとなる。上述したようにr
Gl  rR+  rR1+  rRl<rx、 r2
.rtxであるから、リングゲート及び放射ゲートを設
けることによりraと各抵抗の差が小さくなる。すなわ
ち、GTOの素子面内においてゲート電極抵抗を均一化
できるため各単位GTOに供給されるゲート信号が一様
になり動作の均一性が良好になるので、遮断耐量を向上
する効果がある。なお、外部ゲート端子に接続されるの
はセンターゲートに限らずリングゲートあるいはこれら
両者でもかまわないが、特にセンタゲートを接続する場
合にはパッケージが簡単な構造となり安価になる効果が
ある。
rG and rR are the electrode resistances of the center gate and radiation gate, respectively, rRl and rQ2 are the electrode resistances of the ring gate, r
t, rz, rl2 indicate the resistance of the gate electrode in the region other than each gate, and rQ, rR, rRl and rQ2 are r
The electrode pattern is designed so that the values are sufficiently smaller than l, rz, and rl2. Unit GTOa, b from gate terminal
The resistance of the gate electrodes reaching the gates of , c and d are respectively,
When calculating the difference between each resistance and ra as ra, rb, rc, and rd, when a ring gate and a radiation gate are provided, lrb ral=rRt l rC-ral = l rr+-ralI ra
-ra l = l ru+ rRz - If rGi is not provided, l rb ral=r'1 1 r'Cra l = rr+ rxzl ra-r
al = r1 + rtz + rz. As mentioned above, r
Gl rR+ rR1+ rRl<rx, r2
.. rtx, the difference between ra and each resistance becomes smaller by providing a ring gate and a radiation gate. That is, since the gate electrode resistance can be made uniform within the element surface of the GTO, the gate signal supplied to each unit GTO becomes uniform, and the uniformity of the operation is improved, which has the effect of improving the cut-off withstand capability. It should be noted that what is connected to the external gate terminal is not limited to the center gate, but may also be the ring gate or both, but especially when the center gate is connected, the package has the effect of having a simple structure and being inexpensive.

第3図は本発明の他の実施例のGTOを示す図である。FIG. 3 is a diagram showing a GTO according to another embodiment of the present invention.

第3図では簡略化して描いているが、実際は直径約90
mmの円形半導体基体1に1700本程度OR型カソー
ドエミツタ層2が8重リングに配列され、2リングごと
にリングゲート10を設け、さらに上記円形半導体基体
の中心から矢印の方向へ4本の放射ゲート11を設けた
ものである。本実施例では各矢印の方向においてn型カ
ソードエミツタ層が一直線上に配列されている。こ−れ
により、自動装置によりトリミングする場合、上記−直
線上に配列されたn型カソードエミッタをトリミング開
始点に選べばn型カソードエミッタの各リングにおける
開始点の位置が角度方向では一致するので、プログラミ
ングが容易になる。
Although it is simplified in Figure 3, the actual diameter is approximately 90 mm.
Approximately 1,700 OR type cathode emitter layers 2 are arranged in an 8-layer ring on a circular semiconductor substrate 1 with a diameter of 1,700 mm, a ring gate 10 is provided for every two rings, and four gates are arranged in the direction of the arrow from the center of the circular semiconductor substrate. A radiation gate 11 is provided. In this embodiment, the n-type cathode emitter layers are arranged in a straight line in the direction of each arrow. As a result, when trimming with an automatic device, if the n-type cathode emitters arranged on the above-mentioned straight line are selected as the trimming starting point, the positions of the starting points in each ring of n-type cathode emitters will match in the angular direction. , programming becomes easier.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明によればGTOの素子面内
におけるゲート電極抵抗を均一化できるので、遮断耐量
を向上する効果がある。
As described in detail above, according to the present invention, the gate electrode resistance within the device plane of the GTO can be made uniform, so that there is an effect of improving the cut-off withstand capability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のGTOのカソード側平面図
、第2図は本発明の動作説明図、第3図は本発明の他の
実施例のGTOのカソード側平面を示す模式図である。 1・・・円形半導体基体、2・・・n型カソードエミツ
タ層、10・・・リングゲート、11・・・放射ゲート
、茅 1 固 Aギ22 茅3 固
FIG. 1 is a cathode side plan view of a GTO according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the present invention, and FIG. 3 is a schematic diagram showing a cathode side plane of a GTO according to another embodiment of the present invention. It is. DESCRIPTION OF SYMBOLS 1...Circular semiconductor substrate, 2...N-type cathode emitter layer, 10...Ring gate, 11...Radiation gate, grass 1 solid Agi 22 grass 3 hard

Claims (1)

【特許請求の範囲】 1、1対の主表面を有し、隣接相互間でpn接合を形成
する少なくともpnpn4層を有する半導体基体を備え
、第1層は複数の短冊状領域に分割され、上記短冊状領
域は放射状かつ多重リング状に配列され、第2層と上記
短冊状領域は上記半導体基体の一方の主表面に露出し、
上記短冊状領域にカソード電極が、上記第2層にゲート
電極が、上記半導体基体の他方の主表面にアノード電極
が設けられているゲートターンオフサイリスタにおいて
、上記ゲート電極に複数個のリング状のゲート集電電極
板が上記短冊状領域の多重リングの各々に隣接するよう
に設けられ、かつ上記ゲート電極が、複数の上記ゲート
集電電極板を互いに連結する半導体基体の中央部から周
辺部へ向つて放射状に伸びた複数の領域を有することを
特徴とするゲートターンオフサイリスタ。 2、特許請求の範囲第1項において、短冊状領域の多重
リングに複数個の短冊状領域が半導体基体の中央部から
周辺部に向つて一直線上に配列された領域を有し、この
領域が上記リング状のゲート集電電極板を連結するゲー
ト電極の領域と隣接していることを特徴とするゲートタ
ーンオフサイリスタ。
[Claims] 1. A semiconductor substrate having a pair of main surfaces and at least four pnpn layers forming a pn junction between adjacent ones, the first layer being divided into a plurality of strip-shaped regions, the strip-shaped regions are arranged radially and in multiple rings, the second layer and the strip-shaped regions are exposed on one main surface of the semiconductor substrate;
In the gate turn-off thyristor, a cathode electrode is provided on the strip-shaped region, a gate electrode is provided on the second layer, and an anode electrode is provided on the other main surface of the semiconductor substrate, wherein a plurality of ring-shaped gates are provided on the gate electrode. A current collector electrode plate is provided adjacent to each of the multiple rings of the strip-shaped region, and the gate electrode extends from the center to the peripheral part of the semiconductor substrate connecting the plurality of gate current collector electrode plates to each other. A gate turn-off thyristor characterized by having a plurality of radially extending regions. 2. In claim 1, the multiple ring of strip-shaped regions has a region in which a plurality of strip-shaped regions are arranged in a straight line from the center to the periphery of the semiconductor substrate, and this region is A gate turn-off thyristor, characterized in that the gate turn-off thyristor is adjacent to a region of a gate electrode that connects the ring-shaped gate current collector electrode plate.
JP6889187A 1987-03-25 1987-03-25 Gate turn-off thyristor Pending JPS63236360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6889187A JPS63236360A (en) 1987-03-25 1987-03-25 Gate turn-off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6889187A JPS63236360A (en) 1987-03-25 1987-03-25 Gate turn-off thyristor

Publications (1)

Publication Number Publication Date
JPS63236360A true JPS63236360A (en) 1988-10-03

Family

ID=13386728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6889187A Pending JPS63236360A (en) 1987-03-25 1987-03-25 Gate turn-off thyristor

Country Status (1)

Country Link
JP (1) JPS63236360A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03109772A (en) * 1989-09-22 1991-05-09 Fuji Electric Co Ltd Gate turnoff thyristor
EP1030355A1 (en) * 1998-09-10 2000-08-23 Mitsubishi Denki Kabushiki Kaisha Press contact semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03109772A (en) * 1989-09-22 1991-05-09 Fuji Electric Co Ltd Gate turnoff thyristor
EP1030355A1 (en) * 1998-09-10 2000-08-23 Mitsubishi Denki Kabushiki Kaisha Press contact semiconductor device
EP1030355A4 (en) * 1998-09-10 2006-02-01 Mitsubishi Electric Corp Press contact semiconductor device

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