JPS6323582B2 - - Google Patents

Info

Publication number
JPS6323582B2
JPS6323582B2 JP58185547A JP18554783A JPS6323582B2 JP S6323582 B2 JPS6323582 B2 JP S6323582B2 JP 58185547 A JP58185547 A JP 58185547A JP 18554783 A JP18554783 A JP 18554783A JP S6323582 B2 JPS6323582 B2 JP S6323582B2
Authority
JP
Japan
Prior art keywords
data
input
signal
ram
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58185547A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6077237A (ja
Inventor
Kiichi Matsuda
Toshihiro Pponma
Makoto Hiraoka
Yoshiji Nishizawa
Toshitaka Tsuda
Hideo Kuroda
Naoki Takegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NTT Inc
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP58185547A priority Critical patent/JPS6077237A/ja
Publication of JPS6077237A publication Critical patent/JPS6077237A/ja
Publication of JPS6323582B2 publication Critical patent/JPS6323582B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Controls And Circuits For Display Device (AREA)
JP58185547A 1983-10-04 1983-10-04 バツフア・メモリ制御回路 Granted JPS6077237A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58185547A JPS6077237A (ja) 1983-10-04 1983-10-04 バツフア・メモリ制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58185547A JPS6077237A (ja) 1983-10-04 1983-10-04 バツフア・メモリ制御回路

Publications (2)

Publication Number Publication Date
JPS6077237A JPS6077237A (ja) 1985-05-01
JPS6323582B2 true JPS6323582B2 (enExample) 1988-05-17

Family

ID=16172712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58185547A Granted JPS6077237A (ja) 1983-10-04 1983-10-04 バツフア・メモリ制御回路

Country Status (1)

Country Link
JP (1) JPS6077237A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01180625A (ja) * 1988-01-12 1989-07-18 Fujitsu Ltd 速度変換回路

Also Published As

Publication number Publication date
JPS6077237A (ja) 1985-05-01

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