JPS63234878A - Controller for pulse width modulation inverter - Google Patents

Abstract

PURPOSE:To suppress the distortion of an output voltage waveform, by arranging a means for detecting the arm voltage of each phase of a main circuit, and a means for subtracting the output of the detecting means, from voltage reference signal turned into the modulated wave of pulse width modulation. CONSTITUTION:So far as the controller of a PWM inverter is concerned, the input of phase U arm voltage on the negative side to a photocoupler 100 via a resistor 90 is provided, and the voltage is taken out of a resistor 11. The input of the arm voltage to a photocoupler 101 and to a photocoupler 102 is provided, and the voltage is taken out of a resistor 13. The arm voltage of each phase taken out in this manner is converted to phase U, phase V, and phase W fundamental-wave component Eu, Ev, Ew, by an arm voltage fundamental-wave component detecting circuit 14, and the input to the negative terminals of adding or subtracting units 150-152 is provided. In the meantime, to the positive terminals, the input of phase U, phase V, and phase W voltage reference signals Eu', Ev', Ew' from a voltage reference signal generating circuit 15 is provided. The output of the adding or subtracting units 150-152 is directed to compensators 160-162 to which the input is provided, and phase U, phase V, and phase W modulated-waves Vu, Vv, Vw for PWM control are generated.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an inverter that obtains sine wave alternating current power using a pulse width modulation method, and in particular to control of a pulse width modulation inverter suitable for driving an induction motor. Regarding equipment.

[Conventional technology]

For example, in an inverter for driving an induction motor, it is desirable that the output voltage waveform has as little distortion as possible.

On the other hand, in a pulse width modulation (hereinafter referred to as PWM) inverter, a predetermined margin time is required for alternate switching timing between the positive side arm and the negative side arm in order to prevent arm short circuits within the main circuit.

Setting of so-called dead time is unavoidable, which causes distortion in the output voltage waveform.

Therefore, in the conventional device, for example,
As described in Japanese Patent No. 76, distortion of the output voltage waveform is suppressed by superimposing a correction amount proportional to dead time on a voltage reference signal that is compared with a carrier wave during PWM control.

[Problem that the invention seeks to solve]

The waveform distortion of the output voltage in a PWM inverter is caused by the dead time Td and the PWM included in one cycle of the output voltage.
Product Td・(fc/ft) of number of pulses (fc/f+)
changes in proportion to. Note that fc is the carrier frequency of PWM, and f! is the inverter output frequency.

By the way, the switching characteristics of the switching elements used in the main circuit of the inverter change due to temperature changes and variations in the elements, and therefore the above-mentioned dead time Td also changes while the inverter is in use.

Furthermore, even if the carrier frequency f0 is constant, the inverter output frequency f! Since is variably controlled, the above-mentioned number of pulses (fc/f+) also changes.

Therefore, in the conventional technology described above, in order to suppress the output voltage distortion, the dead time Td and the number of pulses (f
There is a problem in that the above-mentioned correction amount needs to be readjusted every time the value (c/fs) changes.

The purpose of the present invention is to address the problems of the prior art mentioned above,
To provide a control device for a PWM inverter that can always obtain sufficient improvement in output voltage waveform distortion, regardless of the switching characteristics of power switching elements used in the main circuit or changes in the operating conditions of the inverter. be.

[Means for solving problems]

The above objective is achieved by detecting the arm voltages of each phase in the main circuit of the inverter and controlling the fundamental wave components of these voltages to follow a voltage reference signal that becomes a modulation wave when forming a PWM control signal. be done.

[Effect]

The arm voltage of the PWM inverter has a dead time Td
and carrier frequency f. An extra voltage proportional to the product of is included. This voltage (hereinafter referred to as error voltage) is obtained by subtracting the voltage reference signal from the arm voltage.

Therefore, if the modulated wave is controlled in such a way that the arm voltage follows the voltage reference signal, a PWM control signal is created so that the error voltage converges to zero, and the distortion of the output voltage waveform due to dead time Td is automatically eliminated. is suppressed.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A PWM inverter control device according to the present invention will be described in detail below with reference to illustrated embodiments.

FIG. 1 shows an embodiment of the present invention. In the figure, a DC power supply 1
The collectors of transistors 2, 4.6 and the cathodes of diodes 20, 4 (1, 60) are connected to the positive side of the DC power supply 1, respectively, and the emitters of transistors 3, 5.7 and the cathodes of diodes 30. 50.70 anodes are connected respectively.

The emitter of the transistor 2, the anode of the diode 20, the collector of the transistor 3, and the cathode of the diode 300 are each connected to a U-phase terminal of the induction motor 8.

The emitter of the transistor 4, the anode of the diode 40, the collector of the transistor 5, and the cathode of the diode 50 are connected to the V-phase terminal of the induction motor 8.

The emitter of transistor 6, the anode of diode 60, the collector of transistor 7, and the cathode of diode 70 are connected to a phaseable terminal of induction motor 80.

The U-phase arm voltage on the negative side (collector-emitter voltage of transistor 3) is connected to the 7-coupler 100 via a resistor 90.
is input to the anode side of the diode. The negative side U-phase arm voltage insulated by the photocapacitor 100 is taken out from the resistor 11 connected to the emitter of the transistor in the 7-point monitor 100.

The V-phase arm voltage on the negative side (collector-emitter voltage of transistor 5) is connected to the 7-auto coupler 101 via a resistor 91.
is input to the anode side of the diode. The negative side V-phase arm voltage insulated by the 7-digital coupler 101 is taken out from a resistor 12 connected to the emitter of the transistor in the 7-digital coupler 101.

The W-phase arm voltage on the negative side (collector-emitter voltage of transistor 7) is connected to the 7 output cap 2102 via a resistor 92.
is input to the anode side of the diode. 7 Otokapu 2
The negative side W-phase arm voltage isolated by 102 is taken out from a resistor 13 connected to the emitter of the transistor in the photocoupler 102.

Here, each of the U-phase, ■-phase, and W-phase arm voltages input to the 7-oto couplers 100, 101, and 102 are set to voltages based on the negative side of the DC power supply 1.
The cathodes of diodes 101 and 102 are both connected to the negative side of DC power supply 1.

The arm voltages of the negative side U phase, ■ phase, and W phase isolated by the photocouplers 100, 101, and 102 are detected by the arm voltage fundamental wave component detection circuit 14 as a voltage proportional to the fundamental wave voltage, that is, the U phase arm voltage. It is converted into a fundamental wave component Eu, a v-phase arm voltage fundamental wave component Ev, and a W-phase arm voltage fundamental wave component EV. These voltages are then applied to adders/subtractors 150, 151 . and is input to the negative terminal of 152.

On the other hand, the positive terminals of these adders/subtractors 150, 151, and 152 receive the U-phase voltage reference signal B, the y-phase voltage reference signal E, and the W-phase voltage reference signal output from the voltage reference signal generation circuit 5. E: is input.

The outputs of adders/subtractors 150, 151 and 152 are connected to compensators 160, 161 and 162, respectively, and compensators 16
The outputs of 0, 161 and 162 are respectively added and subtracted by the adder/subtractor 153.
, 154 and 155. From these compensators 160°161.162, PW
A U-phase modulated wave vu, a v-phase modulated wave vv, and a W-phase modulated wave VW for M control are generated.

The negative terminals of adders/subtracters 153, 154, and 155 are all connected to the output of carrier wave generator 17.

The carrier wave generator 17 generates a triangular wave for PWM control. Each output of adder/subtractor 153, 154, 155 is connected to an input terminal of comparator 170, 171, 172, respectively.

The output of comparator 170 is connected to the input terminals of non-lap/gate drive circuit 19 and inverting logic element 180.

Similarly, the output of comparator 171 is connected to the input terminals of non-lap/gate drive circuit 19 and inverting logic element 181.

Furthermore, the output of comparator 172 is connected to the non-wrapping/gate drive circuit 19 and the inverting logic element 1820 input terminal.

The comparator 170 outputs a gate signal UP for firing the transistor 2, and the inverting logic element 180 outputs a gate signal UN (gate signal U) for firing the transistor 3.
A signal Up) which is the inverted logic level of p is generated.

The comparator 171 generates a gate signal VP for firing the transistor 4, and the inverting logic element 181 generates a gate signal VW (a signal obtained by inverting the logic level of the gate signal Vp) for firing the transistor 5.

The comparator 172 generates a gate signal WP for firing the transistor 6, and the inverting logic element 182 generates a gate signal Ww (a signal obtained by inverting the logic level of the gate signal Wp) for firing the transistor 7. .

In the non-lap/gate drive circuit 19, the rise time of each signal is delayed by Td time (hereinafter Td is referred to as dead time) from the fall time so that the gate signal Up and the gate signal UN, which is its inverted signal, do not overlap. I have to. Other gate signals Vp and V)l and gate signal Wp
and WM% are delayed by the same Td time as the U-phase gate signals Up and UN.

The gate signal thus obtained is further amplified by the non-lap/gate drive circuit 19, and as a result, the gate signal U is output from the non-lap/gate drive circuit 19.

UQ, V; , VQ, WQ, WM are generated, and the Corellano signal is transmitted through transistors 2, 3, 4, 5, 6 .
7 gates.

Next, the operation of this embodiment will be explained.

First, a process in which voltage waveform distortion occurs due to dead time Td will be explained.

Figure 2 shows the modulating wave (sine wave), carrier wave (triangular wave), and current. By comparing the modulating wave and carrier wave, PWM
This shows that a signal V* is obtained.

A signal whose pulse width has been reduced by a time Td from the time when the PWM signal signal simultaneously rises becomes the signal applied to the gate of the positive side transistor in FIG. 3, and similarly, the PWM signal V is applied to the gate of the negative side transistor. Time Td from the falling point of the phrase
A gate signal of the negative side transistor obtained by reducing the width of the Dayu pulse is applied.

Here, it is assumed that the current flows with a phase ψ delay with respect to the phase voltage (same phase as the modulated wave).

In this state, the voltage v0 generated between the connection point A (Fig. 3) between the positive side transistor and the negative side transistor and the virtual neutral point 0 is equal to the ideal voltage (peak value ED/2) of the same waveform of the PWM signal signal. .En: inverter input voltage) to find out how much error occurs.

First, let's consider a situation where the polarity of the current is negative.

Time 1+ (FIG. 2) is the point in time when the gate signal of the negative side transistor is turned off. The current flows in the negative direction (the third
(Figure), the diode connected in parallel to the positive side transistor becomes conductive, and the current flows in the direction 4. Therefore, at time t1, the magnitude of the terminal voltage V0 between A and 0 changes from -ED/2 to ED/2. The state in which the magnitude of the voltage v0 is ED/2 continues from time t when the positive side transistor is turned off until time t when the negative side transistor is turned on after a time td. As a result, the voltage V0 increases from the ideal voltage V* by the square wave voltage of the pulse width tm ta (='rd) and the peak value ED in this section.

Next, let's examine the case where the current flows in the positive direction.

Consider the point in time when the gate signal of the positive transistor turns off at time t. The positive side transistor is on until just before time t, and current flows in the positive direction through the path 1 in FIG. A at this time.

The terminal voltage V between 0 and 0 is ED/2. and,
When turned off at time t, the diode connected to the negative transistor becomes conductive, and the current continues to flow in the positive direction through the 20 paths. In this case, the terminal voltage between A and 0 changes from En/2 to -ED/2 at the same time as the diode becomes conductive at time ts. Since the current always continues to flow in the positive direction, the current flows in inverse parallel to the negative transistor until time t, when the gate signal of the positive transistor turns on after a time Td has elapsed since the gate signal of the negative transistor turns off. The connected diode is conducting. For this reason, A
The terminal voltage V between O is −ED/2. As a result, the terminal voltage v0 changes between time t and time t (time T
d minutes) generated voltage (peak value - ED/2, pulse width T
d square wave voltage). This voltage decrease occurs every time the negative side transistor is turned off for the same reason.

Terminal voltage v0 and ideal voltage V* arising from the reasons stated above
As shown in Figure 2, the error voltage ∆V (=Vwoo■) with respect to When flowing, it becomes an alternating current signal that changes with negative polarity. and,
This error voltage ΔV is the carrier wave (
number of pulses fc/f+ (fc: carrier frequency,
f,: the product of the modulated wave frequency) and the dead time Td (f
c/fl)・Td. Therefore, dead time Td
It can be seen that as the value of fc/fl increases or the value of fc/fl increases, the voltage distortion increases. Also, f,
Since the value of /fl increases as the frequency of the modulated wave, that is, the inverter frequency, decreases even if the frequency f0 of the carrier wave is constant, it can also be seen that voltage distortion increases in the low speed range.

Next, the operation of the control device shown in FIG. 1 will be explained using the time chart shown in FIG. 4.

The collector-emitter voltage (arm voltage) of each of the three-phase negative side transistors 3 and 5.7 is 7 and the auto coupler 10.
0, 101, and 102, and is input to the arm voltage fundamental wave component detection circuit 14. As a result, the arm voltage fundamental wave component detection circuit 14 outputs the fundamental wave voltage Eu(V
phase and W phase are omitted) are obtained. When the polarity of the current il shown by the broken line is positive, this voltage decreases by an amount proportional to (fc/f, )・Td, and conversely, when the polarity of the current iu is negative, based on the principle of voltage distortion generation described above. When (f
.

/f, )·Td increases by an amount proportional to Td.

On the other hand, the fundamental wave voltage Eu is subtracted from the voltage reference signal Eu generated from the voltage reference signal generation circuit 15 by a subtracter 150,
As a result, an error voltage ΔV shown in FIG. 4 is obtained. This error voltage ΔV is then input to the compensator 160.

The compensator 160 is a first-order slow n element or PI (proportional + integral)
It operates so that the fundamental wave component Eu of the arm voltage matches the voltage reference signal Eu.

For example, when an error voltage ΔV as shown in FIG. 4 is generated, a modulated wave V as shown in FIG. 4 is generated.

Compared to the voltage reference signal E, the modulated wave V* is corrected to a smaller value by the error voltage ΔV when the polarity of the current is negative, and to a larger value by the error voltage ΔV72 when the polarity is positive. Therefore, the modulated wave
8 and carrier wave! PWM obtained as a result of comparison with (triangular wave)
The pulse width of the signal Up becomes narrow in a region where the current polarity is negative, and conversely becomes wide in a region where the current polarity is positive.

Therefore, according to this embodiment, as described above, PWM
Since the signal is automatically corrected, the increase in voltage in the region where the polarity of the current is negative and the decrease in the voltage in the region where the polarity of the current is positive are suppressed. It is possible to suppress voltage distortion that is likely to occur due to time Td.

〔Effect of the invention〕

According to the present invention, the PWM control signal is automatically configured so that the waveform of the inverter output voltage always matches the waveform of the voltage reference signal even if the carrier wave frequency or the inverter output frequency is changed or the dead time changes. Since the distortion of the output voltage waveform is sufficiently suppressed, there is no risk of distortion increasing even in the low output frequency range, and the torque characteristics are good at low speeds and when starting up for induction motor drives. can be kept.

Furthermore, since there is no need to adjust the correction amount even if the carrier frequency or dead time changes, operability is improved.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram showing the principle of voltage distortion generation, and Fig. 3 is a diagram showing the current flowing through the transistors and diodes forming the positive and negative arms. FIG. 4 is a time chart illustrating the operation of the control circuit shown in FIG. 1. 1...DC power supply, 2, 3, 4, 5, 6.7...
...transistor, 20.30.40.50.60
...Diode, 8...Induction motor,
14...Arm voltage fundamental wave component detection circuit, 15
...Voltage reference signal generation circuit, 160, 161,
162...Compensator, 19...Non-lap/gate drive circuit, 170, 171°172...
・Comparator, 100, 101, 102...Photo coupler. Figure 1 8 Inductive electric f/74 170-172
y:, Comparison 3 Figure 2 Figure 3 Figure 4 wJ p

Claims (1)

[Claims] 1. In a pulse width modulation inverter that uses dead time to control the switching control timing of the positive and negative arms of the switching circuit that constitutes the main circuit of the inverter, arm voltage detection detects the voltage appearing on the negative arm. and an arithmetic means for subtracting the output of the arm voltage detection means from the voltage reference signal to be the modulated wave of the pulse width modulation, and the fundamental wave component of the voltage appearing on the negative side arm is added to the voltage reference signal. 1. A control device for a pulse width modulation inverter, characterized in that the control device is configured to obtain control in a direction in which the values coincide with each other.