JPS6323422A - Gray code counter - Google Patents

Abstract

PURPOSE:To suppress the scale of hardware by using four kinds of functions depending whether two kinds of input pulses are respectively logical '1' or '0' so as to generate a carry output thereby attaining the cascade connection. CONSTITUTION:A carry output of a low-order 4-bit counter 33 is inputted to a count pulse input of a high-order 4-bit counter 32 at count operation and a carry output of a low-order 4-bit counter 33 outputs logical '1' when the counter is count operation and a counter output is 15 In decimal notation. In this case only, the high-order 4-bit counter 32 applies count and in other cases, the output of the high-order 4-bit counter 32 is held. In case of the presence of high-order connection to the counter in this way, the count operation by cascade connection is attained by connecting its carry output to the count pulse input of the high-order counter. Further, in case of the cascade connection, an OR circuit 34 aud an AND 35 are connected so as not to lose the preset function, hold function and clear function.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a Gray code counter in a digital control circuit.

2. Description of the Related Art Conventional gray code colors include, for example,
0-32401.

FIG. 8 shows a configuration diagram of this conventional Gray code counter, in which 36 and 37 are cascade-connected D-flip 70-tub circuits, 38 is a Nandt gate for feedback, and 39 is a Nandt gate for control. When a logic 1111+ control signal CT arrives at the Nant gate 39, 2-bit Gray code signals Z1 and Z2 are generated every time a clock pulse OP as a drive signal is input to the trigger terminals of the D flip-flop circuits 36 and 37. Send.

Problems to be Solved by the Invention However, in the above configuration, CT is LL 1
! Since the only function is to perform a counting operation when CT is 1 and not to perform a counting operation when CT is ``○'', it has a problem that it is difficult to use for digital control compared to conventional binary code counters.

Although the Gray code has the advantage that the distance between codes with a value difference of 1 is 1, it has the disadvantage that the structure of the hardware is more complicated than the binary code.

In view of this, the present invention has all the functions of a conventional binary code counter, including a preset function, a hold function, a clear function, and a count function, and also allows vertical string connection of multiple counters. Moreover, it is an object of the present invention to provide a Gray code counter whose hardware size is not so large compared to a conventional binary code counter.

Means for Solving the Problems The present invention provides means for determining which operation to perform among a preset operation, a hold operation, a clear operation, and a counter operation, and means for generating a signal representing whether the counter output is even or odd. 2. A Gray code counter having means for generating a carry output.

Operation The present invention uses four types of functions depending on whether the two types of input pulses are "1" or 0, respectively, and generates a carry output to enable cascade connection, and even or odd counter outputs. By generating a signal representing , the inversion conditions for each pino are simplified, and the size of the doware is suppressed.

Embodiment FIG. 1 shows the configuration of a Gray code counter in a first embodiment of the present invention. In Figure 1, 1
is the most significant bit input terminal, 2 is the second most significant bit input terminal, 3 is the second least significant bit input terminal, 4 is the least significant bit input terminal, 6 is the most significant bit output terminal, 6 is the second most significant bit Output terminals, 7 is the lower second bit output terminal, 8 is the least significant bit output terminal, 9 is the carry output terminal, 10 is the preset pulse input terminal, 11 is the count pulse input terminal, 12 is the clock pulse input terminal, 13 is an inverting circuit,
14. 15. 16. 17. 18,19゜20.
21 is an AND circuit, 22.23 is an exclusive OR circuit, 2
4 is an OR circuit, and 26.26 is a D flip-flop.

The operation of the Gray code counter of this embodiment configured as described above will be explained below.

The gray code counter of this embodiment has a preset function, a hold function, and a count function by the combination of "1", 5", and 0" of the preset pulse input from the terminal 10 and the count pulse input from the terminal 11. It performs four functions: and a clear function. Fig. 2 shows the function performed by the Gray code counter of this embodiment in each combination of "1" and '0' of the precent pulse and the count pulse. When the pulse is “0”, the 14 AND circuits are “1”
Since the AND circuits 15 and 16 output "○", the AND circuit 17 outputs the most significant bit data input from terminal 1, and the AND circuits 18 and 19 output 1.
Outputs 70 It. Therefore, the data of the most significant bit input from terminal 1 passes through the OR circuit 24 to D
It is input to the flip 70 knob 25. As for the upper 2nd bit, the lower 2nd bit, and the least significant bit, in the same way as for the most significant bit, the data of each bit input from the terminals 2, 3.
It is input to 0 knob. On the other hand, the exclusive OR circuit 23 is
1+ 2+ When the number of "1'" included in the 4-bit data input from terminals 3 and 4 is O or 2, "o" is output, and if the number of "1" 2 in the input data is When it is 1 or 3, it outputs "1" 2. Therefore, D flip 7
Data representing whether the number of "1"s in the input data is even or odd is input to the 0-tube 26.

At this time, when the clock pulse rises, each D flip-flop changes to 1. 2. 3. The input data from the terminal No. 4 and data representing whether the number of "1"s in the input data is even or odd are output.

Figure 3 shows 1. 2. 3. 4 is a time chart showing the operation of the Gray code counter of this embodiment when the data input to the terminal No. 4 is f+ 11o o 17. In FIG. 3, a is a clock pulse input from terminal 12, b is a preset pulse manually input from terminal 10, C is a count pulse input from terminal 11, and d
, θ, f', g are data output from the terminals 5, 6 degrees 7.8, h is the output of the D flip-flop 2e, and 1 is the carry output output from the terminal 9. Hereinafter, the most significant bit output will be referred to as 05, the second most significant bit output as G2, the second least significant bit output as 01, the least significant bit output as Go, and the output of the D flip-flop 26 as G. In Fig. 3, the preset pulse is 1", the current pulse is "0", and at the instant j when the clock pulse rises, the input value "'1100" is input to the Gray code counter.
is input.

Next, the hold function will be explained. When both the pre-cent pulse and the count pulse are "0", the AND circuit of 15 outputs 11, 11, and the counters of 14 and 16 output "
o", the AND circuit 18 outputs G3, and the AND circuits 17 and 19 output "0". Therefore, through the OR circuit 24, the D flip 70 tube 25 receives G3. is input, and at the rising edge of the next clock pulse, G5 does not change.G 21 G + l
GQ+G-1 also remains unchanged, and the output of the counter is held.

That is, in FIG. 3, the output of the counter remains "110o" from C to k.

Next, the clear function will be explained. When both the preset pulse and count pulse are “1”, 14, 15, and 16
Since all AND circuits output “O”, 17 and 18
and 19 AND circuits all output ``O''''. Therefore, the entire OR circuit 24 passes through the D flip-flop 25.
“○” is input to G3, and at the rising edge of the next clock pulse, G3 becomes “o”.G2.G4.G
The same goes for ot G+, and the counter output is cleared. That is, in FIG. 3, the counter output becomes "'○○oO" at the moment g.

Next, the count function will be explained. FIG. 4 shows the Gray code corresponding to decimal numbers 0 to 32 and the corresponding lower 4-bit counter G-1. In Figure 5,
The conditions for inverting each bit when counting using Gray code are shown. In addition to the Gray code, the Gray code counter of this embodiment internally generates G, which indicates whether the counter output is even or odd. It can be seen from FIG. 4 that when G is used, when counting the Gray code, Go can be inverted when G is "○". For example, when the counter output is 0 in decimal notation, G is "0", so Go is inverted at the rising edge of the next clock pulse,
The counter output becomes 1 in decimal notation. Furthermore, when the counter output is 1 in 10-base representation, G is "1", so Go is not inverted at the rising edge of the next clock pulse. Regarding G1, it is inverted at the rising edge of the next clock pulse only when Go=1 and G1=1,
When this reversal condition is not satisfied, G1 is held.

G2 is inverted on the rising edge of the next clock pulse only when G1=1 and GQ=O and G-1=1. G3 is G2=1 and G1=0 and GQ =Q and Q
Only when 1==1 does it invert on the rising edge of the next clock pulse. FIG. 1 embodies the counting algorithm shown in FIG. 5.

The present pulse input from terminal 10 is 1"OI'
So, when the count pulse input from terminal 11 is "1", the AND circuit of 14 and 15 outputs "0", so
The AND circuit of 17 and 18 outputs "0". Therefore,
Through the OR circuit 24 to the D flip 70 tube 25,
Output data of the AND circuit 19 is input. On the other hand, since the AND circuit 21 outputs 1 only when G2゜G,, G,), G, = 1, the exclusive OR circuit 22 outputs 1 when G2, G1, Go-G, -. Output G3.

Therefore, Df'J knob flop 25 has G2. G1
．． When Go, G, = 1, the inverted data of G3 is input, and when G2"GI'GO"-j = O, G3 is input, and at the rising edge of the next clock pulse, the counting algorithm of Fig. 5 is executed. The counting operation is performed based on the following. G2°G, . . . Go also performs counting operations based on the counting algorithm shown in FIG.

FIG. 6 shows the configuration of the Gray code counter in the second embodiment 1 of the present invention. In FIG. 6, numerals 1 to 26 have the same contents as in FIG. 40 is an upper even-odd data input terminal, and if the number of "1"s in the data input to the counter connected to the upper order is an even number, "○" is input.
“ゝ” is input, and if it is an odd number, “°1” is input.

41 is a counter input even-odd data output terminal;
2. 3. If the number of 0111s in the data input from 4 is an even number, "0"2 is output, and if it is odd, "1" is output. 42 is an exclusive OR circuit. When the Gray code counter of this embodiment is used in one stage, "o" is input from the terminal 40, and in the same way as the Gray code counter of the first embodiment, preset operation, hold operation, clear operation, and counting are performed. take action.

Next, cascade connections will be explained. FIG. 7 shows a connection diagram when two Gray code counters of this embodiment are connected in series to form an 8-bit Gray code counter. In FIG. 7, 27 is a preset value input terminal, 28 is a gray code counter output terminal, 29 is a clock pulse input terminal, 3° is a count pulse input terminal, 31 is a preset pulse input terminal, 32 is an upper 4 pint counter, 3
3 is a lower 4-bit counter, 34 is an OR circuit, and 35 is an AND circuit. Below is the GO of the upper 4 bit counter.
, Gl/G2/G5 to 04/Cr5. G6. It's called G7.

During counting operation (when the preset pulse is 11011 and the count pulse is "1"), the carry output of the lower 4-bit counter is input to the count pulse input of the upper 4-bit counter. The carry output of the lower 4-bit counter occurs when the counter is in counting operation and the counter output is 15 in decimal notation (when the count pulse is "1'' and ε2゜01・GO・G,=1) ``1''
Output.

Only at this time, the upper 4-bit counter performs counting operation,
At other times, the output of the upper 4-bit counter is held. In this way, when a counter has an upper-level connection, by connecting its carry output to the count pulse input of the upper-level counter, a cascade-connected counting operation becomes possible.

That is, in FIG. 3, the lower counter performs a counting operation after β, and the carry output of the lower counter becomes ``1'' between m and n, and that signal is input to the count pulse input of the upper counter. From K, at that time, the upper counter also performs a counting operation. If the counter is not connected to an upper level, the carry output of the counter may be input to the preset pulse input as shown in FIG. With this, when the counter output is 15 in decimal notation and the count pulse input is ``1'', the preset pulse input is 1.
111+, and the counter output is cleared at the rising edge of the next clock pulse. If this connection is not made, the counter output will be “13, 14° 15.15, 14
, 13.12...''.

Preset function even when cascading connections.

An OR circuit 34 and an AND circuit 36 are connected so as not to impair the hold function and clear function. As a result, when the preset pulse is "1+1" and the count pulse is "○", both the upper and lower counters are preset, and when the preset pulse is "1" and the count pulse is N'1", both the upper and lower counters are preset. cleared.

The preset pulse is 1 “Q” and the count pulse is also “o”
”, both the upper and lower counters are held. In Fig. 7, cascade connection is possible by connecting an OR circuit or an AND circuit outside the counter, but these circuits cannot be connected to the counter. If provided at the output, the counters can perform preset, hold, clear, and count functions without the need for external circuit connections and by simply connecting multiple counters, even when connected in cascade.

As described in detail, according to the present invention, it is possible to construct a Gray code counter that does not impair the functionality of a binary code counter at all, using hardware of the same scale as a binary code counter. If such a Gray code counter is made into an IC and replaced with a conventional binary code counter,
Its practical effects are great.

The Gray code counter of the present invention is useful as an address counter for a memory that stores data that has a very large correlation between data at adjacent addresses, such as an image information storage device.

With conventional binary code counters, when the transfer rate from memory is increased, the address may be incorrect by about 1 bit due to the slight delay time difference between each bit from the address counter output to the memory address input. When accessed, there is a problem in that data at an address completely different from the designer's intention is output.

When the Gray code counter of the present invention is used as an address counter, even if the address input to the memory is incorrect by about 1 bit, data at an address close to the true address will be accessed. If information is stored that does not have a large difference between the data at the address, the data that does not have a large difference from the true data will be output from the memory.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a Gray code counter according to a first embodiment of the present invention, FIG. 2 is a functional explanatory diagram of the Gray code counter, FIG. 3 is a time chart showing the operation of the same embodiment, and FIG. FIG. 5 is an explanatory diagram of the counting function, FIG. 6 is a configuration diagram of the Gray code counter of the second embodiment of the present invention, and FIG. 7 is a connection diagram when the Gray code counters of the same embodiment are connected in cascade. FIG. 8 is a block diagram of a conventional Gray code counter. 1.2, 3.4... Preset value input terminal, 5
゜6, 7. 8...Counter output terminal, 9.
...Carry output terminal, 1Q...Preset pulse input terminal, 11...Count pulse input terminal, 12...Clock pulse input terminal, 2
1...AND circuit, 26...D flip-flop, 40...Upper even-odd data input terminal, 41...Counter input even-odd data output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Fig. Sasa ε99 Danrara 9/mi Fig. 4 Fig. 5 Fig. 7 Fig. 8 l

Claims (1)

[Claims] A means for selecting a preset operation, a hold operation, a clear operation, and a counting operation, a means for generating a signal representing an even/odd number of counter output data, a means for determining an inversion condition for each bit during a counting operation, A Gray code counter comprising means for generating a carry output to enable cascade connection.