JPS63231537A - Fault processing system - Google Patents

Abstract

PURPOSE:To recover and process the inverting trouble of a RAM used as an RCS cheaply and at high speed by providing a means to store the same data as the data (micro-instruction sequence) RCS (reloadable control storage)-loaded and a restarting address which goes to a pair with the data. CONSTITUTION:Together with the recovering data of RAM, a restarting address RADRi is prepared beforehand corresponding to a trouble address and by a channel control device CHC 300, a restarting processing corresponding to the trouble address can be executed to a channel device 3101-n. Namely, the instructing information to instruct the effect to restart after the CHC 300 sets the value to an address register ADR 312 together with the value of the RADRi fetched earlier to a data line 530 in continuation to the recovering processing of an RCS 311, is published and informed by a signal line 5101.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system, and relates to a fault handling method suitable for recovering from a microinstruction read error in a microprogram-controlled processing device [Prior art] With the advent of high-performance microcombinators and low-cost, high-speed random access memory (RAM), microprogram control systems with reloadable control storage (RCS') have become popular in the control sections of various electronic devices. It has been adopted.

The advantage of microprogramming the control section of this type of processing device using RCS is that complex control can be easily realized with less development effort, but the problem is the reliability of the RAM used in RCS. It's in the sex. That is,
If a failure occurs in the RCS, it becomes impossible to execute the microprogram, and the contents of the RCS are not updated during normal operation, so even if the failure is caused by a temporary RAM pit inversion, it is an irrecoverable failure. This results in a loss of equipment availability. Conventional countermeasures for this include correcting error pits using Hamming codes, correcting error bits using horizontal and vertical parity pits, or reloading a group of data from external storage (such as a 70-bit disk). Disaster recovery methods have been adopted. Although the Hamming code method is effective against temporary failures as well as permanent RAM failures, the need to add redundant bits increases production costs. Furthermore, the method using horizontal and vertical parity pits or the method using paste loading from external storage has the disadvantage that it takes a long time to recover from a failure.

[Problem that the invention seeks to solve]

In order to solve the above drawbacks, the storage means is provided with a storage means for storing the same data as the RCS, and when an error in the read data (microinstruction) of the RCS is detected, the execution of the microinstruction is temporarily inhibited, and the storage means Japanese Unexamined Patent Publication No. 49-90466 discloses a method in which normal data is read out from the RCS, reloaded into the RCS, and the microprogram is re-executed using the normal data in place of the error data. However, the microinstruction cannot be executed unless the reading of the RCS is completed and the normality of the read data is confirmed by a check circuit, which increases the execution cycle of the microinstruction and degrades performance. In general, the so-called RAM read access time from when the address of RC3 is determined until the read data is obtained, and the time from when the read data is determined until the next address to be executed is set is the microinstruction time. Performance can be maximized by setting the execution cycle to . However, although performance can be maximized with this method, after the RCS read data is determined, the read data is immediately used to set the address of the next microinstruction, and the microinstruction is The operation specified by the instruction is also executed, and the read data is checked in parallel, so even if an error in the read data is detected, the read data has already been executed as a microinstruction. . Therefore, it becomes impossible to suppress and modify the execution of each microinstruction, to recover from a RAM failure by rewriting to the RCS, and to re-execute the microinstruction subsequent to the failure recovery process.

Furthermore, if an RCS read error is detected in one of the microprogram-controlled subprocessing units, the main processing unit acquires normal data from another subprocessing unit and R that detected an error in the data
Means are known for restoring the contents of the RCS by reloading it into the CS. However, no consideration was given to a method for re-executing the operation sequence that was being executed before the error was detected by the sub-processing device that detected the RCS read error.

An object of the present invention is to provide a low-friction and high-speed recovery processing method for a reversal failure of a RAM used as an RCS.

SUMMARY OF THE INVENTION An object of the present invention is to provide an effective microinstruction re-execution system in a processing device in which an erroneous microinstruction is already being executed when an error in RCS read data is detected.

[Means for solving problems]

The above object is achieved by providing a storage means for storing the same data (microinstruction sequence) loaded into the RCS and a restart address paired with the data.

〔Example〕

An embodiment of the present invention will be described below. As an example,
An example applied to a channel device, which is one of the components of a data processing system, will be used.

FIG. 1 shows the overall configuration of the data processing system.

100 is a central processing unit (CPU), 200 is a main storage control unit (SCU), '210 is a main storage unit (MSU), 3
00 is a channel control device (CHC), 51° is a channel device (CH), of which there are a plurality of devices (n devices), and 400 is a read device device (SVP).

FIG. 2 shows a channel control device 500. and channel device 3
10-311 Loadable Control Storage (RCS), 3
12 is an address register (AD
H) and 313 is the month 2 delay register (DA
DR), and if an error in the read data of 311 is detected, 512 is already updated to the address of the next microinstruction, but 313 retains the microinstruction address used when reading the data where the error was detected. be done.

5001-n are interrupt signal lines from 3101-n to 300, respectively, and 5101゛ is from 300 to 3101. , is a response signal to the interrupt signal 5001A,n. The bus line 520 is a data line from 6101-n to 300, and the bus line 550 is a data line from 300 to 5101ψ. FIG. 5 shows the format and format of information stored in the storage means.

In this embodiment, it is assumed that the storage means is provided in a part of the main storage unit MSU (210).

The service device 400 uses the RCS 311 of the channel device 5101M1 in the initial setting process associated with power-on, etc.
At the same time, load the microinstruction into the MSU 210, and also set information on the pair of RCS and RADR (restart address) as shown in Figure 4 from a predetermined address (offset address). do. Thereafter, each channel device 5101 . , T1 is RCS5
11 is read and executed one by one to advance the process, and when the predetermined process is completed, an interrupt signal is sent to CuC3O0. The CHC 500 scans the interrupt signal lines 5001 to 500n one by one, and when it receives an interrupt from the channel device 31010, for example, it returns a response signal to the channel device 3101 through the corresponding response signal 5101. This results in
Channel device 5101 sends device status information to data line 52.
CuC2O4 reports this information to the capture program.

When the channel device 3101 detects an error in the read data of the RCS 311, the channel device 3101 issues an interrupt signal to the CuC2O4 via the interrupt signal line 5001. When CuC2O4 receives the sedative signal, it responds via signal line 5101. Channel device 3101 receives signal +
! ! 5101, using data line 520 to
One channel that notifies the contents of DR515 as well as status information reflecting the detection of an error in the read data of RC3511.
C500 takes in the information on data line 520, analyzes the status information, and finds that an error has occurred in the read data of RCS311, so it adds the value of DADR to the offset address as shown in Figure 3. Send a request to the SCU 200 using the value as the main memory address. 5CU200 is RC from MSU210
Fetch S(i) and RADR(t), and
Transfer to 4. Since ADR 312 of channel device 3101 has already been updated to the next microinstruction address,
CM (,500 is the DAD received earlier on the data line 530
The value of R512 and instruction information instructing the ADH 512 to set this value are loaded and notified to the channel device 3101 via the signal line 5101. Channel device 610
1 receives the notification and resets the ADR 512. Subsequently, the CHC 5oo fetches the value of RCS(i) from the MSU 210 and loads the instruction information to load this value into the RCS 511, and notifies the channel device 5101 via the signal line 5101. The channel device receives the notification y and reloads the RCS(i) into the RCS 511.

Although the fault inherent in the RCS 311 is recovered by the above operation, the operation sequence of the channel device 3101 is damaged due to the error in the read data of the RCS 311, so the operation sequence is not executed in the channel device 5101 until the error is detected. The process must be re-executed, or if re-execution is not possible, a fault handling routine must be activated. Whether or not re-execution is possible depends on the microinstruction address that contained the fault data.

Therefore, in the present invention, as shown in FIG. 3, a 'restart address (RADR(i)) is prepared in advance in correspondence with the failed address along with the recovery data in the RAM.
CHC! too allows the channel device "01-n" to respond to a faulty address and perform start processing.

That is, CHC5 (10 is the previously fetched RA
Along with the value of DR(i), instruction information instructing to restart after setting this value to the ADR 312 is loaded and notified via the signal line 5101.

In the above explanation, an example was used in which a part of the main memory is used as a storage means for RCS(i) and RADR(i), but
The storage means may be provided inside CuC2O4,
Alternatively, an independent storage device may be installed. Alternatively, it may be built into the processing device itself.

As is clear from the above explanation, RCS in the processing device
Data failures can be recovered quickly and easily at the processing speed of the processing device, and recovery processing can be performed without impairing the microinstruction execution speed of the processing device, which has the advantage of providing an inexpensive and highly available processing system. . In particular, when applied to a channel device as in the embodiment, there are further advantages as follows: In general, an internal failure in a channel device causes an error in the program (usually the operating system), including an error in RCS read data. is notified, and fault recovery processing for the data processing system as a whole is executed by the program. However, if the present invention is used, an error in RCS read data can be retried within the channel device depending on the address of occurrence in step 2-. It is possible to reduce the number of failure recovery processes in a program and improve the average performance of the data processing system.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a data processing system according to an embodiment of the present invention, FIG. 2 is a connection diagram of a channel device and a channel control device to which the present invention is applied, and FIG. 500 Channel Control Unit (CHC). 5101A, n... Channel device (CH). 312...RCS address register. 5001, interrupt signal line from rl-CH to CHC. 5101-n...Response signal line from CHC to CH. 520...Data line from CH to CHC. 530・Data line from CHC to CH. No. 17, Figure 2] No.

Claims (1)

[Claims] 1. A processing device having an RCS (reloadable control storage), comprising a storage means for storing information in which the same data as the RCS and a restart address are paired; When an RCS read error is detected, data identical to the RCS and a restart address are read from the storage means based on the RCS address at that time, and after reloading the data RCS, a restart address is written to the RCS address register. A failure handling method characterized by setting an address and restarting.