JPS63231395A - Double speed line forward scanning circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Minute Hand] The present invention relates to a liquid crystal color image display device, and in particular, to drive two rows of pixels on a liquid crystal panel during one normal horizontal scanning period. The present invention relates to a double-speed line sequential scanning circuit that performs line sequential scanning (the m sequential scanning will be explained in detail later).

[Conventional technology]

In general, color television image display devices with a screen size of about 6 inches or more require particularly high resolution.
When inputting all NTSC image signals, it is necessary to display 4aO effective horizontal scanning lines. Therefore, in the case of an active matrix type television image display device, approximately 480 pixels are required in the vertical direction. . Also, N.T.
Since the SC system image signal is an interlaced signal with a frame period of 30 tlz, in the above active matrix type television image display device, one horizontal scanning period (hereinafter referred to as 1
It is also called a horizontal scanning period. ), each pixel is selected once per frame and driven with an image signal corresponding to that pixel.

Here, in this display device, if a liquid crystal element is used as a display element, it is necessary to perform AC driving in terms of its lifespan (liquid crystal elements have a shortened lifespan if they are not driven with AC). ), the polarity of the image signal is reversed for each frame, but at this time, the AC frequency of the liquid crystal element is 1/2 of the frame frequency.
5 Hz (that is, the first frame has positive polarity, the first frame has negative polarity, and two frames constitute one period). However, if the liquid crystal element is
If the liquid crystal element is driven with an AC voltage, flicker often occurs due to its low frequency, so it is necessary to ensure that the AC frequency of the liquid crystal element is at least 30 Hz'.

Therefore, in order to set the AC frequency to f 30 Hz,
Instead of selecting each pixel once in one frame, each pixel is selected twice, once in l field (one frame consists of two fields), and the polarity of the image signal is reversed for each field. All you have to do is drive it. However, the number of effective scanning lines in one field is approximately 240.
Therefore, when driving a liquid crystal panel having approximately 480 pixels in the vertical direction, pixels for two rows must be selectively driven during one horizontal scanning period.

In this way, pixels for two rows are selectively driven during one horizontal scanning period, all pixels of the liquid crystal panel are selectively driven once per field, and the AC frequency of the liquid crystal element is set to 30 Hz. An example of a color image display device is given in IEICE technical report, Vol. 84, No. 159 (1981), pages 21 to 26.
Discussed on page.

By the way, in a liquid crystal color image display device, as a method of arranging color filters for colorization, a triangular arrangement with less directional dependence and high resolution is advantageous. Triangular arrangement means that pixels of the same color are arranged vertically on the screen, R, G,
In contrast to the stripe arrangement in which the pixels of the three primary colors of B are lined up in order, the pixel positions of the three primary colors are shifted horizontally by 1.5 pixels for each row, and the three pixels in contact with Construct a triangle using primary colors. An example of a liquid crystal color image display device using such a triangular arrangement is, for example, Japanese Patent Laid-Open No. 61-14
Examples include those described in Japanese Patent No. 1492.

[Problem that the invention seeks to solve]

Among the above-mentioned conventional techniques, in the former proposed example, l
In order to sequentially drive two rows of pixels ``ff:'' during a horizontal scanning period, an A/D converter, a digital memory as a field memory, a D/A converter, etc. are used. A non-interlaced signal was obtained by performing so-called double-speed conversion on the television signal, and the non-interlaced signal was manually input to a horizontal scanning circuit to drive a liquid crystal panel.

In this way, in this prior art, pixels for two rows are driven during one horizontal scanning period, but for this reason, compared to the case where all pixels for one row are driven during one horizontal scanning period, Therefore, it was necessary to increase the speed of the horizontal scanning circuit described above. However, as horizontal scanning circuits become faster,
There were problems in that the circuit configuration became more difficult and power consumption increased.

Further, in this conventional technology, as described above, an A/D converter,
Since a digital double speed conversion circuit consisting of a digital memo IJ, a D/A converter, etc. is used, there is also the problem that the circuit scale becomes large.

- 10,000, in the latter proposed example, the color filter triangular arrangement i
In order to realize i', data is written to the liquid crystal panel using a video signal delayed by 1/2 horizontal clock every other row, and data is written to the liquid crystal element one pixel at a time. It was a sequential scanning method. Therefore, although it is effective in reducing the frequency of the horizontal clock, it does not take into account high-definition displays with as many as 480 vertical pixels as mentioned above, and therefore No consideration was given to the line sequential scanning method or the row-by-row reversal driving method.

Here, the line sequential scanning method means that data to be written to a liquid crystal element is stored in a storage means for one line, and then that one line is stored in a storage means.
This is a method in which a line's worth of data is written all at once into each liquid crystal element corresponding to one line.

In addition, the row-by-row inversion driving method is a method used to prevent brightness differences between the upper and lower parts of the screen, and is a method in which the polarity of the image signal is reversed for each row. (a method in which a signal with inverted polarity is applied to the column signal electrodes for each row).

An object of the present invention is to
Also, to provide a double-speed line sequential scanning circuit that can drive all pixels for two rows during one horizontal scanning period without using a digital double-speed conversion circuit, and can realize high-definition display using a triangular arrangement of color filters and filters. It is in.

[Means for solving problems]

In order to achieve the above object, the present invention arranges a plurality of pixels each consisting of a switching element and a liquid crystal display element in a matrix, connects the pixels in the same column to the same column signal electrode, and then connects each pixel to the same column signal electrode. The pixels in the row are red, green, and blue.
Each column has a liquid crystal panel that is constructed by sequentially corresponding to the primary colors and rearranged so that adjacent pixels corresponding to the same color in at least adjacent rows are separated from each other by 1.5 pixels in the row direction. Supplying a desired drive signal to the signal electrode,
In a liquid crystal color image display device that displays an image on the liquid crystal panel by controlling on/off the switching element in each pixel, an image signal and a clock signal are input, and the image signal is converted to the clock signal. The sample and hold circuits are divided into groups and sampled at the input timing of a signal and then held, and the sample and hold circuit is divided into groups. a control means for sequentially outputting the clock signal to the group and controlling the sample and hold circuits in the same group to perform sampling operations simultaneously;
A delay means for adjusting the time by delaying the image signal to be input in advance is provided, and during one horizontal scanning period, the image signal corresponding to the shift in the row direction of each pixel of two adjacent rows is
The sample and hold circuits were sampled and held in correspondence with each pixel, and the sample and hold circuits were held together in sets of two (
I! The pixels corresponding to the IIgI signal are grouped into 21# elements connected to the same column signal electrode, and for each group, the outputs from the two sample and hold circuits in the group are switched and one is Connecting means are provided to connect to the corresponding column signal electrodes, and each connecting means switches the output from the sample and hold circuit at a predetermined timing during another horizontal scanning period, thereby providing a hold signal to the sample and hold circuit. The image signals corresponding to the pixels in two adjacent rows are supplied to each column signal electrode one row at a time as the drive signal.

[Effect]

In the present invention, Il! corresponding to each pixel of two rows during one horizontal scanning period! ! The i-image signal is sampled and held by the sample and hold circuit, and during another horizontal scanning period,
The held image signal is divided into two parts for each row by the connecting means and supplied as a drive signal to the corresponding column signal electrodes. The liquid crystal panel with the triangular filter arrangement is driven. At this time, by supplying an image signal whose polarity is exactly reversed between the first field and the second field, the AC frequency of the liquid crystal display element can be changed to the frame frequency (for example, when an NTSC television image signal is input, 30 Hz), it is possible to obtain an image with less image distortion without using a digital double speed conversion circuit, and to prolong the life of the liquid crystal display element. Further, the control means and delay means cause the sample and hold circuit to sample image signals at different timings simultaneously, and l! By taking in all signals at the same timing, it is possible to reduce the speed of the horizontal scanning circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a double-speed line sequential scanning circuit as an embodiment of the present invention. This double-speed 1 lil sequential scanning circuit is used in a triangular active matrix type liquid crystal color image display device.

In FIG. 1, 1 is a horizontal scanning shift register, 2 is an AND circuit, 3 is a level shifter, 4 is a delay circuit, 5 is a polarity inversion circuit, 6R, 6Q.

6B is an input terminal for inputting R, G, and B image signals, 7 is a buffer amplifier with output control, 8 is a shift register for vertical scanning, and 9 is a triangular three-primary color filter for each image. A color liquid crystal panel Wi consisting of
(h-1, 2, 3, . . .) are digital data selectors, Sij (i-A, B.

C, j-1, 2, 3,...ri are analog switches composed of MOS transistors, etc., and 8/Hij (r-
As B #”5J-1m 2 e a *...)
is the sample hold circuit, Dr J (J-1, 2+3
*...) are column signal electrodes, Oak (k = 1 e 2
T 3 v ””) is the row signal electrode.

First, an overview of the operation of this embodiment will be explained.

2 and 3 are explanatory diagrams for explaining the operation contents of the embodiment shown in FIG. 1, respectively.

In Figure 2, (a) is the first field, (B
) shows the case of the second field, and in each figure, the left side is a screen obtained by ink-lace scanning, and the right side is a screen of the color liquid crystal panel 9 of FIG. 1.

In this embodiment, as shown in FIG. 2(a), in the first field, first, the image signal (
By sampling the image signal (corresponding to the normal first scanning line) to be displayed on each pixel in the first and second rows of the color liquid crystal panel 9, the image signal (corresponding to the normal first scanning line) is obtained. By sampling the pixels (corresponding to the normal third scanning line), image signals to be displayed on each pixel in the third and fourth rows are obtained. On the other hand, in the second field,
As shown in FIG. 2(b), the image signal of the first horizontal scanning period (corresponding to the normal second scanning line) is sampled,
Obtain the image signal to be displayed on each pixel in the second and third rows, sample the image signal in the second horizontal scanning period (corresponding to the normal fourth scanning line), and display the image signal in the fourth and fifth rows. An image signal to be displayed on each pixel of the eye is obtained.

The above-mentioned sampling is performed in each sample-and-hold circuit S/H shown in FIG. /H is held.

Then, among the image signals held during the 1/2 horizontal scanning period of the front cow in the next 1 horizontal scanning period,
The image signals of two rows of pixels corresponding to the previous row are simultaneously
The image signals corresponding to the subsequent rows are written to each corresponding pixel, and during the latter 1/2 horizontal scanning period, the image signals corresponding to the subsequent rows are written at once.
written to each corresponding pixel. In this way, the above-mentioned line sequential scanning is realized by writing image signals one line at a time every 1/2 horizontal scanning period.

On the other hand, the above-mentioned sampling of the image signal will be explained in more detail using FIG. 3.

FIG. 3 is an explanatory diagram for explaining sampling timing in the sample hold circuit of FIG. 1.

In FIG. 3, (a) shows the pixel arrangement of the color liquid crystal panel 9, and (b) shows the input terminals 6R*6G.
* Pixel signals R and G input to bH.

(C) shows a sampling clock for sampling the image signal shown in (B), and (d) shows a sampling clock for sampling the image signal shown in (d).

In addition, in FIGS. 3(b) to 3(e), the horizontal axis indicates time, and the time reference is common to each.

Now, let us consider the case where the pixel gl signal corresponding to the position of each pixel in the first and second rows is sampled with respect to the pixel arrangement shown in FIG. 3(a).

Among the image signals R, G, and H inputted sequentially in time from the input terminals 6Rr 6G + 6B, the image signals corresponding to the position of each pixel (the position of the pixel in the row direction [) are temporally If you look at it, you will see that it is placed at the position shown in FIG. 3(b). Therefore, in order to sample these image signals, simply considered, a sampling clock as shown in Figure 3 (C) may be used. However, in Figure 3 (C
) has a high frequency, so
This results in an increase in the speed of the horizontal scanning circuit (corresponding to the horizontal scanning shift register 1 in FIG. 1).

Therefore, in this embodiment, a delay circuit 4 shown in FIG. 1 is used to delay the image signals ① and G, respectively. That is, in the delay circuit 4, as shown in FIG. 3(b), with the time T corresponding to the distance of one pixel in the image signal as a reference, 2T is applied to the image signal R, and 2T is applied to the If image signal G. On the other hand, by delaying T, both image signals R and G are made to coincide with the temporal timing of image signal B, as shown in FIG. 3(d). Then, by sampling using the sampling clock obtained in this way, an image signal corresponding to each pixel is obtained. That is,
As the sampling clock, as shown in FIG. 3(e), it is possible to use a pulse signal whose one cycle is a time corresponding to the distance of 1.5 pixels in the image signal (i.e., 1.5 T). .

In this way, in this embodiment, the sampling clock is
As shown in Figure (e), since the frequency can be made low, the speed of the horizontal scanning circuit does not increase.

Further, in this embodiment, in order to perform the above-mentioned row-by-row inversion drive, a polarity inversion circuit 5 shown in FIG. 1 is provided, and the polarity inversion circuit 5 shown in FIG. The signals ~, GN, and BN are generated, and the sample and hold circuit S/H performs sampling so that an image signal whose polarity is inverted for each row can be written to each pixel. In addition, in order to set the AC frequency of the liquid crystal element to 30 Hz, the polarity is reversed for each field in the same row.

The above is an outline of the operation in this embodiment.

Next, the operation of each circuit in FIG. 1 will be explained.

In FIG. 1, the horizontal scanning shift register 1 is synchronized with a horizontal synchronizing signal obtained from a television signal, and one period corresponds to a distance of 1 to 5 pixels in the image signal as described above. Clock pulse φH (Fig. 3 (
(Similar to the sampling pulse shown in e)) and a horizontal scanning start signal DH obtained by delaying the horizontal synchronizing signal are applied.

This horizontal scanning shift register 1 has the same configuration as a normal shift register, and when the horizontal scanning start signal DH is input, the output Q1. Output Q2 to output Qa +...
The signals are shifted to the right in this order and output one clock at a time.

Next, the output Qzn-11 of the horizontal scanning shift register 1
Q2n (n-1# 2 e a *-) are both data selectors w2n-1, w2n (n-1t 2 s 3
*...''), and is output with the order changed for each field by a signal Fi whose logic is inverted for each field.

For example, the first field is the output Qzn-1m from the data selector W2n-1 and the output Qzn-1m from the data selector W2n.
In the second field, the data selector W2n-1 outputs an output Q2ns, and the data selector W2n outputs an output Qzn-1.

The output of the data selector W2n-1 is directly input to the three level shifters 3, and the output of the other data selector W2n is a signal H1 whose logic level is inverted to each other and which is switched every horizontal scanning period. and with H2,
The signal is input to an AND circuit 2, and input to three level shifters 3 among the six level shifters 3, with the input destination alternately changed every l horizontal scanning period.

In each level shifter 3, the input signal is passed through a hold circuit S/Hij (i-A, B, C1j-1,
2, 3,...) to a voltage level that can be driven.

Next, each sample and hold circuit S/Hi j performs a sampling operation using the output from the level shifter 3. That is, among each sample and hold circuit, S/HAj (
J-1, 2+ 3 +...) [hereinafter abbreviated as S/H-A] once per horizontal scanning period, S/HBj and S/Hc
j (j-1, 2, 3,...) [hereinafter referred to as S/H-B
, 8/H-C] are the aforementioned image signals RP, RN, G, , G, once every two horizontal scanning periods.

BP and BN are each sampled, the voltage to be supplied to the column signal electrode Dr-j (j-xs2*a*...) in charge of driving each is held, and the impedance is converted as necessary and output. .

This held signal voltage is applied to the analog switch 51
j('-A, Bt C, J-1e'2t a p...
), and by the control signals H,, HB, Ho, 1
It is switched every half period of the horizontal scanning period and is input to the buffer amplifier 7 with output control, and its output is applied to the column signal electrode Dr-
j (j-x*2ta*...) is being driven.

Next, a clock pulse φ7 having a frequency twice the horizontal scanning frequency and a vertical scanning start signal Dv obtained by delaying the vertical synchronization signal from the television signal are applied to the vertical scanning shift register 8. . This vertical scanning shift register 8 also has the same configuration as a normal shift register, and when the vertical scanning start signal Dv is input, the row signal electrode OB 1 s is changed every time the clock pulse φ7 is input for one clock. QB 2 e Ga 3 *”
”, and outputs it to the row signal electrode Ga-k (k-1゜2.3...) in l clock increments. Figure 4 shows the color liquid crystal shown in Figure 1. 1 in the panel
FIG. 2 is a circuit diagram showing the configuration of a pixel.

In FIG. 4, 10 is a MOS transistor, and 11 is a liquid crystal cell.

A row signal electrode Ga-k (k
-1, 2, 3,...) as described above from the vertical scanning shift register 8, the gates are connected to the row signal electrodes Ga-k as shown in FIG. The MOS transistor 1o that has been connected is turned on, and the column signal electrode D
The signal voltage applied to rj is applied to the liquid crystal cell 11, and the pixel in row j, column of color liquid crystal panel 9 enters a display state.

In addition, if the leakage when the liquid crystal itself or MOS) transistor 10 is off cannot be ignored, the column signal electrode Dr of each pixel
A signal holding capacitor may be added to j.

Further, one electrode of all the liquid crystal cells 11 shown in FIG. 4 is connected in common, and approximately the midpoint potential of the signal voltage is applied to drive the liquid crystal with alternating current.

The operation of each circuit in FIG. 1 has been described above.

Now, the operation described above can be expressed as j(-3J-2
:J-1, 2, 3,...) column signal electrode Dr
j and j+1. j+2nd column signal electrode Dr-j+1
, Dr-j +2 will be discussed in more detail with reference to FIG.

FIG. 5 is a time chart showing the operation timings of the main circuits and the timings of the main signals in FIG. 1, respectively.

In FIG. 5, the sampling period of each sample-and-hold circuit is W'', and the analog switch Sij (i-person, B, C1j-1, 2, 3, . . . ) is selected and the sampled image signal is The output period during which the output control material is sent to the amplifier 7 and the column signal electrode Dr J is driven is indicated by the symbol R1''.The period following the sampling period ``W'' and the output period ``几'' The sampled image signal should be written in ().
Row number k of the row to which the pixel belongs (K-1t2, 3t...)
is entered. Also, in Qa-k in FIG.
During the “H” period, the row signal electrode Ga-k is selected (i.e.,
A signal is input from the vertical scanning shift register 8. ) represents the period in which the

In the first field, the output Q of the horizontal scanning shift register 1 is controlled by the signal Fi whose logic is inverted every field.
zn-1 is selected as the output of data selector w2n-1, and Qzn is selected as the output of W2n.

During the first horizontal scanning period, the output of the data selector W2n-1 is sent to the sample and hold circuit j3 via the level shifter 3.
The signal is input to s/H-A and sampling is performed. On the other hand, the output of the data selector W2n is input to the AND circuit 2 together with the signals H1 and B2 whose logics are inverted each other every horizontal scanning period. In the Igl horizontal scanning period, Hl
is “H” and B2 is “L”, so data selector W
The output of 2n is then inputted to the sample and hold circuit S/H-B via the level shifter 3, where sampling is performed.

At this time, the outputs of the data selectors W2n-1 and W2n are consecutive R and G in the first and second rows, respectively.

It is transmitted to three sample and hold circuits corresponding to the B pixels, for example, first R11e G12 * B13, then 几21 * G22 p "23, and then 几14
* Image signals for three consecutive primary color pixels in the same row are sampled at a time, such as G15 and B16, and this is alternately repeated over two rows. However, B (red)
The image signal of 2 pixels (i.e., 2T) is processed by the delay circuit 4.
, q (green) 1iiiIII image signals are similarly delayed by one pixel (i.e., IT), so as mentioned above, the timing signals of 几, G, B are substantially different in phase.
This is equivalent to sampling three times separately. Therefore, the clock pulse φ□ of the horizontal scanning shift register 1
This means that the frequency required is 1/3 of that required when sampling f pixels per pixel.

Next, when this sampling operation ends for the effective display period of the first horizontal scanning period, each sample and hold circuit S /H-A through the analog switch 8Aj and the buffer amplifier 7 with output control, the first
An image signal corresponding to the pixel in the row is applied to the column signal electrode Dr j, and the liquid crystal cell of the pixel in the first row is driven. At this time, the row signal electrode Ga-1 of the first row is selected before the above-mentioned image signal is output from the output control buffer amplifier 7 (that is, the row signal electrode Ga-1 is selected from the vertical scanning shift register 8). signal is input). That is, during the horizontal retrace period, the pixels are arranged in rows and fit into pixels. Then, before a new signal is added to the column signal voltage &Drj, the row signal becomes the [pole Ga-1, ,@L''.

When the effective display period of the wS2 horizontal scanning period begins, the output Qzn-1 of the horizontal scanning shift register 1 is output as the output of the data selector w2n-, as in the first horizontal scanning period, and is sampled via the level shifter 3. The signal is input to hold circuit j38/HA and sampling is performed.

On the other hand, the output Qzn is input to the AND circuit 2 as the output of the data selector W2n, but this time, Hl is 1L", contrary to the first horizontal scanning period, and B2 is @l(III
Therefore, after passing through level shifter 3, S/H-C is selected instead of sample-and-hold circuit S/H-B, and
A sampling operation is performed in exactly the same manner as in the first horizontal scanning period together with the sample hold circuit 3/H-A.
In parallel with this sampling operation, at a time approximately in the middle of the effective display period in the second horizontal scanning period, the analog switch 8Bj and An image signal corresponding to the pixels in the second row is applied to the column signal electrode Dr-J through the buffer amplifier 7 with output control, and the row signal electrode Ga-2 in the second row selected in advance causes the pixel in the second row to be applied to the column signal electrode Dr-J. The liquid crystal cells of the eye pixels are driven.

As is clear here, the sample and hold circuit 8/H-
A is a sample and hold circuit that repeats sample and hold every horizontal scanning period, 8/H-B.

The S/H-C performs sample and hold alternately once every two horizontal scanning periods, and the sample and hold circuit 8/H-A receives image signals corresponding to pixels in odd-numbered rows whose sampling timing is early; Hold circuit S/H-B
, S/H-C, image signals corresponding to even-numbered row pixels whose sampling timing is slow are sampled and held, respectively.

Thereafter, the same operation is repeated, and if the number of pixels in the vertical direction is, for example, 480 pixels, the three primary color image signals are sampled during 240 horizontal scanning periods, and all pixels are sampled once until the 241st horizontal scanning period. The selection drive will be performed one by one.

As a TV image, for example, interlaced NTSC
When dealing with image signals, one field has 262.
It is composed of 5 horizontal scanning periods. Therefore, in the case of a normal television receiver, the display using the image signal of the 263rd horizontal scanning period (in other words, the scanning line) is the display using the image signal of the 1st horizontal scanning period (in other words, the scanning line) in the vertical direction of the screen. , and is displayed by the image signal of the 264th horizontal scanning period (in other words, the scanning S
) should be located one position below the display by the image signal of ill horizontal scanning period (in other words, scan i). In this way, since the vertical positions of the scanning lines are different in the first field and the second field, the combination of two rows of pixels driven by the image signal of l horizontal scanning period can be set in the first field and the second field. It needs to change.

Therefore, taking this into consideration, the 26th
Only the pixels in the 111!1 row are driven with the image signal of 3 horizontal scanning periods, and the pixels of the 2nd row and the pixels in the 3rd row are driven with the #I signal of the 264th horizontal scanning period. There is. Therefore, the signal obtained by sampling the image signal by the sample-and-hold circuit S/H-A during the 263rd horizontal scanning period is not applied to the pixel. This is indicated as 几(X) in FIG.

Specifically, data selectors w2n-1 and w2n select the input opposite to the first field in the second field, and Q2n is 1 from W2n-1 and Q2n is 1 from W2n. The outputs of Q2n-t are respectively output.

That is, by switching the outputs of the data selectors w2n-1 and W2n for each field using the signal Pi, the sample-and-hold circuit selects the earlier sampling timing of the two sampled image signals for the first field first. The slower one is output first in the second field. In other words, in both the @1 field and the second field, the sample and hold circuit S/H-A outputs the sampled signal first, so in the second field, the sample and hold circuit S/H-A outputs the sampled signal first. In this case, the image signals corresponding to the pixels of even rows with slow sampling timing are outputted at the timing of Q2n, and the image signals corresponding to the odd rows with early sampling timing are sent to the sample and hold circuits S/H-B and S/H-C. The image signals are each sampled and held at the timing of Q2n-1.

In this way, the first. through the second field, the fifth
All pixels are selectively driven twice during the 04 horizontal scanning period.

Here, the primary color signals of 几, G, and H pass through a delay circuit 4 as necessary, and then are converted into two signals of positive polarity and negative polarity by a polarity reversing circuit 5, ~, GP, GN.

It is output separately into BP and BN. The sample-and-hold circuit 8/HA always samples and holds a positive signal, and the sample-and-hold circuits S/H-B and S/H-C always sample and hold a negative signal. This sampled and held signal is the analog switch %3, Snj
, Scj to switch the column signal T! 1 pole Dr
Therefore, the polarity of the image signal applied to the column signal electrode Dr j is switched every 1/2 horizontal scanning period.

Therefore, if we consider each pixel, 1 field contains 1 pixel.
Since image signals of different polarities are applied, the driving voltage of the liquid crystal cell 11 is AC driven at a two-field period, that is, a frame period (30 Hz). Note that the polarities of the image signals supplied to the sample-and-hold circuit S/H-A and the sample-and-hold circuits S/H-B and S/H-C do not have to be as described above, as long as they are opposite to each other.

Furthermore, in this embodiment, the column signal electrode Dr! Line inversion drive (in which the polarity of the image signal applied to the image signal is inverted every 1/2 horizontal scanning period, that is, the polarity of the image signal is inverted every row
The sample and hold circuit S/H-A, the sample and hold circuit S/H-B,
1ihi11 to sample with S/H-C! It is also possible to perform field inversion driving in which image signals of the same polarity are sampled and the image signals of the same polarity are inverted field by field without separating the polarities of the signals. In this case, the polarity of the image signal applied to the column signal electrode Drj is also the same as rI! applied to each liquid crystal cell 11. The polarity of the Ii image signal is also reversed for each field, resulting in an alternating current waveform with a two-field period.

In Figure @1, the number of horizontal pixels of the color liquid crystal panel 9 is 6.
It is thought that approximately 648 pixels will be required for a screen size of about 100 mm, but at this time, the required frequency &fH of the clock pulse φ□KIF of the horizontal scanning shift register 1 is as follows for an NTSC television image signal. It is calculated as follows.

-8,2Mllz Here, the reason for multiplying by 2/3 is that, as mentioned above, since the triangular array is used, the sampling point of the same primary color signal is twice the number of horizontal pixels, and the delay circuit of the image signal. 4 to perform simultaneous sampling of the three primary color signals. Generally, as the frequency of the lock pulse φ□ increases, the power consumption of the horizontal scanning shift register increases.

Therefore, the frequency of clock pulse φ□ is reduced to 1/2 (4, I
A dynamic shift register with a reset terminal (Rs) using a two-phase clock φH1lφH2 (MHz) is used as a horizontal scanning shift register.

Think about using it.

An example of its configuration is shown in FIG. 6, and an example of its operating waveforms is shown in FIG.

In FIG. 6, 21 is an analog switch, which here has a CMO8 configuration. 22 is a hold capacitor that holds the signal voltage immediately before turning off when the analog switch 21 is off, and may be replaced by a parasitic capacitor. Reference numeral 23 denotes a non-inverting circuit 7a, which is, for example, two inverters connected in series. 24 is an NMO8) transistor for reset, and when the two-phase clocks φH1 and φ8° are not applied for a long time such as during the retrace period, an H level is applied to the reset terminal R5 to stably deselect the shift register output. It works to maintain the condition.

When the horizontal scanning shift register 1 in FIG. 1 has, for example, 432 output stages (the number of horizontal pixels is 64
8), the circuit scale and power consumption can be reduced by using 216 cascaded circuits of the circuit shown in FIG. The circuit example shown in FIG. 6 can also be applied to horizontal scanning shift registers in other embodiments of the present invention, which will be described later.

In addition, as the horizontal scanning shift register 1 in the port 1 diagram,
When the number of output stages is 432 (horizontal pixel number 648
), a circuit using two systems of normal 1-clock input 216-stage shift registers may be used. In this case, the clock pulses of the two systems of shift registers have a phase of 1
By using two phase clocks differing by 8° as the respective clocks, output waveforms similar to those shown in FIG. 7 can be obtained.

FIG. 8 is a circuit diagram showing a circuit for forming the control signal H1+H2e HA t HB r HC applied from each input terminal of FIG. 1.

In the stone 8 diagram, 25 is a quaternary counter, and 27 is an and (
AND) circuit.

When a clock H/2 with a period half the horizontal scanning period (for example, it may be substituted with a four clock pulse φV of the vertical scanning shift register 8) is given to the quaternary counter 25, the upper bit Q1 has the horizontal scanning period. A signal that is inverted each time is obtained, and at the same time, the inverted signal Q1 is also obtained. These signals are exactly the signals required by H1tH2 in FIG.

On the other hand, as for the control g] signals He, HB, Ho, the fifth
A selection pulse corresponding to the output period "R" of the sample-and-hold circuits S/H-A, B, and C shown in the figure is required, but these control signals are provided by the output of the quaternary counter 25 and the output It is obtained by inputting the control signal OE to an AND circuit 27.

The signal HB formed from the lower bit output of the quaternary counter 25 has a 1/2 horizontal scanning period, and the signal HB is formed from the divided output of the upper bit and lower bit.

Hc is one horizontal scanning period.

Incidentally, in order to synchronize with the vertical scanning shift register 8, it is necessary to apply a signal ~ synchronized with the vertical synchronization signal to the reset terminal R of the quaternary counter 25.

Further, when the double-speed linear sequential scanning circuit shown in FIG. 1 is integrated into an IC, the number of input terminals can be reduced by incorporating the control circuit shown in FIG. 8.

Next, FIG. 9 is a block diagram showing another embodiment of the present invention,
FIG. 10 is a time chart showing the operation timings of the main circuits and the timings of the main signals in FIG. 9, respectively.

The major difference between this embodiment and the embodiment shown in FIG. 1 is that the number of sample and hold circuits connected to one column signal electrode is 3.
The system has been changed to four systems, the buffer amplifier 12 without output control is used instead of the buffer amplifier 7 with output control, and the combination of corresponding pixels of the image signal sampled at one time has been changed. Accordingly, Rin, G, B
The difference is that the amount of delay of the delay circuit 4 for delaying the image signal of is changed.

As can be seen by comparing the operation timings in FIG. 5 and FIG. 10, the sample hold circuit S/H-A in FIG.
Therefore, in the embodiment shown in FIG. 1, the number of sample and hold circuits per column signal electrode is only three. However, with this configuration, the sample and hold circuit S/H-A
As shown in the figure, sampling must be performed at all times during the effective display period of one horizontal scanning cycle, so the output period "R" from the sample and hold circuit 8/H-A must be within the horizontal retrace period. . Therefore, in the embodiment shown in FIG. 1, a buffer amplifier 7 with output control is used, and the buffer amplifier 7 is operated for a time corresponding to the horizontal retrace period to drive the column signal electrode Dr j, and the remaining period is The signal voltage was held by a hold capacitor or a parasitic capacitor connected to the column signal electrode Dr j.

Further, although there is no restriction on the output time of the sample and hold circuits S/H-B and C, the output time is set to be the same as that of the sample and hold circuit S/H-A in consideration of variations in drive voltage. However, such a short output time of 1R''
In this case, the column signal v1 pole Dr J is not driven sufficiently and is easily affected by circuit variations. In addition, the column signal electrode Dr
If there is a leak in j, the held signal voltage may change.

Therefore, in this embodiment, four sample and hold circuits are provided for each column signal electrode, and as shown in FIG.
In the horizontal scanning period, the sample and hold circuit S/H-A,
S/H-B performs sampling operation, sample and hold circuits S/H-C and S/H-D perform hold operation, and in the second horizontal scanning period, each performs the opposite operation, so that the output time is 9R. The buffer amplifier 12 always outputs a signal, but a buffer with output control is used instead. It is also possible to reduce power consumption by using a method in which the signal is output only for a necessary and sufficient time.

In FIG. 9, the output of the AND circuit 2 is connected to three sample and hold circuits corresponding to the three primary color pixels closest to each other among the two adjacent rows of pixels. In the first horizontal scanning period, R
11 (in this case, since there are no adjacent pixels, only 1i# elements are sampled), then G12 * B13
* R21, then 814 r (3zz t B
22, image signals corresponding to each pixel are sampled sequentially from the left side of the liquid crystal panel 9.

At this time, in the embodiment shown in FIG. 1, image signals corresponding to three consecutive pixels in the same row were sampled at one time, so 2 pixels (i.e., 2T) for G, and 1 pixel for G. (mchi, IT), each image signal had to be delayed, but in this embodiment, since the pixel signals for the three closest pixels across two rows are sampled, the delay is 1/2 pixel portion (i.e. 1/2T),
As for G, it is possible to suffice with a delay of one pixel (IT), making it easy to manufacture the delay circuit 4.

Note that the signals HA, HB, Hc, and HD in FIG. 9 can be easily obtained by simply decoding the outputs Qo and Qr of the quaternary counter 25 shown in FIG. 8.

The other operations in this embodiment are almost the same as those in the embodiment shown in FIG. 1, so their explanation will be omitted.

Next, FIG. 11 is a block diagram showing another embodiment of the present invention.

In FIG. 11, 13 is a level shifter, and 14 is a data selector using an analog switch.

In this embodiment, as in the embodiment shown in FIG. 9, there are four sample and hold circuits per column signal electrode, but the major difference from the previous embodiment is that The amount of delay of the delay circuit 4 for delaying each image signal is 1/2
It only takes one pixel (i.e., 1/2T), and one pixel (i.e., I
There is no need to use a delay circuit that is long and has large variations such as T) or two pixels (that is, 2T).

Instead, the signal obtained by decoding the output of the horizontal scanning shift register l by the signal H1#B2 in the AND circuit 2, that is, the output of the AND circuit 2, is a sample hold signal of two systems. It will be connected to the circuit, so the horizontal scanning shift register l
The frequency of the clock pulse φ□ is 15 times that of the embodiments shown in FIG. R1 and FIG. 9 (the actual frequency is
By setting the coefficient of the second term of equation (1) to 2/2 (that is, 1).

will be given. )0 In other words, for a triangular array in which pixels are shifted horizontally by 1.5 pixels in every other row, the delay circuit 4 shifts the phase by 0.5 pixels,
This method reduces the sampling clock frequency to half (half the sampling clock frequency when sampling one pixel at a time) by simultaneously sampling the image signal that has been detected and the image signal that does not have a phase shift.

Further, in this embodiment, unlike the embodiments shown in FIGS. 1 and 9, the arrangement order of the polarity inverting circuit 5 and the delay circuit 4 is reversed, and a data selector 1 using an analog switch is provided between them.
4 is inserted and switched for each field. This means that the polarity of the image signal applied to the column signal electrode is reversed for each row, and for each pixel, for each field,
This is to support line inversion drive (row-by-row inversion drive) in which the polarity of the image signal applied to the liquid crystal cell is inverted. In addition, when performing field inversion driving as described above, the data selector 14 is not required, and it is sufficient to directly connect the image signal that is inverted for each field.Other operations in this embodiment are the same as in the embodiment shown in FIG. Since they are similar, their explanation will be omitted.

〔Effect of the invention〕

According to the present invention, it is possible to easily selectively drive two rows of pixels during one horizontal scanning period, and also to perform line sequential scanning and row-by-row inversion driving while supporting the triangular arrangement of color filters. For example, when driving a liquid crystal panel with approximately 480 vertical pixels using an NTSC television image signal, by reversing the polarity of the image signal every field, the voltage applied to the liquid crystal cell is applied at a cycle of 2 fields (1 frame). ,
In other words, it is an AC signal of 30 Hz, has less flicker, can extend the life of the liquid crystal element, and can provide high-definition display due to the triangular arrangement of color filters.

Further, according to the present invention, since a digital double speed conversion circuit is not used, the circuit scale does not become large, and furthermore, a delay circuit is used to generate pixel signals corresponding to a plurality of pixels to be sampled at different timings. By sampling at once, the speed of the horizontal scanning circuit can be reduced, so
The circuit configuration is also simplified and power consumption is reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Figs. 2 and 3 are explanatory diagrams for explaining the operation of the embodiment of Fig. 1, and Fig. 4 is a color diagram of Fig. 1. A circuit diagram showing the configuration of one pixel in a liquid crystal panel, Fig. 5 is a time chart showing the operation timing of the main circuit and the timing of the main part signals in Fig. 1, and Fig. 6 is a diagram for horizontal scanning in Fig. 1. A circuit diagram showing another specific example of the shift register, FIG. 7 is a time chart showing the timing of the main signals in FIG. 6, and FIG. 8 is a diagram showing the control signals H1, H2°H, HB,
FIG. 9 is a circuit diagram showing a specific example of a circuit for forming Hc, and FIG. 9 is a block diagram showing another embodiment of the present invention.
0 is a time chart showing the operation timing of the main circuit and the timing of the main part signals in FIG. 9, and FIG. 11 is a block diagram showing another embodiment of the present invention. Explanation of symbols 1...Horizontal scanning shift register, W...music data selector, 2...AND circuit, 3...
・・Level shifter, 4・・・・Delay circuit, 5・River・
・Polarity inversion circuit, S/H... Sample hold circuit, S... Analog switch, 7...
・Output buffer with output control, 8...Vertical scanning shift register, 9...Liquid crystal panel, Ga...
... Row signal electrode, Dr... Curved column signal electrode, 10...
Song MOS transistor, 11... Song LCD cell representative Patent attorney Akio Namiki Figure 2 (Do 1) Figure 15 Figure 4 ■ Figure 5 (b) Fang 2 field 6th episode Figure 7! J8 figure

Claims (1)

[Claims] 1. After arranging a plurality of pixels consisting of switching elements and liquid crystal display elements in a matrix, and connecting the pixels in the same column to the same column signal electrode, the pixels in each row are set to red. A liquid crystal panel constructed by sequentially corresponding to the three primary colors of , green, and blue, and rearranging adjacent pixels corresponding to the same color in at least adjacent rows to have a distance of 1.5 pixels from each other in the row direction. In a liquid crystal color image display device, an image is displayed on the liquid crystal panel by supplying a desired drive signal to each column signal electrode and controlling on/off the switching element in each pixel. A signal and a clock signal are input, the image signal is sampled at the input timing of the clock signal, and then the sample and hold circuit is divided into a plurality of sample and hold circuits that hold the signal, and the image signal is inputted. A control means for sequentially outputting the clock signal to each group at a rate of one clock per group in synchronization with a sampling pulse, and controlling the sample and hold circuits in the same group to perform sampling operations simultaneously; and the sample and hold circuit. A delay means is provided to adjust the time by delaying the image signal to be input in advance so that the image signal to be held is input during the sampling operation, and during one horizontal scanning period,
An image signal corresponding to a position in the row direction of each pixel in two adjacent rows is sampled and held in the sample-and-hold circuit corresponding to each pixel, and the sample-and-hold circuit is set as a set of two, The pixels corresponding to the mutually held image signals are grouped into two pixels connected to the same column signal electrode, and the outputs from the two sample and hold circuits in each group are switched for each group. A connection means is provided for connecting one of the column signal electrodes to the corresponding column signal electrode, and the output from the sample and hold circuit is switched at a predetermined timing by each connection means during another horizontal scanning period. A double-speed line sequential scanning circuit characterized in that image signals corresponding to pixels in two adjacent rows held in the circuit are supplied to each column signal electrode one row at a time as the drive signal.