JPS63229858A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the speedup of operation of a semiconductor device, an increase in the density of the device and the improvement of reliability of the device by a method wherein an impurity layer having a conductivity type inverse to that of a semiconductor substrate is formed in the substrate surface to bore a groove and impurity diffused layers having a conductivity type inverse to that of the substrate are provided separately from a gate electrode for filling the groove. CONSTITUTION:An n-type epitaxial layer 103, which is an impurity layer having a conductivity type inverse to that of a p-type semiconductor substrate 101, is formed in the surface of the substrate 101, a groove 113 to reach the substrate 101 is bored and is used as a channel region and at the same time, the layer 103 is halved by the groove 113 to form drain and source regions. A gate electrode 108 is buried in the groove 113 through a high-concentration p<+> impurity region 105 on the bottom part of this groove 113 and a gate insulating film 106 to reach the surface of the layer 103. Moreover, high-concentration n<+> diffused layers 109 and 110 having a conductivity type inverse to that of the substrate 101 are formed in the layer 103 separately from the edge end parts of the electrode 108. By this constitution, the injection of electrons into the film 106 is inhibited, the electric capacities of the layers 109 and 110 are decreased and the operation of a semiconductor device can be speeded up. Moreover, the channel length is decided by tie width and depth of the groove, an increase in the density of the device can be contrived and the reliability of the device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an MO3 type semiconductor device.

[Conventional technology]

Conventionally, attempts have been made to shorten the channel in an attempt to achieve high-density design of MO3 type semiconductor devices, but when shortening the channel is done using an N-channel MOS (MOS) transistor on a P-type substrate, the electric field between the source and the train is strong. As a result, the impact ionization phenomenon near the drain is amplified and current flows to the substrate, and electrons flow to the gate electrode side and are captured in the gate insulating film, causing fluctuations in the threshold voltage and deterioration of the withstand voltage of the gate insulating film. This is not desirable in terms of reliability.

In addition, the substrate current increases the substrate potential, and due to the increase in drain current due to the NPN transistor structure,
The so-called snap-back voltage will drop, making it impossible to apply a high drain voltage. Furthermore, since the margin for the power supply voltage is reduced, there is no margin for noise, which poses a problem in terms of reliability.

Although the shortening of the channel has improved to some extent and high-speed operation is possible, the above-mentioned problems have hindered technological improvements.

Conventionally, in order to solve the above problem, a method has been adopted in which the concentration of the diffusion layer near the drain of the MO3 type transistor is made relatively low to increase the snapback voltage.

This will be explained below using FIG. Here, P type substrate 3
The method for manufacturing an N-channel transistor using 01 is shown, and even when used in a complementary type, the N-channel transistor
Transistors are described to mean that they exhibit similar functional characteristics. That is, it is well known that in complementary devices, the above-mentioned phenomenon causes a latch-up phenomenon, which is very disadvantageous. With this point in mind, examples of methods that have been considered in the past will be explained.

First, as shown in FIG. 3(a), a P-type semiconductor substrate 30
1, a field insulating film 302 is formed by the usual selective oxidation method, a gate insulating film 303 is provided in the active region, and a gate electrode 304 is formed thereon by impurities such as phosphorus in polycrystalline silicon. Thereafter, source/drain diffusion layers 305 and 306 are formed using an ion implantation method with a relatively low impurity concentration.

Next, as shown in FIG. 3(b), a photoresist 307 is applied to cover the gate electrode 304 and at least the vicinity of the drain.
are formed to form diffusion layers 308 and 309 with high impurity concentration.

After that, as shown in FIG. 3(c), the insulating film 310 is
For example, the metal wirings 311 and 312 are grown using a vapor phase growth method or the like, and predetermined contact holes for connection are opened to provide metal wirings 311 and 312.

In this way, the cross-sectional structure of the conventional example is shown in FIG. It is characterized in that there is a region with high impurity concentration separated by a certain distance from the gate electrode 304. Because of this structure, when a voltage is applied to the drain,
The electric field strength between the train and the substrate, which has a low impurity concentration, is weakened, increasing the snapback voltage.

The high concentration diffusion layer lowers the source/drain resistance,
This is done to achieve high-speed operation.

[Problem that the invention seeks to solve]

In the conventional N-channel MO8 type transistor described above, the source train is determined by the gate electrode 304 in a self-aligned manner, and in order to shorten the channel, the impurity concentration of the source/drain diffusion layer and the subsequent heat treatment must be adjusted. The depth of the diffusion layer and the dimensions of the gate electrode must be reduced. In order to shorten the channel, it is possible to increase the impurity concentration of the substrate, but even if this is effective in shortening the channel, it will increase the junction capacitance and also prevent electron injection into the gate insulating film. This increases and becomes an impediment to higher speed and higher reliability. Furthermore, since the gate electrode and the high concentration region must be isolated, a margin for this is necessary for the phosphorography technique, which also hinders higher density.

An object of the present invention is to provide a method for manufacturing a semiconductor device that is capable of high-speed operation, has higher density, and has improved reliability.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes the steps of: - forming a field insulating film on a conductive type semiconductor substrate; and introducing impurities from the surface of the semiconductor substrate surrounded by the field insulating film, or performing epitaxial growth on the semiconductor substrate. forming an opposite conductivity type impurity layer, and forming a groove reaching into the semiconductor substrate from the surface of the opposite conductivity type impurity layer, and then introducing an impurity into the bottom of the groove to form a one conductivity type impurity layer. a step of forming a concentrated impurity layer, a step of forming a gate insulating film on the entire surface including the groove surface, a step of filling the trench in which the gate insulating film is formed to form a gate electrode, and a step of forming a gate electrode at the end of the gate electrode. forming a highly concentrated impurity layer of opposite conductivity type by introducing an impurity from the surface of the opposite conductivity type impurity layer or depositing a conductor on the opposite conductivity type impurity layer. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type semiconductor substrate 10
A field oxide film 102 is formed on the surface of the oxide film 102 by a normal selective oxidation method. The active region is a portion of the surface of the P-type semiconductor substrate 101 that is exposed.

Next, as shown in FIG. 1(b), an epitaxial layer containing a relatively low concentration of N-type impurities is grown over the entire surface of the semiconductor substrate, and a field oxide film 10 is grown using a grinding or polishing method.
No epitaxial layer is left on 2, and the N-type epitaxial layer 103 is left buried in the active region.

Thereafter, a photoresist 104 is applied and a predetermined portion is removed, and using the photoresist 104 as a mask, a groove 113 is formed extending from the surface of the N-type epitaxial layer 103 to the inside of the P-type semiconductor substrate 101. Next, a P-type impurity is introduced into the bottom of the trench 113 by ion implantation to form a P-type impurity N105.

Next, as shown in FIG. 1(c), a photoresist 104
After removing, the gate insulating film 106 is formed by thermally oxidizing the trench and the epitaxial layer.

Next, polycrystalline silicon containing an impurity such as phosphorus is grown on the entire surface so as to fill the groove 113, and a photoresist 107 is formed leaving a portion where a gate electrode is to be formed, and this is used as a mask. A gate electrode 108 made of polycrystalline silicon is formed under the photoresist 107 by etching the polycrystalline silicon.

At this time, the edge of the gate electrode 108 and the photoresist 10
Usually, there is a difference at the edge of 7. Therefore,
Next, using the photoresist 107 as a mask, N-type impurities are introduced into the N-type epitaxial layer 103 by ion implantation.
A + type scattering layer 109110 is formed. Therefore, the N+ type scattering layer 109110 is provided at a certain distance from the end of the gate electrode 108, and
It consists of a type epitaxial layer 103 and is formed within a source/drain low concentration diffusion layer separated by a trench 113.

Next, as shown in FIG. 1(d), a photoresist 107
After removing the insulating film 111, an insulating film 111 is grown using a vapor phase growth method after an appropriate heat treatment, and a contact hole for connection is formed at a predetermined position. After that, metal wiring 112 is applied and MO3
Complete the type semiconductor device.

In the MO3 type semiconductor device manufactured in this way, the channel length can be determined by the width and depth of the groove 113 formed by one-time lithography, and high-density design is possible. Furthermore, since the drain diffusion layer is formed from the lightly doped N-type epitaxial layer 103, the snapback voltage is increased and the power supply margin is expanded, thereby improving reliability.

In addition, since the P-type impurity layer 105 with a relatively high impurity concentration is formed only in the channel region, and is not in contact with the source or drain diffusion layer, the source/train diffusion layer has a low concentration, which insulates the gate. Electron injection into the film is suppressed, the electrical capacity of the diffusion layer is reduced, reliability is improved, and high-speed operation is possible.

Furthermore, since the region surrounded by the field oxide film is filled with an N-type epitaxial layer, there is no step, and since the trench 113 is filled with gate electrode material, the surface is flattened and the metal wiring It has advantages such as being able to have multiple layers.

FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), a P-type semiconductor substrate 10
1, a field oxide film 102 is formed. Next, N-type impurities are introduced into the active region using ion implantation,
An N-type diffusion layer 203 is formed. This corresponds to the N type epitaxial layer 103 in FIG. 1(b).

Next, as shown in FIG. 2(b), a groove is formed in the same manner as in the first embodiment, and then a relatively high concentration P-type impurity layer 105 is formed on the substrate. After forming the gate insulating film 106 and removing a part of the gate insulating film, polycrystalline silicon containing an N-type impurity, such as phosphorus, is grown to fill the trench and field oxidation 11A, 10 is formed.
Fill in the area surrounded by 2. Next, this polycrystalline silicon is patterned using a lithography technique to separately form source/drain regions 206 and 207 and gate electrode 208. After that, an insulating film 111 is grown, a contact hole is opened at a predetermined position, a metal wiring 112 is formed, and the MO
Complete the S-type semiconductor device.

In this second embodiment, a low concentration source/drain is formed by separating an N-type diffusion layer formed by ion implantation over the entire surface of the active region of the substrate with a trench, and forming a low concentration source/drain in the substrate at the bottom of the trench. Structurally, the surface of the active region is planarized by forming a P-type impurity layer on the surface, and simultaneously forming a gate electrode made of polycrystalline silicon and an electrode that will become the source/train region via a gate insulating film. It is a characteristic.

The MOS type semiconductor device formed in this way has a source/drain formed with a relatively low concentration, has a high snapback voltage, and has a small electrical capacitance of a diffusion layer, so that high-speed operation is possible. . In this second example,
Gate electrode 208 and highly doped source/train region 20
6 and 207 at the same time, and since the electrodes that become the source and drain regions are formed using polycrystalline silicon, the metal wiring The influence of alloy spikes caused by this is eliminated, and leakage current is suppressed. Therefore, shallow junctions can be formed, high-density flattening can be achieved, the resistance of this electrode can be freely lowered, and high-speed operation can be achieved.

Although the above embodiment has been described using a P-type substrate, it can also be applied to a P-channel transistor on an N-type substrate, and when used in a complementary device, a latch characteristic of the complementary device can be applied.・This has the effect of making it difficult for the up phenomenon to occur.

〔Effect of the invention〕

As explained above, the present invention includes forming an opposite conductivity type impurity layer on the surface of a -conductivity type semiconductor substrate, digging a groove reaching into the semiconductor substrate in this impurity layer, forming a gate insulating film on the surface,
By filling this groove to form a gate electrode and forming a highly concentrated impurity layer of opposite conductivity at a certain distance from the edge of the gate electrode, high-speed operation and high-density design are possible. , it is possible to obtain a semiconductor device with improved reliability.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) and FIGS. 2(a) to 2(b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention. 3(a) to 3(C) are cross-sectional views of a semiconductor chip for explaining a conventional method for manufacturing a semiconductor device. 101... P-type semiconductor substrate, 102... Field oxide film, 103...・N-type epitaxial layer, 104・
... Photoresist, 105 ... P-type impurity layer, 106
... Gate insulating film, 107 ... Photoresist, 10
8... Gate electrode, 109.110... N+ type scattering layer 111... Insulating film, 112... Metal wiring, 11
3... Groove, 203... N-type diffusion layer, 206.207
... Source/drain region, 208... Gate electrode, 301... P-type semiconductor substrate, 302... Field insulating film, 303... Gate insulating film, 304... Gate electrode, 305.306 ... Source train diffusion layer, 307... Photoresist, 308, 309...
Diffusion layer, 310... Insulating film, 311, 312... Metal wiring. Ward 4

Claims (1)

[Claims] A step of forming a field insulating film on a semiconductor substrate of one conductivity type, and forming an impurity layer of an opposite conductivity type by introducing impurities from the surface of the semiconductor substrate surrounded by the field insulating film or by performing epitaxial growth on the semiconductor substrate. forming a groove reaching into the semiconductor substrate from the surface of the opposite conductivity type impurity layer, and then introducing an impurity into the bottom of the groove to form a high concentration impurity layer of one conductivity type; a step of forming a gate insulating film over the entire surface including the groove surface;
a step of filling the trench in which the gate insulating film is formed to form a gate electrode; and introducing an impurity from the surface of the reverse conductivity type impurity layer apart from the end of the gate electrode or conductive on the reverse conductivity type impurity layer. 1. A method for manufacturing a semiconductor device, comprising the step of forming a highly concentrated impurity layer of opposite conductivity type by depositing an impurity layer.