JPS63226777A - Image data reading system - Google Patents

Abstract

PURPOSE:To increase the number of divided parts in one line and to improve the reading accuracy of image data by automatically forming a slice level value by a hardware. CONSTITUTION:Prior to reading out image data, slice level values respectively corresponding to plural divided image signals are previously stored in an FIFO 11 through a selector 10. During the period of image data reading based on a line sensor 1, the oldest slice level value out of plural ones stored in the FIFO 11 is outputted to a comparator 7 every input of a shift clock signal and simultaneously reinputs its output as the up-to-date slice level value. Since the shift clock signals corresponding to the divided number are applied to the FIFO 11, the slice level values corresponding to one period, i.e. one line, can be outputted to the comparator 7 and the image data can be identified by comparing the image signal with the slice level value through the comparator 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image data reading method in a device having an image reading function.

(Prior art) The conventional image data reading method is shown in Fig. 2 (a) and (b).
I will explain about it. That is, the image signal a photoelectrically converted by the licensor 1 and further amplified by the amplifier 2 is sent to the comparator 7.
The slice level value of the image signal is input to one input (-) of the comparator 7, and the other input (+) of the comparator 7 is input. The slice level value is 1, for example, as shown in FIG. m digital values (Vl
.

V2. ...Vm) is stored. When the CPU 3 is interrupted by a shift clock signal, it reads a digital value stored in the memory, and then executes a parallel input/output controller (hereinafter referred to as PIO), which is an input/output interface that handles parallel signals according to a write command.
4).

The output C from the PI04 is input to the register 5 by the shift clock signal S, and the output d of the register 5 is input to the D/
The signal is input to the A converter 6 and converted from a digital value to an analog value. The output of the D/A converter 6 is sent to the comparator 7.
The analog value is compared with the image signal a, and as shown in the binarized data signal e, the white data has a low level value "0" and the black data has a low level value "0". Converted to high level value "1". The above process is executed for m divisions per line, that is, m times, to read one line of image data.

(Problem to be Solved by the Invention) However, in the system with the above configuration, the slice level value is read from the memory of the CPU 3 and written to the PIO 4 by an interrupt to the CPU 3 by the shift clock signal. When processes such as motor driving and printing overlap, it takes time to read the slice level value from the memory of the CPU 3 and write it to the PI04. Therefore, if the period of the shift clock signal S is shortened, the time required for an interrupt by the next shift clock signal S is reduced.
A state in which the above processing is not completed, a so-called overrun, occurs.

Therefore, since the cycle of the shift clock signal must be limited, the number of divisions of one line of the image signal cannot be increased, resulting in a problem that the reading accuracy of the image signal cannot be improved.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an image data reading method that enables further segmentation of an image signal and thereby allows the image signal to be read with high precision.

(Means for Solving the Problems) In order to achieve the above object, the present invention uses a means for comparing an image signal obtained by dividing one line in the main scanning direction into a plurality of parts and the slice level value of each of the divided image signals. An image data reading method for reading image data by comparison includes a storage means for storing each slice level value as needed, and a selection means for appropriately selecting an input to the storage means, the storage means , before reading the image data, input slice level values for the number of divisions of the image signal through the selection means, and while reading the image data, the oldest slice level stored in the storage means is input for each shift clock signal. The present invention is characterized in that the value is output to the comparison means, and the output is re-inputted as the latest slice level value via the selection means.

(Function) According to the above configuration, before reading the image data, the slice level values corresponding to each of the divided image signals can be stored in advance in the storage means via the selection means, and while the image data is being read. In the shift clock signal, the oldest slice level value among the plurality of slice level values stored in the storage means is output to the comparing means, and at the same time, the output is re-inputted as the latest slice level value. By supplying the clock signal by the number of divisions to the storage means, the slice level value for one period, that is, one line, can be output to the comparison means, and by comparing the image signal and the slice level value with the comparison means, the image data can be identified. Can be done.

(Embodiment) FIGS. 1, 3 to 5(a) and 5(b) show embodiments of the present invention, and the same components as those of the conventional example are denoted by the same reference numerals. That is, 1 is a line sensor, 2 is an amplifier, and 3 is a C
PU, 6 is a D/A converter, and 7 is a comparator, which binarizes the result of comparing the image signal output from the amplifier 2 and the analogized slice level value from the D/A converter 6. Output as a data signal.

10 is a selector which stores the slice level value on the data bus 14 output from the CPU 3 in response to the OUT command and the first-in-first-out (hereinafter referred to as FIFO) 11 that outputs the first input data first. One of the slice level values and the output B is selected according to the level value of the select signal A, and the input of the FIFO II is determined. The selector 10 is configured such that when the select signal A is at a low level "0", the slice level value from the CPU 3 is selected, and when the select signal A is at a high level "1", the output B is selected and input. Incidentally, when one line is divided into n parts and a slice level value is determined, the FIFO II is composed of n stages of memory. Reference numeral 12 denotes an order decoder which inputs instructions from the CPU 3 via the address bus 15 and outputs the result of decoding the instructions as a pulse signal E.

Here, n slice level values (Vl,
A case where the select signal A is at a low level rOJ will be described.

First, a differential signal is generated at the trailing edge of the select signal A that is active during the valid period of the image signal F, and when this signal interrupts the CF'U3, the CPU 3 enters the interrupt processing routine and issues an OUT command. put out. The OUT command is input to the order decoder 12 via the address bus 15, and as a result of being decoded, a pulse output E is output as 20R13.
The signal is input as the clock signal of the FIFO II via the FIFO II.

On the other hand, due to the OUT command, the CP
The slice level value stored in the memory of U3 is transferred to the FIFO via the data bus 14 and the selector 10.
II. The relationship between the input and output B is the FIF
When vl is input to OII, v'1 is output as output B, when v2 is input, V'2 is output, and in the same way, when vn is input, v'n is output. ing.

However, V'1 to v'n are slice level values previously stored in the FIFO II.

As described above, the setting of the slice level value to be given from the CPU 3 to the FIFO 11 is based on the trailing edge differential signal of the select signal A indicating the effective range of the image signal F.
By using the U3 interrupt and executing the process using the interrupt, it is not possible to limit the process to the low level "0" period of the select signal A.

Next, the case where the select signal A is at a high level "1", that is, the case where the output B of the FIFO II is input to the D/A converter 6 and re-input to the FIFO II via the selector 10 will be explained. .

As shown in FIG. 5(a), the slice level value V1 stored in the final stage of the FIFO II is output as an output B by the shift clock signal C passing through the 20R13, and the output B is As shown in FIG. 5(b), the FI
Re-entered into FOII. The slice level value v1, which is a digital value, inputted to the D/A converter 6 is converted to a voltage level, which is an analog value, and outputted, and inputted to the input (+) of the comparison value 7. One input of (−
) is compared with the image signal F, which is the input of the comparator 7, and the comparator 7 outputs it as a binarized data signal G. Thereafter, similar processing is repeated until the final slice level value Vn of one line is compared with the image signal F in the comparator 7 and outputted from the comparator 7 as a binarized data signal G.
times) to read one line of image data. Note that in this process, the shift clock signal C is
It will be output for the number of divisions of the slice level value, that is, n times.

(Effects of the Invention) As described above, according to the present invention, the slice level value is stored in the storage means before image data is read, and during image data reading, the slice level value is stored in the oldest slice level value in the storage means by a shift clock signal. By outputting the slice level value of , and re-inputting the output to the storage means as the latest slice level value, the slice level value can be autonomously given by hardware, and the firmware processing is the slice level value giving process. Since the number of divisions of one line can be increased without overrun, there is an advantage that the accuracy of reading image data is increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image data reading method of the present invention, FIG. 2(a) is a block diagram showing an embodiment of the conventional image data reading method, and FIG. Figure 2 (
FIG. 3 is a waveform diagram to explain the operation of FIG. 1. FIG. 4 is a diagram showing slice level values stored in the memory of the CPU. FIGS. 5(a) and 5(b) are diagrams showing slice level values stored in FIFo. In the figure, 1...Licensor, 2...Amplifier, 3...
cPU, 4...PIo, 5...Register, 6:...
D/A conversion circuit, 7... Comparator, 10... Selector, 11... FIFo, 12-... Order decoder, 1
3-2 OR. 14...Data bus, 15...Address bus. Patent applicant Oki Electric Industry Co., Ltd. Agent Patent attorney Yoshi 1) Takashi Sei CV+
V2 V3 V4 --- Vme I want to use the elephant data λ. ) Slice level M'i, -r in FIFO, Figure 5 (b)

Claims (1)

[Scope of Claims] An image data reading method in which image data is read by comparing an image signal obtained by dividing one line in the main scanning direction into a plurality of parts and slice level values of each of the divided image signals using a comparing means, comprising: The storage means has a storage means for storing the slice level value as needed, and a selection means for appropriately selecting an input to the storage means, and the storage means selects the image signal via the selection means before reading the image data. The slice level values corresponding to the number of divisions are input, and during image data reading, the oldest slice level value stored in the storage means is outputted to the comparison means for each shift clock signal, and the output is outputted to the selection means. An image data reading method characterized by re-inputting the latest slice level value through means.