JPH0134422B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a significant pixel block detection method for facsimile devices.

In facsimile apparatuses that handle black and white binary images, there is a method in which one line is divided into a plurality of blocks, and the image signal of only the block containing significant pixels (usually black pixels) is transmitted, and the rest are not transmitted.
For this purpose, it is necessary to detect which block contains significant pixels from the image signal sequence obtained by reading scanning.

A conventional detection device is shown in FIG. An image signal for one line is led to a memory 2 via an input line 1 and is stored therein. Reference numeral 3 designates a read address counter for the memory 2, which is incremented by a clock pulse _Cp inputted through an AND gate 4.
Memory 2 according to the address specification of counter 3
The image signal read out from the exclusive NOR circuit 5 is supplied to one input terminal of the exclusive NOR circuit 5, and is also supplied to the other input terminal of the exclusive NOR circuit 5 via a 1-bit delay circuit 6. Therefore, this exclusive NOR circuit 5
becomes "0" when the image signal changes from white to black or from black to white. Of course, as described later, the 1-bit delay circuit is reset in the initial state (corresponding to white), so
This indicates the change from white to black. When the output of this exclusive NOR circuit becomes "0", an interrupt is generated to the black block detection circuit 7 composed of a microcomputer. As a result, the black block detection circuit 7
outputs “0” to signal line a and executes AND gate 4.
At the same time, the count value of the counter 3 at that time is read. Then, by calculating, for example, dividing this count value by the number of pixels in one block, it is determined in which block this change has occurred. The detection results are temporarily stored. Next, the detection circuit 7 resets the 1-bit delay circuit 6, loads the counter 3 with a numerical value corresponding to the first block following the block obtained by this detection, and further changes the signal on the signal line a to " Return to 1”. Detection of the next black block is then started, and such a detection operation is repeated. When the counter 3 reaches a full count state, a carry signal is generated on the signal line c. The black block detection circuit 7 thus completes the detection operation for one line, controls the memory 2 to write state, and starts the next one.
Write the image signal for the line. After writing, the above operation is repeated again. The temporarily stored detection results, ie, black block information, are used for transmission processing.

In this way, black blocks can be detected, but as mentioned previously, this conventionally required arithmetic processing functions. Although microcomputers are equipped with arithmetic processing functions,
It took a considerable amount of time and was a problem.

By the way, conventionally, the number of pixels in one line is 2.
, which is a power of 2 ^l , and is divided into 2 ^m blocks each having 2 ⁿ pixels. Here l
=m+n.

The present invention focuses on this point and solves the above problems, and will be described below with reference to FIG. 2.

In FIG. 2, the same components as those in FIG. 1 are given the same reference numerals, and individual explanations will be omitted. The difference from the conventional example shown in FIG. 1 lies in the black block detection circuit 17. When the output of the exclusive NOR circuit 5 becomes "0", the black block detection circuit 17 reads the upper m bits of the counter 3 as is as a black block number and temporarily stores it. In other words, if one line consists of 2 ^m+n pixels and is divided into 2 ^m blocks each having 2 ⁿ pixels, the upper m bits of the output of counter 3 represent the block number itself at that time. It represents. Therefore, the number of the black block can be detected without going through the conventional calculation process.

The configuration of the black block detection circuit 17 may be a microcomputer or other so-called wire logic circuit. The other operations of the black block detection circuit 17 are similar to those of the conventional device.

As described above, according to the present invention, high-speed processing is possible because calculations for detecting significant pixel blocks are not required, and one or at most two microcomputers normally provided in a facsimile machine can be used.
When used together with other controls to detect significant pixel blocks, the load can be reduced, which is preferable.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional black block detection device.
FIG. 2 is a diagram showing an embodiment of the present invention. 2...Memory, 3...Address counter, 6...
...1-bit delay circuit, 7...black block detection circuit.

Claims (1)

[Claims] 1 The image signal of one line divided into 2 ^m blocks each having 2 ⁿ pixels is read out from the memory sequentially according to the address specification from the address counter, and the change is detected. In a method of detecting the number of a block in which a significant pixel exists from the output signal of the address counter at a time, the signal of the upper m bits of the addressing output signal consisting of m+n bits of the address counter at the time when the above change is detected. A significant pixel block detection method is characterized in that a significant pixel block is detected as the number of a block in which a significant pixel exists.