JPS63223853A - Bus arbitrating circuit - Google Patents

Abstract

PURPOSE:To perform the fast arbitration of buses via a simple circuit according to the output characteristics of an open collector. CONSTITUTION:When a bus application request signal 11 is inputted, a recognizing signal generating circuit 12 produces a signal group so that the low and high level signals are increased one by one with modules having high and low bus application priorities respectively. An arbitrating signal line group 15 consists of signal lines in the number larger than the number of modules using buses. An open collector output circuit 13 outputs the recognizing signal produced by the circuit 12 to the group 15. In case plural modules have the bus application requests, the signal obtained from collision between signals of high and low levels is set at a low level since the output of an open collector is given to the group 15. Therefore a comparator 14 of the module having the highest priority among those modules having bus application request obtains the coincidence between the signal produced by the circuit 12 and the signal set on the group 15 and outputs a bus application permitting signal 16.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bus arbitration circuit for a system having a plurality of modules using a bus.

2. Description of the Related Art In conventional bus arbitration circuits, a method is often used in which an encoder and a decoder are used to provide arbitration signals to each module in response to arbitration participation signals from modules using each bus.

An example of the conventional bus arbitration circuit mentioned above will be described below with reference to the drawings.

FIG. 4 shows a block diagram of a conventional bus arbitration circuit. 41 is a bus use request signal, 42 is a priority determination circuit, 43 is a drive circuit, 44 is an arbitration participation signal, 45 is an encoder, 46 is a decoder, 47 is an arbitration signal, 48 is a signal selection circuit, 49 is for arbitration The signal line group 50 is a bus use permission signal.

The operation of the bus arbitration circuit configured as described above will be described below.

When the bus use request signal 41 is generated, the drive circuit 43
outputs the arbitration participation signal 44 to one signal line in the arbitration signal line group 49 according to the priority according to the signal from the priority determination circuit 42. For example, when there are eight modules using the bus, the arbitration signal line group 49 consists of 16 lines in total, 8 lines for arbitration participation signals and 8 lines for arbitration signals. The eight arbitration participation signals 44 are encoded by an encoder 45, and this code, which in this case is a 3-bit code, is transmitted to a decoder 46 and decoded into eight arbitration signals 47. Only one of the eight arbitration signals is allowed to use the bus. The signal selection circuit 48 inputs the arbitration signal 47 from the signal line in the arbitration signal line group 49 according to the priority according to the signal from the priority determination circuit 42, and inputs the bus use permission signal 50 if the bus use is permitted. occurs.

Problems to be Solved by the Invention However, the above configuration has a problem in that the circuit configuration is complicated and the time required for bus arbitration is long.

In view of the above problems, the present invention provides a bus arbitration circuit that has a simple configuration and is capable of high-speed processing.

Means for Solving the Problems In order to solve the above problems, the bus arbitration circuit of the present invention has the following features:
It includes a group of arbitration signal lines, a recognition signal generation circuit, an open collector output circuit, and a comparator.

Function: With the above-described configuration, the present invention can perform bus arbitration at high speed with a simple circuit due to the characteristics of the open collector output.

Embodiment Hereinafter, a bus arbitration circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a bus arbitration circuit in an embodiment of the present invention.

In FIG. 1, 11 is a bus use request signal, 12 is a recognition signal generation circuit, 13 is an open collector output circuit, and 14 is a recognition signal generation circuit.
1 is a comparator, 15 is a group of arbitration signal lines, and 16 is a bus use permission signal.

The operation of the bus arbitration circuit configured as described above will be explained using FIGS. 1, 2, and 3.

When the bus use request signal 11 is input, all modules with the highest priority will receive a low level signal, and as the priority goes down, a high level signal will be sent, depending on the priority of using the bus as shown in Figure 2. The recognition signal generation circuit 12 generates a signal group that increases by one.

0m means an electrically low level signal, and "l" means an electrically high level signal.

The arbitration signal line group 15 is composed of signal lines corresponding to the number of modules that use the bus. The open collector output circuit 13 outputs the recognition signal generated by the recognition signal generation circuit 12 to the arbitration signal line group 15.

When a plurality of modules make bus usage requests, the output to the arbitration signal line group 15 is an open collector, so if a high level signal and a low level signal collide, the colliding signal becomes low level. Therefore, the comparator 14 of the module with the highest priority among the modules making a bus use request outputs a bus use permission signal when the signal generated by the recognition signal generation circuit 12 and the signal on the arbitration signal line group 15 become equal. Outputs 16.

For example, a case where there are five modules using a bus will be explained using FIG. 3. At this time, there are five arbitration signal line groups. The priorities range from 1 to 5, with 1 being the highest. If the recognition signal “00001” of priority level 2 and the recognition signal “00111” of priority level 4 collide on the arbitration signal line group, the output of the recognition signal to the arbitration signal line group is an open collector. The recognition signal on the signal line group becomes "ooooo" and in a module with priority 4, the recognition signal with a low priority changes on the arbitration signal line group, so when compared with the comparator, they are not equal. .

Therefore, no bus use permission signal is output from the comparator. In the priority level 2 module, the high priority recognition signal does not change even on the arbitration signal line group, so when compared by the comparator, it matches its own recognition signal. Therefore, the comparator outputs a bus use permission signal. This example describes the case where there are five modules using the bus, and bus arbitration can be performed in the same way even if the number of modules using the bus increases.

Effects of the Invention According to the present invention, bus arbitration can be performed at high speed using the circuit configuration as described above.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bus arbitration circuit according to an embodiment of the present invention, FIGS. 2 and 3 are relationship diagrams between priorities and recognition signals according to an embodiment of the present invention, and FIG. 4 is a block diagram of a bus arbitration circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of an arbitration circuit. 11... Bus use request signal, 12...
Recognition signal generation circuit, 13...Open collector output circuit, 14...Comparator, 15...
Arbitration signal line group, 16...Bus use permission signal

Claims (1)

[Claims] A bus arbitration circuit that determines which module uses a bus that connects a computer system, and includes a group of arbitration signal lines for outputting signals for arbitration, and a group of arbitration signal lines for outputting signals for arbitration, and a group of arbitration signal lines for outputting signals for arbitration, and a group of arbitration signal lines for outputting signals for arbitration, and a group of arbitration signal lines for outputting signals for arbitration. A recognition signal generation circuit generates a signal group in which all high-level modules are electrically low-level signals, and as the priority decreases, electrically high-level signals increase by one, and the signals generated by the recognition signal generation circuit are an open collector output circuit that outputs to the arbitration signal line group; and a comparator that compares the recognition signal on the arbitration signal line group with the recognition signal generated by the recognition signal generation circuit and outputs a bus use permission signal. A bus arbitration circuit comprising: