JPS6322088B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to sample value decimation filters.

Since the hardware of the digital filter has a large portion occupied by multipliers, it is required to reduce the amount of multiplication per unit time. Traditionally, non-recursive digital filters (hereinafter referred to as NRFs) have been used to implement sampling rate conversion and narrowband signal filtering.
It is abbreviated as. ) was used. The reason for this is explained below.

Compared to a recurrent digital filter (hereinafter abbreviated as RF), NRF requires a larger number of orders to obtain a filter with the same characteristics, although NRF can be operated at a low sampling rate. On the other hand, RF must be operated at a high sampling rate, and when comparing the amount of multiplication per unit time, NRF has the advantage of being smaller.

However, for example, delta modulated signals and PCM
Considering mutual conversion with the signal, the filter characteristics are quite severe (in-band ripple: ±0.2 dB,
Out-of-band attenuation: about 40 dB or more) is required, so implementing it with NRF as in the past requires a large number of filter orders, which has the disadvantage of increasing hardware scale.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a sample value thinning filter that requires fewer multiplications per unit time than the conventional filter and therefore requires a smaller hardware scale.

Another object of the present invention is to provide a sample value thinning filter suitable for time division multiplex processing.

As mentioned earlier, RF needs to operate at a high sampling rate, so although the order is smaller than NRF, the amount of multiplication per unit time is large. However, the transfer relationship H(Z) as shown in equation (1)
If configured with an RF that has a It is possible to make it smaller.

H(Z)=a ₀ Z ⁰ +a ₁ Z ^-1 +a ₂ Z ^-2 +...+a _n Z ^-m /1+b ₁ Z
^-K ＋b ₂ Z ^-2K ＋…＋b _o Z ^-n

Claims (1)

[Claims] 1 Input K l (where l is a positive integer) channel time-division multiplexed signals with a sampling frequency K·fs (where K is an integer greater than or equal to 2), and select each of the K l-channel time-division multiplexed signals in a time-division manner. K sets of numerator coefficient multipliers each including a plurality of multipliers for receiving the outputs of the K selection circuits and multiplying them by predetermined numerator coefficients; and a delay element. A delay/addition block group consisting of a plurality of delay/addition blocks each consisting of an adder that receives the outputs of the K sets of numerator coefficient multiplier groups, and a delay/addition block group in which a plurality of delay/addition blocks are connected in cascade, and a predetermined delay/addition block group that receives the final output of the delay/addition block group a plurality of denominator coefficient multipliers for multiplying denominator coefficients, the i-th ( i is a positive integer).
The outputs of a plurality of multipliers for multiplying by the denominator coefficient are separated by K from each other. A time division multiplexed signal of K and L channels having a sampling frequency fs is obtained at the final output of the group of delay and addition blocks. sample value thinning filter.