JPS6320047B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to sample value interpolation filters.

A large portion of the hardware of a digital filter is occupied by a multiplier, and a reduction in the amount of multiplication per unit time is required. Conventionally, a non-recursive digital filter (hereinafter abbreviated as NRF) has been used to implement sample rate conversion and narrowband signal filtering. The reason for this is explained below.

NRF is a recursive digital filter (RF
It is abbreviated as. ), but NRF can be operated at a low sampling rate, whereas RF must be operated at a high sampling rate. This is because NRF has the advantage of being smaller when comparing the amount of multiplication per unit time.

However, when considering mutual conversion between a delta modulation signal and a PCM signal, for example, the filter characteristics are quite severe (in-band ripple: ±
0.2 dB, out-of-band attenuation: about 40 dB or more), so in order to implement it with NRF as in the past, it required a large number of filter orders and the hardware scale increased.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a sample value interpolation filter that requires fewer multiplications per unit time than the conventional filter and therefore requires a smaller hardware scale.

Another object of the present invention is to provide a sample value interpolation filter suitable for time division multiplexing.

As mentioned earlier, RF needs to operate at a high sample rate, so although the order is smaller than NRF, the amount of multiplication per unit time is large. However, it has a transfer function H(Z) as shown in equation (1).
If configured with RF, it is possible to directly reflect the reduction or increase in sampling rate in reducing the amount of multiplication.
Advantages of NRF and RF useful for reducing filter order
It has the following advantages, and it is possible to reduce the hardware scale.

H(Z)=a ₀ Z ⁰ +a ₁ Z ^-1 +a ₂ Z ^-2 +...+a _n Z ^-m /1+b ₁ Z ^-K
+b ₂ Z ^-2

Claims (1)

[Claims] 1 l of sampling frequency fs (l is a positive integer)
a denominator coefficient comprising an input stage adder receiving a channel time division multiplexed signal as input, a delay element with a tap receiving the output signal of the input stage adder, a plurality of multipliers and an adder receiving the output signals thereof; A numerator coefficient multiplication block K consisting of a multiplication block, a plurality of multipliers, and an adder that receives their output signals.
(where K is an integer of 2 or more) and the output signal of the adder of the numerator coefficient multiplication block of the K set are both input, and each selects one of the K input signals in a time-sharing manner. circuit, configured so that the amount of delay between adjacent taps of the delay element with taps is the same, and at the same time assigns a number to each tap output sequentially starting from 1, and at the same time assigns a number to the input of the delay element with taps.
When the tap output is the K.sup.th tap output, each of the plurality of multipliers in the denominator coefficient multiplication block is the K.sub.ith tap output (where i=1, 2, 3, etc.) of the tap delay element.
While receiving the signal of the tap output, the output signal of the adder in the denominator coefficient multiplication block is input to the input stage adder, and the K sets of numerator coefficient multiplication blocks are numbered 1, 2, ..., K. kth when
(However, the plurality of multipliers in the numerator coefficient multiplication block of k=1, 2, ..., K) are respectively configured to output the {K(i-1)+k-1}th tap output of the delay element with taps. A sample value interpolation filter, characterized in that it is configured to receive a signal, and is configured to obtain l-channel time-division multiplexed signals each having a sampling frequency of K·fs at the outputs of the K selection circuits.