JPS63220567A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To control the value of gamma by using a bias of a substrate by a method wherein a carrier in a gate region is made to flow to the substrate through a buried layer and its amount is controlled by a potential of the substrate. CONSTITUTION:An SIPT is an n-channel SIPT where an n<+> region 21 is used as a source, n<+> regions 22 are used as drains, p<+> regions 23 are used as gates and an n<-> region 24 is used as a channel region; it is formed on p<+>/p<-> substrates 25, 26. The n<+> regions 22 are formed in such a way that they are not only the drains of the n-channel SIPT but also function as the gates of a p-channel static induction transistor (a p-channel SIT) where the p<+> regions are used as sources and the p<+> substrate 26 is used as a drain. That is to say, channels 28 between the n<+> regions 22 are depleted by a diffusion potential of the n<+> regions 22; the amount of its potential is controlled by potentials of the n<+> regions 22 and the p<+> substrate 26 in an electrostatic induction manner. By this setup, it is possible to change the value of gamma by using a bias voltage of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device, and more specifically, to a solid-state imaging device with excellent weak light detection sensitivity, in which the value of γ can be controlled by substrate bias. This is what we provide.

In addition to applications ranging from home video cameras to television cameras for broadcast stations, it can also be applied to video cameras for astronomical observation and still cameras that take advantage of its high sensitivity.

[Conventional technology]

Static Induc phototransistor
tionPhototranSister Below SIP
It's called T. ) Two-dimensional solid-state imaging devices based on the Ga1 accumulation method have been proposed and prototyped in various structures. Among these, a pixel can be constructed using 5IPT which has excellent weak light detection sensitivity in a structure in which all three main electrodes of the SIPT constituting the pixel are connected to either the address line or the signal readout line. An example of the cross-sectional structure of one pixel of this structure is shown in the fourth section.
As shown in the figure.

The conventional technique will be explained with reference to FIG.

5IPT of the structure shown in Fig. 4 is n+ region 41.42
In the following explanation, we will take as an example the upright movement using the 4th hand as the source.

Figure 4 shows the cross-sectional structure of one pixel, or one pixel is one 5
It consists of an iPT and a gate capacitor. 5IPT has the n+ region 41 as the source, the n+ region 42 as the drain, and the p″
n with region 43 as a gate and n-region 44 as a channel
Channel 5IPT. A MOS capacitor is formed on the p+ agate 3 by a transparent insulator 43' such as 5 iOz and a transparent electrode 48 such as polysilicon, and serves as the aforementioned gate capacitor. This 5
The IPT is formed by forming an n+ region 42 on a p-type S1 substrate 45, and then epitaxially growing an n layer, which becomes an n- region 44. A region 410 is a region for pixel separation,
Separates adjacent pixels. In this example, a U-groove formed by etching is oxidized to form a SiO2 film, and then polysilicon is deposited.

A drain 42 embedded in the substrate is common to pixels in a direction perpendicular to the plane of the paper. A p+ region 45l separates this buried drain 42.

In this example, the buried drain 42 has an electrode 42' separated from the substrate surface by an n+ region 42/j.

42/ is a high conductivity material such as kl-5i to reduce the resistance of the buried drain (buried line). The source region 41 has an electrode 49 made of polysilicon or the like.
Is the source line perpendicular to the drain 42 taken? This is connected. The gate 43 of 5IPT is connected to the gate address line through a gate capacitor. gate 43
The electrode of the upper MOS capacitor is connected to the gate address line with the same material 48. 48' is kl-8
A high conductivity material such as i reduces the resistance of the gate address line. The gate address line is formed to be perpendicular to the signal readout line (either the buried line or the source line).

[Problem that the invention seeks to solve]

The two-dimensional solid-state imaging device configured with the above structure is 5IP
It took advantage of the inherent characteristics of T-C, such as low noise, high light sensitivity, and high speed, and had features such as excellent weak light detection sensitivity, high speed, and large capacity. One way to change the value of γ, which is one of the photoelectric conversion characteristics of this two-dimensional solid-state imaging device, is to change the value of the pulse applied to the gate address line at the time of gate address and the value at time of gate refresh. However, in this method, since the readout circuits are integrated on the same chip, the readout circuits become complicated, which poses a practical problem.

Means for Solving Problem C] In order to solve the above-mentioned problems, the present invention provides a structure in which the value of γ can be changed by changing the bias voltage of the substrate.

The operating principle of the solid-state imaging device of the present invention will be explained using FIG.

Figure 2 (al) shows a schematic cross-sectional structure of 5IPT constituting one pixel. Figure 2 (b) is Fat and A-
Band diagrams along A' and BB' are shown superimposed.

The royal movement will be explained below.

The 5IPT is an n-channel 5IPT in which the n+ region 21 is the 7-s, the n+ region 22 is the drain, the p+ region 23 is the gate, and the n- region 24 is the channel region. ) is formed on.

Although the p+ regions 23 are depicted as being separated here, they are electrically connected to each other. Similarly, n+ regions 22 are also electrically connected to each other. The n+ region 22 not only serves as the drain of the n-channel 5IPT, but also serves as the gate of a p-channel static induction transistor (hereinafter referred to as p-channel SIT) having the p+ region 23 as the source and the p+ substrate 26 as the drain. It is formed. That is, the channel 28 between the n'' regions 22 is depleted by the diffusion potential of the n++ region 22, and the potential height is controlled by electrostatic induction by the potential of the n++ region 22 and the p'' substrate 26. .

The time from when one pixel is read out to when the next pixel is read out is called optical integration time. During this optical integration time, the potential VSL of the source 21 and the potential VBL of the drain 22
; i o, the resistive gate 23 is at a higher potential than the potential Lj- which can be obtained in thermal equilibrium due to gate refreshing. p→A negative bias Vsub is applied to the substrate 26. At this time, the output structure diagram along lines AA' and BB' is as shown in FIG. 2(b). Ecx in the figure (X =” + G + G” + D +
D'', 5Llb) indicates the energy level of the conduction band (which is applied to X), and Evx indicates the energy level of the valence band. The lowest point, D is the potential of the drain 22, and DI' is the highest potential of the channel 28. Energy h is applied to this pixel from the surface.
When light of ν is incident (hν is larger than the forbidden band energy), carriers are excited in the channel 24 by this light, and the electrons (in the figure) are moved by the strong electric field in the channel. It flows to the drain 22, and the hole (○ in the figure) flows to the gate I23. Since the gate 23 is isolated from the outside by the gate capacitor CG, holes due to photoexcitation are directly accumulated in the p'' gate 23, lowering the potential of the gate. So, was it held inside the gate by a high potential barrier?
In the structure of the present invention, the potential for holes in channel 28 is lower than the potential for holes in n''-region 22. Therefore, the holes in p+ agate 3 flow through channel 28 to p++ plate 26.

The amount of holes flowing to the p++ plate 2G with is channel 2
8, or as mentioned above, this potential is also controlled by the potential of p→substrate 26.

By changing the bias voltage Vsub to the closed substrate 26, the potential height of the channel 28 for holes is controlled, and the accumulation of holes in the p+ agate 3 due to photoexcitation is controlled. The difference in the accumulation of holes in the p+ge]·23 appears as a difference in the value of γ of the photoelectric conversion characteristic. Therefore, the value of γ is controlled by the value of the substrate.

In the second explanation, we have explained the case of n-channel 5IPT or upright operation.
During the inverted operation using the + region 22 as the source, the energy node diagram in the optical integration time is the same as that shown in FIG. 2(b), and the operation is also the same.

When the structure of one pixel described above is expressed in circuit terms, it is shown in Figure 3 (a
), (b). fa) shows when the 5IPT is in an upright position, and (b) shows when the 5IPT is in an inverted position. 5r
PT3], gate capacitor 32, and p-channel 5I
It consists of T33. fa) will be explained. 34 is 5
35 is the drain of 5lPT31 and the gate of 5IT33, and 36 is the gate of 5IPT3] and the source of 5IT33. 37 is SIT
The drain is the substrate. 36 is gate capacitor 3
2 to the gate terminal 38. In fbl, 34' is the drain of 5IPT31, 35/ or 5IP
It serves as the source of T31 and the gate of 5IT32.

The band diagram along the in is shown. Below, the royal movement will be explained in the same way.

Static Induction Holo-Transtor (SIPT).

Figure 2 (Similar to al, n-channel 5IPT with n++ region 21 as source, n region 22' as drain, p++ region 23 as gate, and n- region 24 as channel region -1)"/p-S i Board (25 or p-126 is ■)''
)”-. p″-region 23 is electrically L
1 is connected to 1. The n region 22' is an n channel S
I l') Not the scale that is the drain of T, but p4
The region 23 is the emitter and the p+ root plate 26 is the collector.
) +1 +) It is formed to function as the base of a hyperpolar transistor (hereinafter referred to as BPT). In other words, the thickness and impurity density of the n-region are appropriately designed.

During the optical integration time, the source 21 potential VSL and the drain 2
Assume that the potential VBL of 2 is 0<, the p+ agate 3 is at a potential higher than the built-in potential between the source and gate immediately after gate refresh. A negative bias Vsub is applied to the p+ substrate 26i. At this time, the band diagram along the line shown by c-c' becomes (di. Light with energy hν is incident on this pixel from the surface, and this light causes channel 24
When carriers are excited in this case, electrons (in the figure) flow to the drain 22' due to the strong electric field in the channel, and holes, ○ in the figure, flow to the gate 23'.
flows to Since the gate 23 is isolated from the outside by the gate capacitor cG, holes caused by photoexcitation are directly accumulated in the p''-gate 23, lowering the potential of the gate.

Holes accumulated in the resistive gate are retained within the gate by a high potential barrier. When the holes due to photoexcitation 1ζ are accumulated in the p+ agate 3, the potential of the gate becomes lower.The situation at this time is shown by the dashed line in Fig. 2 (di). The holes flow into the n region 22!, which has a low potential relative to the hole l.The amount of holes flowing is determined by the n base region 22' due to the p+substrate bias.
is controlled by varying the width of the neutral region.

Therefore, as described above, the accumulation of holes due to photoexcitation in the p+ agate 3 is controlled by the bias voltage Vsub of the p+, 2+1 plate 26, and the value of γ is controlled by the substrate bias.

Above, the case where the n-channel 5IPT is operated in an upright position has been described, and the case where the n-channel 5IPT is operated in an inverted position will be similarly explained.

If the structure of one pixel explained above is expressed in circuit terms, the third
The result will be as shown in Figures (C) and (C1). (C1 shows when the 5IPT is in upright operation, and (d) shows when it is inverted. 5IPT31, gate capacitor 32, and BPT33
It consists of '. (For C1, 34 is the source of 5IPT31, 35 is the drain of 5IPT31 and B P
At the base of T 33', 36 is the gate of 5IPT31 and the emitter of BPT33/.

37 is the collector of the BPT, which is the substrate. 36 is connected to a gate terminal 38 through a gate capacitor 32. In (d), 34' is the drain of 5IPT37, 3
It is the source of the 5/5 IPT31 and the base of the BPT33'.

[For production]

The solid-state imaging device according to the present invention is constructed of pixels whose γ value can be controlled by substrate bias without sacrificing the inherent characteristics of electrostatic induction phototransistors such as low noise, high photosensitivity, and high speed. From the practical point of view of integrating readout circuits on the same chip, it is very useful to be able to control the γ value by simply changing the substrate bias.

〔Example〕

An embodiment of the solid-state imaging device of the present invention is shown in FIG. Although a case will be described in which a Si substrate is used, other semiconductors may of course be used.

FIG. 1 shows the cross-sectional structure of one pixel. One pixel consists of an n-channel S I PT, a gate capacitor, and a p-channel SIT.

First, Figure 1 (al) will be explained. Hereinafter, 5IPT is assumed to be in upright operation. 5IPT is formed with n+ region 1 as a source, n+ region 2 as a drain, p+ region 3 as a gate, and n- region 4 as a channel region. ing.

Although the n+ regions 2 are drawn separately in the figure, they are electrically common. Further, the drain region 2 has an electrode 21 extending from the substrate surface by an n+ region 2//. The electrode 2I may be made of a material with high conductivity, such as Al-5i. The drain region 2 is common between pixels adjacent to each other in the direction perpendicular to the plane of the paper, and is an embedded line. The electrode 21 also serves to reduce the electrical resistance of this buried line. Embedded line 2
The left and right adjacent pixels are separated by a p4 region 5 rt . This S I P T is ]) I-/p-
n″ regions 2 and n″ on the Si substrate (5 p+, 6 p)
- Region 5 r/ is formed by ion implantation or the like, and then an n layer, which will become channel region 4, is epitaxially grown. Further, the n''- region 2 is a p-channel SIT with the p+ region 3 as the source and the p'' substrate 5 as the]/rain.
It is formed to act as a gate. As mentioned above, the value of γ is controlled by the bias voltage applied to the p9-substrate 5.

The source 1 of the 5IPT is connected to an electrode 9 by a transparent electrode layer such as polysilicon and guided to a source line.

p4-gate 3 is a transparent insulator 3 such as SiO2
MOS by / and a transparent material 8 such as polysilicon.
A capacitor is formed and becomes a gate capacitor. Furthermore, the transparent material 8 is guided to the gate address line. 81 is a high conductivity material such as Ap-3i,
The resistance of the gate address line is reduced.

Region 10 is a region for pixel separation, and separates adjacent pixels. Region 10 is formed by oxidizing a U-groove formed by etching to form a SiO2 film, and then depositing non-doped polysilicon. The device surface is protected by a transparent film 7 such as SiO2 or PSG.

When light enters this pixel from the surface and carriers are excited in the channel 4, holes are accumulated in the p+ agate due to the strong electric field in the channel. Is n+ region 2 the gate of p-channel SIT?
The potential for holes between n″− region 2 is p+
It is controlled electrostatically inductively by the potential of the substrate 5. Therefore, the pole of the p'' gate 13 passes through the gap between the n+ regions 2 and the p+
It flows to the substrate 5. Therefore, as mentioned above, it can be controlled by the value of γ or the bias to the substrate.

In the following description of another embodiment, the areas labeled with the same numbers as in (a) have the same functions as those described in (a).

FIG. 1 fb) shows another embodiment. The difference from the embodiment shown in (a,) is that the n+ region 2'' is not connected to the n+ region 1j! p channel S
The potential height of the IT channel is controlled by the potential of the p+ substrate 5. Furthermore, when reading, 5IP
Electrons injected from source 1 of T are transferred from n+ region 2 to n+
In other words, the embodiment of FIG. 1(b) in which the n+ region 2" is not connected to the 1)+ region 2 can perform the same operation as the embodiment of FIG. 1(a).

Another embodiment is shown in FIG. 1. The difference from the embodiment shown in FIG. In this example, p substrate 5
A depletion layer is formed by the diffusion potential of 1 and n+ region 2, and the first
The operation is similar to the embodiment shown in Figure fa).

FIG. 1 (di indicates another embodiment. Similar to fbl, n+
Region 2 is not connected to n+ region 2 rr , and the operation mechanism is the same as in (a).

FIG. 1fe) shows another embodiment. In this example,
Is there any punching-through part provided inside the n″゛゛ area?
It is not in contact with L. The p+ agate pole passes between the n″- region 2, the pixel isolation region 10, and the n+ region 2, and
+ flows to area 5I. In other words, the pixel isolation region 10 and n
A channel is formed between the + region 2 and the hole potential height of this channel is controlled by electrostatic induction by the potential of the 1 region 2 and the p+ substrate potential. Therefore, even in the embodiment of FIG. 1(e) in which part of the n+ region 2 is not punched through, the value of γ is controlled by the bias applied to the I and L plates.

FIG. 1 (The phrase indicates another example. (In the structure shown in el, the n+ region 2 is not electroded by the n+ region 2 Li , but in this example as well, similar to (b)) , the same operation as (e) can be performed.

FIG. 1(g) shows another embodiment. This is a structure similar to the one shown in FIG. 1 made on a p-substrate 51, and the effect of substrate bias is small or can operate in the same way as el.

FIG. 1 (hl shows another embodiment. This is a structure shown in U+ made on a p-type substrate 51, and although the effect of substrate bias is small (it can operate in the same way as fl).

FIG. 1 (il+,;h, shows another example. This is (a
The pixel isolation region 10 in the structure shown in FIG. 1 is replaced by a p+ region 11, and the operation is the same as the embodiment shown in FIG.

Figure 1 (jilt) shows another example. In this structure, the n+ region 2 is not electroded by the n+ region 2 tr in the structure shown in ti+, and as in (b), (]) and r- intercropping is possible.Furthermore, in this example, holes in p+ agate can be extracted by using a channel between n+ region 2 and n+ region 2 rl.

Figure 1 + and +1) show other embodiments, in which the structures shown in (1) and (j) are made on a p-substrate, respectively, and similar operations are possible.

FIG. 1: A pixel isolation region 10 having the structure shown in FIG.
The same operation can be achieved by replacing the p+ region 11 with the p+ region 11.

FIG. 1(0) shows another embodiment. The difference from the embodiment shown in fa+ is the n area 2''.The n area 2'' is:
B where the p medium region 3 is the emitter 5p + the substrate 5 is the lefter
It is designed to be the base of PT. As mentioned above, the p″ gate 3 hole passes through the n region 2I″′ to the p″ gate 3 hole.
The hole passes through to the + substrate 5, but the flow of this hole is to the p+ substrate 5.
Therefore, the value of γ can be changed by changing the substrate bias.

FIG. 1(p) shows another embodiment. This is a structure shown in (0) in which no electrode is provided by the n region 2〆l/or the n+ region 2tt, and the same operation as in (0) can be performed.

In FIG. 1(q), (rl indicates another example, or (0), respectively, an fpl device is fabricated on a p-substrate 51, and the n-region 2 is
It is made so that the width of m can be changed, (0), f
Operates similarly to pl.

FIG. 1 (Sl, +1+ indicates another embodiment;
0 is replaced by p+ region 11, and the operation is the same as (0) and (q), respectively.

In the embodiment described above, only a single channel is used, but a multi-channel version is also possible. Also, the conductivity type is opposite in all regions #, r f)
The operating method of this solid-state imaging device is
An example of how to configure a circuit will be explained. It can be operated with conventional circuit configurations and readout methods, except that the value of r can be controlled by substrate bias.

The configuration of the two-dimensional solid-state imaging device will now be described using FIG. 5(a). p-channel SIT is omitted.

One of the nxm pixels arranged in a two-dimensional matrix, Cij, is composed of one erecting 5IPT and a gate capacitor. The source of 5IPT of this pixel Cij is connected to the signal readout line SLi, the dedicated drain is connected to the buried fin BL4, and the gate is connected to the vertical address line GLj through the gate capacitor. BLj and GLj are parallel and perpendicular to SLi.

The signal readout line S L i l ;1 is grounded through the reset transistors Q and R, and the gates of QR are all made common and a reset pulse 〆R is applied. The square block SLi is connected to a switch transistor Qs through a transfer transistor QT. All QT gates are common and transfer pulse OT
is applied. A suitable capacitor CT is provided at the connection between QT and Qs, and Q3 is further grounded by a suitable load resistor RL common to all Qs, and the point where this load resistor is connected to all Qs is the output. End j″-Vo11
It becomes t. Water is led to the 'J'-l- of the switch transistor Qs by the shift register 52, and read out.
Pulse 〆S is applied. The buried line BLi is connected to the power supply VD through the buried line selection I and transistor QB.
Connected to D. The gate of Ql( is connected to the vertical address line GL, and GL4 is the vertical shift register 5.
1, and a vertical address pulse OG is applied.

FIG. 5(b) shows a timing chart of read pulses.

The vertical shift register is vertical at1/Subarus〆G0,・
. , χGm are sequentially output. In FIG. 5(b), yG and <Oc4++ are shown.

At time j, , turn on the transfer pulse 〆T, l
・After transfer transistor QT becomes conductive ・At time 12, recess t is activated by recess
・L・The Shinkyu readout line is C through Runstar QR.
Together with -r, it becomes a ground potential. At time t3, the vertical address pulse i64 enters, and each pixel C++, .
to charge. At time t4, simultaneously with flr, the optical information of βG, cut, C+j, . . . , CnJ is stored in the respective CTs.

After 〆T expires, the horizontal shift register generates read pulses ys1, .
The outputs of Ci j, . . . and Cnl are sequentially discharged through ■. It is output as a potential change of uj. In this way, by time t8, when the optical information of the horizontal column of CIJ, . . . , Cnj has been outputted, next
→A similar procedure is repeated in order to read out the optical information of l.

In Fig. 5(a), QR-QT, QB-QS
These are all MOS transistors, but do not have to be transistors, ST, bipolar transistors, or JFETs.
etc.

〔Effect of the invention〕

The solid-state imaging device of the present invention has a part of the nl buried drain in a punch-through state, and the ease of accumulating holes due to photoexcitation of the p+ agate of 5IPT is controlled by the bias of the p+ substrate, thereby improving the photoelectric conversion characteristics. The value of γ is controlled.

Therefore, in addition to the inherent characteristics of 5IPT such as low noise, high photosensitivity, and high speed, it is possible to provide a solid-state imaging device in which the value of γ can be easily controlled.

FIG. 6 is a diagram for showing the effects of the invention, and shows an example of photoelectric conversion characteristics when a device having the structure of FIG. 1 (nl) is operated in the method shown in FIG. 5.

The dimensions of one pixel are 85μ×65μ, and it has two channels. Power supply voltage V, D=2V, load resistance Rl-=11(
Ω, optical integration time T I-r = 10 mS, wavelength 6
55 nm (red) light is irradiated, the horizontal axis shows the incident light hIPI Ctt W//J2), and the vertical axis shows the difference in output voltage Voni from the dark state ΔvoutCmV]. It is clearly seen that γ can be changed from 0.42 to 5.7 by changing the substrate bias V (5ul) from OV to 15cm. In other words, 5IP due to substrate bias
This shows that the amount of the pole accumulated in the p+ gate of T injected into the channel (di→ channel of p-channel SIT) is controlled. This means that in areas where the amount of incident light is weak, increasing the γ value will reduce the sensitivity to weak light but will increase the contrast of the image, and when there is strong incident light, it will effectively miss the poles that cannot be accumulated in p+ agate. It can also happen. In other words, it is possible to suppress blooming, which occurs when carriers generated when there is strong incident light flow out to adjacent pixels.

[Brief explanation of the drawing]

Claims (3)

[Claims] (1) A static induction transistor formed vertically on a substrate of a first conductivity type, with a buried layer of a second conductivity type as one of the main electrodes, and a gate region of the first static induction transistor. A solid-state imaging device in which one pixel is formed by a MOS capacitor provided in the solid-state imaging device, characterized in that carriers in the gate region can flow to the substrate through at least a portion of the buried layer, and the amount thereof is controlled by the potential of the substrate. A solid-state imaging device. (2) The solid-state imaging device according to claim 1, wherein in the solid-state imaging device, the value of γ of the photoelectric conversion characteristic can be controlled by a bias voltage applied to the substrate. (3) In the solid-state imaging device, the substrate is p^+/
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is a p^-Si substrate.