JPS59108465A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To obtain a sensor having double high resolution and density by dividing a gate region of an electrostatic induction transistor into two, attaining electric independence and using the region in common at picture element section. CONSTITUTION:A source 13 is diffused on an upper part of a substrate 12 having a transparent electrode 11 via an n<+> layer 10 and a drain 14 is embedded to a position corresponding to a source in the substrate 12. Source wire lines by a signal electrode 15 are sectioned by a separating region 16 by an embedded oxide film and a gate 17 is diffused into an epitaxial layer 18 similarly as the source 13 so as to clip the source 13. Each gate 17 is connected by bridging over a separation region 16 with a readout electrode 19 in the direction orthogonal to the source wire line by the signal electrode 15.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state image sensor that converts an optical image into an electrical signal using a semiconductor, and an object of the present invention is to provide a high-density, high-resolution solid-state image sensor. Instead of image pickup tubes, solid-state image sensors such as COD or MOS type, which are manufactured using semiconductor integrated circuit technology, are being used as nine-frame conversion elements used in digital cameras.Such solid-state image sensors are Features 4. Compact, lightweight, low magnetic force consumption, etc.

However, a major drawback is that the resolution is lower than that of an image pickup tube. That is, the resolution of a solid-state image sensor is determined by the number of pixels, but in a solid-state image sensor such as a 00D or 140S type, the size of one pixel is, for example, lj! ! ! The Y eyes were cut during construction.

Due to the minimum dimension of photolithography, it is limited to approximately 80 μm. In order to obtain a resolution comparable to that of an image pickup tube with this pixel size, a semiconductor substrate approximately 15 square meters is required to arrange 500×500 pixels. However, with current integrated circuit technology, 1. .

It is extremely difficult to fabricate semiconductor substrates of this size without defects, and the number of chips that can be obtained from one wafer also decreases. For this reason, manufacturing a high-resolution solid-state imaging device has the drawback of low yield and high price. I.

In order to solve the above-mentioned problems, it is desirable to have an element structure that allows the size of one pixel to be further reduced. A solid-state image sensor using a static induction transistor (SITI) meets this demand.
E E 'rransacti, ons on,
,.

Electron DeViOeS' (VO/,
26, sx 12, No. 11970-19779
) is proposed. This uses 5ITIs with longitudinal channels as shown in 1d, arrow 2
Charge carriers generated in the substrate 4 through the transparent layer 01 due to the incidence of light from the direction indicated by are accumulated in the drain 5,
When a read pulse is applied to the gate 6, the signal is read out from the id node 8 via the source 7. Furthermore, each SI'I'l
are separated from each other by a separation region 9.

In this way, the solid-state image sensor using SIT has 1. .

Since signal readout is performed in the vertical direction, the size of one pixel can be reduced.

In order to achieve the purpose of roughly equalizing the resolution of a solid-state image sensor using this type of SI'I', the invention is to provide a photo-wake-up conversion area on a semiconductor substrate and a static area for reading out a photoelectrically converted signal. an electric induction transistor, the gate region of the transistor is divided into two to make them functionally independent, and the gate region is divided into two so that these two divided gate regions can be shared when adjacent photoelectric conversion pixel regions are successively selected. The -1° solid-state image sensor is characterized by the arrangement of.

The non-invention will be explained with reference to the drawings.

FIG. 2 is a partially cutaway perspective view showing an embodiment of a solid-state image sensing device according to the present invention using a static induction transistor (SIT), and FIG. FIG.

Substrate 1 provided with transparent electrode 11 via n+ layer 10t-
A source 13 is diffused in the upper part of the substrate 2, and a drain 14 is buried in the substrate at a position corresponding to the source. The source wiring by the No. 1 tung electrode 15 and the 5° line are separated by an isolation region 16 made of a buried oxide film, and the gate 17 is diffused into the epitaxial layer 18 similarly to the source 18 so as to sandwich the source 18. . Each game) 1
7 is connected across the isolation region 16 by a 1° pole 19 extending in a direction perpendicular to the source wiring line with the same number Itth 15. 5° FIG. 4 shows the circuit configuration of the solid-state image sensor shown in FIGS. 2 and 3. 20 is a horizontal shift register that applies a read pulse to the gate, 1° is 1°, and 21 is a vertical shift register that changes the signal current flowing to the source. The theory of operation is 47. Each source is A, B, and O as shown in the diagram (from the top).

-..., and each gate is a, b, O in order from the top.

......

FIG. 5 is a waveform diagram showing successive pulses applied to the gate. In this FIG. 5, since successive pulses are applied to the gates of a and b during the period To, a current flows to the source of A. Next, during period T, successive pulses are applied to the gates of b and ○, so 1. .

Current flows. Similarly, T8. T...
During the period, four currents flow through the sources of O, D, etc., and the signals can be read out sequentially.

As is clear from the above, according to the invention, if one gate is provided for each source, 1° is better. In general, as can be seen by comparing the conventional example shown in FIG. 1 with two gates per source and the present invention shown in FIGS. 2 and 8, according to the present invention, vertical direction The size of one pixel can be reduced to about 14. Therefore, one thing! ... Obtaining twice the resolution is the trick. Note that in the example mentioned above, the gate is connected horizontally and the source is connected vertically, but this also applies if the source is connected horizontally and the gate is connected vertically. Of course it's a good thing, -1 in this case horizontal resolution! f: f can be increased approximately twice.

FIG. 6 is a diagram showing the circuit configuration when Ike's readout method is used, and in this example, for convenience of explanation, each source is arranged in the order of A, B, O, . . . 1 from the top as shown in the figure. It is assumed that the gates are a, b, O, . . . in order from 1 to j.

In this case, each gate is a readout switch 12A, 12B.
, 120. Horizontal shift register 20 via...
is wired to. Each readout switch 12A, 12B
, 120. ...l.

The gate is divided into two systems (1) and (2).

FIG. 7 shows terminals (END), (A), (TS) of the shift register 20 in the example of FIG.

FIG.

In FIG. 71, during the period To, the readout changeover switch 12
Since A is turned on, the read pulses are divided by 7]1 for a and b, and a current flows to the source of A.

During the period T2, since the continuous output changeover switch 120 is on, a read pulse is applied to gates c and d, and a current flows to the source of gate C. Game during the T8 period) 8. Current flows into the source of E due to f.

During the period T4, the continuous output changeover switch 12B is on, so the readout pulses are output to game)b and c.

A current flows through the source of B. Thereafter, a direct current flows to the source of D during a period of °r5, and to the source of F during a period of T6. As described above, each source is A and O.

E, -... B, D, F,... are scanned in the order, so interlaced scanning can be performed b
FIG. 8 is a sectional view showing a modification of FIG. 8, and the same parts as those in FIG. 8 are designated by the same reference numerals. In this example, each drain is surrounded by an insulating layer 30 for isolation between the drains 14.
This is the result of this 4. .

This will reduce crosstalk between adjacent pixels! 11° You can press it even more completely. The above two methods are shown as process steps for achieving this structure.

The first method is to form an oxide insulating layer 80- on a single crystal substrate 12 by a selective oxidation method commonly referred to as the LOOO8 method.

is formed into a convex shape, and then the drain diffusion layer 1 is formed by diffusion.
form 4. ) Then grow an epitaxial layer 18. At this time, the epitaxial layer on the insulating layer is not made into a single crystal, but it can be made into a single crystal by a laser annealing method or the like after that. ] From 1 onwards, the conventional manufacturing method 1 is used.

The second method is to form a buried diffusion layer 14 on the entire surface or selectively on the substrate 12J, and then form an epitaxial layer 18 on it. i: Growth, and then ion implantation of nitrogen ions and nitrogen ions at sub-velocity/high a density.

Then, an insulating layer is formed inside the epitaxial layer.
IIi (commonly referred to as SIMOX method), and then the insulation Jt! which became an ion path by an annealing method. The area above J30? i: Restoration to properties comparable to those of a single crystal region. The manufacturing method thereafter is the same as the conventional manufacturing method. -,.

In the embodiments shown in FIGS. 2.8 and 8, the region in which carriers (holes) generated in the yC'' city 1 conversion region are accumulated is the region in contact with the drain diffusion layer 14 of the low m degree substrate region 12. However, as shown in Fig. 9, the conventional Hooic type S
IT sensors often cause problems.

It is also easy to modify the structure to provide a p++ diffusion layer 31 as a signal charge accumulation layer between the substrate region 12 and the drain diffusion layer 14.

The present invention can also be easily applied to a front-illuminated SET image sensor. The example is shown in the 10th section. .

As shown in the figure. FIG. 10a is a cross-sectional structural diagram, FIG. 10b is a cross-sectional structural diagram taken along the line A-A', FIG. 100 is an example of the matrix array llmbsE for explaining the operation, and FIG. An example of waveforms during successive O and reset operations will be shown tomorrow.

One method of process steps to achieve the structure shown in Figure FILLOA, B is as follows. First, in order to insulate the n-type buried diffusion layer 41 that will become the drain of the SIT on the p-type substrate 40 and the adjacent drains.

After forming p++ buried diffusion layers 42, respectively.

The n-type epitaxial layer 43 is elongated, and an insulating layer 44 is formed within this epitaxial layer. A p+ type agate diffusion layer 45 and an n++ source diffusion layer 46 are respectively formed. Thereafter, a gate electrode 4s and a source diffusion layer 46 are formed on the gate diffusion layer 45 via a thin insulating film 47 using a transparent electrode or a semitransparent polycrystalline silicon layer doped with impurities to increase conductivity. A source electrode 49 is formed in ohmic contact with.

Next, the operation will be explained with reference to FIG. 100. This matrix array configuration of the first ocm is an example applied to so-called interlaced imaging in which the time to capture an incident image is divided into two, and the detected pixel position is shifted by i pixels.

As described in the embodiment of the back-illuminated SIT sensor described above, when the first image (referred to as A frame) is produced one after another, the gate polarization wiring lines 50pa-b, c-d, e
-f, -------.

Then, the shift register 51 for gate scanning selects the gate magnetic pole wiring lines 50 from b-c and d-e when the next second image (referred to as a B frame) is to be output one after another.

Select by matching the gi.

In this case, the drain electrode wiring line 52 is drained.

It is selected by the in-scanning shift register 58 and a high voltage is applied. Here, the photoelectric conversion section has a gate diffusion layer 45 (
(Fig. 1 OA, B) and the depleted region around it, and among the ton-hole pairs generated by the incident light, holes cross the depletion layer... and form a p+ type agate diffusion layer. 45 is accumulated.

As a result, the potential of the gate diffusion layer increases, and when a pulse is applied to the gate pole wiring line 50, the gate electrode 4
At the time of selection induced by the capacitance between the gate diffusion layer 45 and the gate diffusion layer 45, the potential of the gate diffusion layer 145 becomes 4th in proportion to the incident light compared to when there is no incident light. When the drain diffusion layer 41 is selected by this foreshadowing and a high voltage is applied, and the source wiring line 54 is also selected, a drain current related to the above-mentioned incident light flows, and it is connected to the load resistance -
□...It is converted at 55 and read out as a signal voltage.
Since the one-piece diffusion layer 45 is electrically floating, the potential of this diffusion layer is reset only after all the pixels connected to the same gate line are connected (time period T0 in FIG. 10d). G By setting the interval of one gate pulse, the potential change due to the incident light can be reset.

After the successive reading of gate lines (A-frame readout) is completed, the potential is reset and then imaged, and the combination of gate lines is changed as described in item 1j for the gate diffusion layer where signals are being accumulated. Readout similar to No. 1 (B frame successive) is performed.

As explained above in each of the embodiments, according to the present invention, in one direction of the matrix array, the inter-pixel insulation region of the conventional example is eliminated, a source diffusion layer is provided in that region, and these source diffusion layers are Surrounding gate, 1° (11) A gate diffusion layer is divided into two on the structure and electrical connection, and each gate layer divided into two halves can be electrically controlled independently. By sharing the diffusion layer when selecting pixels on both sides, the pixel interval can be equivalently reduced to 1, and an SIT sensor with twice as high density and high resolution can be obtained. Specific application examples include a method of sequentially reading out adjacent pixels to configure it as a double high-density 1sIT sensor, and a method of selecting every other adjacent pixel in the first cycle and using the entire screen as an A frame. Readout 1.1゜As an application to the so-called interlaced readout method, in which every other pixel that is not sold in the second cycle is selected (by shifting the combination of gate regions) and the entire screen is read out as a B frame. There are several possible ways to configure this.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an example of a conventional solid-state image sensor using S-T, FIG. 2 is a partially cutaway perspective view showing a cross section of an example of the solid-state image sensor according to the present invention. (12) Fig. 3 is a cross-sectional view taken along the line lN-1 in Fig. 2, Fig. 4 is a diagram for explaining the operation of Figs. The figure is a waveform diagram showing an example of successive pulses applied to the gate, Figure 6 is a diagram showing the circuit configuration when using a successive readout method different from the reading method shown in Figure 4, and Figure 7 is a diagram showing the circuit configuration for the example of Figure 6. FIG. 8 is a waveform diagram showing an example of successive pulses applied to the gate. FIG. 8 is a sectional view showing a modification of FIG. 3. FIG. 9 is a sectional view showing a partial modification of FIG. 8, FIG. 10a is a sectional view showing an example in which the present invention is applied to a front-illuminated SET image sensor, and FIG. 1o'b is a sectional view of FIG. 10a. A-A
Figure 100 is a diagram for explaining the operation of Figure 1Ua). Figure 10d is a diagram showing the circuit configuration of the IJ rack array.
FIG. 6 is a waveform diagram showing an example of a pulse applied to the gate in FIG. 1...SIT 2...Ge C incident direction 3
...Transparent electrode 4...Substrate 5...Drain 6...Gate? ···sauce
8...Signal electrode 9...Separation region lO・
...N layer 11...Transparent electrode 12...Substrate 13...Source 14...Drain 15
... Signal electrode 16 ... Separation region 17 ...
・'r'-to 18...Epitaxial layer 19...Reading electrode 20...Horizontal shift register 1. . 21... Vertical shift register 80... Insulating layer 31...
...p diffusion layer 40...substrate 41...n+ diffusion layer (drain) 42...p+ diffusion layer 43...n-
Epitaxial layer 44...Insulating layer 45...p+ agate diffusion layer 46...n"y-s relaxation layer I47...
Insulating film 48...ge) + [pole 49...
Source electrode 50...gate magnetic pole wiring line 5
1... Shift register for gate scanning 52... Drain electrode wiring line 58... Shift register for drain scanning
=・1゜54...Source electrode wiring line 55...Load resistance 12A, 12B, 120,...
...Reading selector switch. Patent applicant: Olympus Optical Industry Co., Ltd. Applicant: Jun Nishizawa -1'-w Shin -
N wrath 9 theft 9; ” -(J”Ci ω tun 6

Claims (1)

[Scope of Claims] 1. A magneto-optical conversion region and a static induction transistor for reading out a photoelectrically converted signal are provided on a semiconductor substrate, and the gate region of the static induction transistor is divided into two to conduct electrical conversion. 1, characterized in that the gate regions are arranged so that the two gate regions are made independent and can be shared when successive selections of adjacent photoelectric conversion pixel regions are made. Solid-state image sensor.