JPS63219177A - High-output semiconductor amplifier element - Google Patents

Abstract

PURPOSE:To build a high-output FET by a method wherein an insular source electrode of a via-hole structure is surrounded by a gate electrode, and a drain electrode is provided outside, for an increase in the gate width per unit chip area. CONSTITUTION:When a gate electrode 1 is provided also over a portion 4 of an insular source electrode S of a via-hole structure, the gate width increases without an increase in the chip area. This design results in an increased drain saturation current and in higher output. In a structure designed as such, the chip area may be smaller as compared with other designs handling the same size of drain saturation current. Accordingly, for a signal travelling from an input portion 5 to pass through a portion 1 or from a portion 3 to portion 6, the distance of transmission is shortened and therefore loss is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element structure in an ultra-high frequency region, and particularly to an electrode pattern structure suitable for increasing the output of the element.

[Conventional technology]

The electrode pattern structure of conventional high-output semiconductor devices is [3
0GHz band power synthesis type GaAS FET (1),
J (Proceedings of the 1985 National Conference of the Institute of Electronics and Communication Engineers, Volume 8)
As described in 40), semiconductor devices with island-shaped source electrodes are known in which thermal resistance is reduced by thinning the substrate and source inductance is reduced by forming the source electrode into a via-hole structure. . A conventional electrode pattern structure is shown in FIG.

In addition, for high output, “X-band IW monolithic F
ET Amplifier" (Refer to A109 of the 1985 National Conference of the Optical and Radio Division of the Institute of Electronics and Communication Engineers),
The F
ET amplifier element.

[Problem that the invention seeks to solve]

The above conventional technology does not consider the output power per chip area, and the increase in gate width due to higher output increases the chip area, reduces substrate utilization efficiency, and reduces signal transmission. This results in an increase in line loss and a decrease in power gain due to a synchronization difference between the FET operations in the center and the periphery.

The purpose of the present invention is to increase the gate width per chip area,
The purpose of this invention is to effectively utilize the substrate of a high-output element and to realize high output of the element without causing a decrease in power gain.

[Failure to solve the problem]

The above purpose is to surround an island-shaped source electrode using a via-hole structure with a gate electrode, and provide a drain electrode on the outside thereof, thereby increasing the gate width per unit chip area, thereby increasing the saturation drain current of the FET. By doing so, high output can be achieved.

[Effect]

The output of an FET depends on its drain saturation current, and in order to realize a high output F'ET, it is necessary to obtain a high saturation current. This requires a long gate width.

The operation of the present invention will be explained using FIG. By providing a gate electrode also in the portion 4, the gate width can be increased without increasing the chip area, which increases the drain saturation current and enables higher output.

This effect results in a smaller chip area for the same drain saturation current. Input signal enters from 5,
When passing through 1 and 3, the signal suffers a loss proportional to the distance over which the signal is transmitted, and therefore the power gain decreases. If the area can be reduced, the transmission distance can be shortened, loss can be suppressed, and power gain can be prevented from decreasing.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 is a plan view of an element electrode pattern showing an embodiment of the present invention. 1 is a gate electrode, 2 is a source electrode, 3 is a drain electrode, and the input signal is amplified by 5 and outputted from 6. 4. It becomes possible to increase the number of gate electrodes. In the embodiment shown in FIG. 1, a circular arc shape is used for the source electrode.
The electrode shape may be thin.

According to this embodiment, the three sides of the source electrode are effectively utilized, and the gaps between the source and the gate and drain are kept constant at any position.

〔Effect of the invention〕

According to the invention.

■ The gate width can be made longer with the same chip area, and the drain saturation current can be increased. As a result, higher output is achieved and wafer utilization efficiency is increased.

■ The area of a high-output FET chip can be reduced by about 30% (calculated from the size of the source electrode (100 μm x 60 μm)), which shortens the signal transmission distance and reduces loss there. Since the phase shift can also be reduced, it is possible to suppress a decrease in power gain.

[Brief explanation of drawings]

FIG. 1 is a plan view of an element electrode pattern according to an embodiment of the present invention, and FIG. 2 is a plan view of an element electrode pattern according to the prior art. 1... Gate electrode, 2... Source electrode, 3... Drain electrode, t... Lateral dimension of source electrode, t8...
Vertical dimension of the source electrode. Agent Patent Attorney Masaru Koyo 7', 77゛・7

Claims (1)

[Claims] 1. A high output semiconductor device having an island-shaped source electrode using a via hole structure, characterized in that the source electrode is surrounded by a gate electrode, and a drain electrode is provided outside the gate electrode. Semiconductor amplification element. 2. A high-output semiconductor amplification element according to item 1, wherein the corner of the island-shaped source electrode is curved, and the distance between the source, gate, and drain at the curved portion is constant. .