JPH04186901A - Matching circuit for monolithic ic amplifier - Google Patents

Matching circuit for monolithic ic amplifier

Info

Publication number
JPH04186901A
JPH04186901A JP31694190A JP31694190A JPH04186901A JP H04186901 A JPH04186901 A JP H04186901A JP 31694190 A JP31694190 A JP 31694190A JP 31694190 A JP31694190 A JP 31694190A JP H04186901 A JPH04186901 A JP H04186901A
Authority
JP
Japan
Prior art keywords
matching circuit
input
output
electrode
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31694190A
Other languages
Japanese (ja)
Inventor
Yasuhiro Akiba
秋葉 康弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31694190A priority Critical patent/JPH04186901A/en
Publication of JPH04186901A publication Critical patent/JPH04186901A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Microwave Amplifiers (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To offer the matching circuit whose occupied area is small, and also, which has no coupling of an input and an output by constituting a ground side electrode of a shunt type capacitor provided between an input/output transmission line connected to an amplifying part and a ground electrode of the reverse side of a semiconductor substrate so as to be used as a receiving electrode of a viahole. CONSTITUTION:On both sides of an amplifying part 1, an input matching circuit 2 and an output matching circuit 3 are placed symmetrically. The input matching circuit 2 and the output matching circuit 3 are constituted of a transmission line 4 and a capacitor 10, and a transmission line 5 and a capacitor 10', respectively. The capacitors 10, 10' are connected to each transmission line 4, 5 by the upper electrode 6, and the lower electrode (ground side electrode) 8 combines a receiving electrode of a viahole 9 connected electrically to a ground electrode 11 of the reverse side of a semiconductor substrate. The matching circuits 2, 3 become LC matching circuits. Since the capacitor is formed in the vertical direction in the substrate, a plane occupied area of the capacitor is a contact area with a transmission line of an input and an output, and it scarcely becomes a problem. Also, different from a stub line, the matching circuit scarcely has coupling between the input and output.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マイクロ波モノリシンクIC増幅器の整合回
路に関し、特に10GHz以上の超高周波帯のマイクロ
波モノリシックIC増幅器の整合回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a matching circuit for a microwave monolithic IC amplifier, and particularly to a matching circuit for a microwave monolithic IC amplifier in an ultra-high frequency band of 10 GHz or higher.

〔従来の技術〕[Conventional technology]

従来の整合回路の1例を第2図に示す、ここで12.1
.!はそれぞれ入力・出力整合用のオーブンスタブ線路
である。増幅部1への入力伝送路4゜出力伝送路5との
組合わせで入力整合回路2.出力整合回路3を形成して
いる。ショートスタブ線路を用いることもある。
An example of a conventional matching circuit is shown in FIG. 2, where 12.1
.. ! are oven stub lines for input and output matching, respectively. Input transmission line 4 to amplifier section 1 and output transmission line 5 are combined to form input matching circuit 2. An output matching circuit 3 is formed. Short stub lines may also be used.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来のマイクロ波モノリシ、りIC増幅器では、整
合回路として用いているオープンスタブ線路もしくはシ
ョートスタブ線路の占有面積はチップ面積の50%以上
あり、しかも超高周波帯の増幅器では増幅部の面積を極
力小さく設計するので、スタブ線路では、入出力線路間
の間隔が近づき、そのカップリングにより、周波数特性
が変化するという問題点があった。
In this conventional microwave monolithic IC amplifier, the open stub line or short stub line used as a matching circuit occupies more than 50% of the chip area, and in ultra-high frequency band amplifiers, the area of the amplification section is minimized. Since the stub line is designed to be small, the spacing between the input and output lines becomes close, and this coupling causes a problem in that the frequency characteristics change.

本発明の目的は、上記の事情に鑑み、マイクロ波モノリ
シックIC増幅器の整合回路として、占有面積が小さく
、しかも入出力のカンプリングのない整合回路を提供す
ることにある。
In view of the above circumstances, an object of the present invention is to provide a matching circuit for a microwave monolithic IC amplifier that occupies a small area and is free from input/output compensating.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のマイクロ波モノリシンクIC増幅器の整合回路
は、増幅部に連結される入出力伝送路と。
The matching circuit of the microwave monolithic IC amplifier of the present invention includes an input/output transmission line connected to the amplifier section.

該伝送路と半導体基板裏面の接地電極との間に設けたシ
ャント型キャパシタとからなり、該キャパシタの接地側
電極は、バイアホールの受電極となるように構成されて
いる。
It consists of a shunt type capacitor provided between the transmission line and a ground electrode on the back surface of the semiconductor substrate, and the ground side electrode of the capacitor is configured to serve as a receiving electrode of the via hole.

〔作用〕[Effect]

キャパシタは基板内に垂直方向に形成されるので、キャ
パシタの平面的な占有面積は、入出力の伝送路との接続
面積であり、殆ど問題にならない。
Since the capacitor is formed vertically within the substrate, the planar area occupied by the capacitor is the connection area with the input/output transmission path, and is of little concern.

またこの整合回路はスタブ線路と異なり入出力のカップ
リングは殆どない。
Further, unlike a stub line, this matching circuit has almost no input/output coupling.

〔実施例〕〔Example〕

以下、本発明の一実施例につき説明する。第1図が実施
例の平面図(a)およびA−A縦断面図(blである。
An embodiment of the present invention will be described below. FIG. 1 is a plan view (a) and an A-A vertical cross-sectional view (bl) of the embodiment.

増幅部1の両側に入力整合回路2.出力整合回路3が対
称的に配置される。入力整合回路2は、伝送路4とキャ
パシタ10とから、また出力整合回路3は伝送路5とキ
ャパシタ10′とから構成される。キャパシタ10.1
0’は、上部電極6により各伝送路4,5と接続がとら
れ、また下部電極(接地側電極)8は半導体基板の裏面
の接地電極11と電気的に接続のあるバイアホール9の
受電極を兼ねている。なお、7は誘電体である。
Input matching circuits 2 are provided on both sides of the amplifier section 1. Output matching circuits 3 are arranged symmetrically. The input matching circuit 2 is composed of a transmission line 4 and a capacitor 10, and the output matching circuit 3 is composed of a transmission line 5 and a capacitor 10'. Capacitor 10.1
0' is connected to each transmission line 4, 5 by an upper electrode 6, and a lower electrode (ground side electrode) 8 is a receiving part of a via hole 9 that is electrically connected to a ground electrode 11 on the back side of the semiconductor substrate. Also serves as an electrode. Note that 7 is a dielectric material.

上記整合回路2.3は、LC整合回路となっている。The matching circuit 2.3 is an LC matching circuit.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように、本発明ではLC整合回路の主素
子のキャパシタは、入出力伝送路に対して垂直方向に接
地電極との間に構成されるので、半導体基板の表面面積
に占める占有面積の増大は殆どない。したがって、電力
増幅器としてのチップ面積を従来に対し格段と小さくす
ることができる。また入出力線路は、増幅部に対して対
称的に直線状に延在し、従来のスタブ線路と異なり、相
互の間隔が狭くなる個所が全くないので、線路間のカッ
プリングが生じない。
As explained above, in the present invention, the capacitor, which is the main element of the LC matching circuit, is configured between the ground electrode and the input/output transmission line in a direction perpendicular to the input/output transmission path, so that it occupies an area that occupies the surface area of the semiconductor substrate. There is almost no increase in . Therefore, the chip area as a power amplifier can be made much smaller than in the past. In addition, the input/output lines extend linearly symmetrically with respect to the amplifying section, and unlike conventional stub lines, there are no places where the mutual spacing becomes narrow, so that coupling between the lines does not occur.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の平面図(a)、A−A縦断
面図(blであり、第2図は従来例の平面図である。 1−・−増幅部、 2,3(入力、出力)整合回路、4
.5− (入力、出力)伝送路、 6−上部電極、 7−誘電体、 8−下部電極(接地側電極)、 9−・−バイアホール、 10.10’−−−キャパシタ、 11−・−接地電極。 特許出願人  日本電気株式会社 代理人   弁理士  内原 晋 第1因 第2因
FIG. 1 is a plan view (a) and an A-A vertical cross-sectional view (bl) of an embodiment of the present invention, and FIG. 2 is a plan view of a conventional example. 1--Amplifying section, 2, 3 (input, output) matching circuit, 4
.. 5- (input, output) transmission line, 6- upper electrode, 7- dielectric, 8- lower electrode (ground side electrode), 9-.- via hole, 10.10'-- capacitor, 11-.- Ground electrode. Patent applicant Susumu Uchihara, agent for NEC Corporation Patent attorney 1st cause 2nd cause

Claims (1)

【特許請求の範囲】[Claims]  マイクロ波モノリシックIC増幅器において、増幅部
に連結される入出力伝送路と,該伝送路と半導体基板裏
面の接地電極との間に設けたシャント型キャパシタとか
らなる整合回路であって、該キャパシタの接地側電極は
、バイアホールの受電極となっていることを特徴とする
整合回路。
In a microwave monolithic IC amplifier, a matching circuit consists of an input/output transmission line connected to an amplifying section and a shunt type capacitor provided between the transmission line and a ground electrode on the back surface of a semiconductor substrate, A matching circuit characterized in that the ground side electrode serves as a receiving electrode for a via hole.
JP31694190A 1990-11-21 1990-11-21 Matching circuit for monolithic ic amplifier Pending JPH04186901A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31694190A JPH04186901A (en) 1990-11-21 1990-11-21 Matching circuit for monolithic ic amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31694190A JPH04186901A (en) 1990-11-21 1990-11-21 Matching circuit for monolithic ic amplifier

Publications (1)

Publication Number Publication Date
JPH04186901A true JPH04186901A (en) 1992-07-03

Family

ID=18082651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31694190A Pending JPH04186901A (en) 1990-11-21 1990-11-21 Matching circuit for monolithic ic amplifier

Country Status (1)

Country Link
JP (1) JPH04186901A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5153866B2 (en) * 2008-04-11 2013-02-27 三菱電機株式会社 Power distributor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5153866B2 (en) * 2008-04-11 2013-02-27 三菱電機株式会社 Power distributor

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