JP2001185966A - Microwave power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide loop oscillation stopping technology which has higher efficiency than before and to provide a microwave power amplifier equipped with a small-sized, high-performance, and high-output FET chip which stably operates by efficiently absorbing loop oscillation power generated nearby the FET chip by a resistor. SOLUTION: A high-output power amplifier which uses a multicell-constituted FET chip 1 is provided with comb-shaped slits 16 in a transmission line nearby the FET chip 1 and loaded with the resistor in the slits 16 in the form of a sheet resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for suppressing loop oscillation, and more particularly to providing a technique for suppressing loop oscillation which is more efficient than conventional techniques. The present invention relates to a microwave power amplifier provided with a small, high-performance, and high-output FET chip that efficiently absorbs light and operates stably.

[0002]

2. Description of the Related Art In general, a high-power amplifier used in a microwave band is provided with a plurality of high-power GaAs field-effect transistors (hereinafter referred to as a plurality) used in a microwave band in order to obtain a high output of several W or more. There is known a circuit configuration in which a GaAs FET chip) and an input / output impedance matching circuit are mounted in one package. In order to obtain high output in the microwave band, multi-finger multi-cells are generally used. However, there is a problem that the chip size becomes large, and in the case of one chip, there is a problem in terms of manufacturing or mechanical strength of the chip. Due to problems, the available power is limited. Therefore, to obtain high output in one package,
An amplifier must be composed of a plurality of FET chips.

FIG. 6 is a circuit diagram illustrating a conventional embodiment, and is an equivalent circuit diagram in the case where a high-output amplifier is formed by combining four FET chips 1 in parallel. FIG.
Referring to FIG. 2, the RF signal input from the input terminal 14 is distributed to the respective FET chips 1 via the equivalent input matching circuits 2a, 2b, 2c and 2d, and the RF signal amplified by the respective FET chips 1 is , Equivalent output matching circuits 6a, 6
The power is combined to the output terminal 15 via b, 6c, 6d. Also, the FET chip 1 and the equivalent output matching circuits 6a, 6
Odd mode oscillation (oscillation in which the FET chips 1 on the loop operate in opposite phases) may occur depending on the oscillation conditions in the closed loop circuit composed of b, 6c, and 6d. Thus, by loading the input-side resistor 10 and the output-side resistor 11 in parallel in the loop, the odd-mode oscillating power α between two chips and the odd-mode oscillating power β between four chips are supplied to the input-side resistor 10 and the output. Absorption by the side resistor 11 stabilizes the operation of the amplifier.

The values of the input-side resistor 10 and the output-side resistor 11 loaded in parallel in the loop are such that the input-side excitation loop gain S1 and the output-side excitation loop gain S2 are 1 or less as shown in the following equation. Is set to Since the loop gain S1 of the input side excitation and the loop gain S2 of the output side excitation are attenuated, the odd mode oscillation power does not appear at the output terminal 15 of the amplifier. S1 = Re ｛ΓsΓin｝ <1 S2 = Re ｛ΓlΓout｝ <1 Here, Γs is a reflection coefficient as viewed from the side of the equivalent input matching circuits 2a, 2b, 2c, 2d connected to the unit transistors constituting the amplifier. , Γin are the input reflection coefficients of the unit transistors, and Γl is the equivalent output matching circuits 6a, 6b,
It is assumed that the reflection coefficient is the reflection coefficient as viewed from the side of 6c and 6d, and that Γout is the output reflection coefficient of the unit transistor.

FIG. 7 is a specific configuration diagram illustrating a conventional embodiment, and is an external view in which four FET chips 1 are combined in parallel to form a high-output amplifier in a small package 17. . Referring to FIG. 7, an RF signal input from the input terminal 14 is transmitted through an equivalent input matching circuit 2a, 2b, 2c composed of a transmission line formed on an alumina substrate and a plate capacitor formed on a high dielectric constant substrate. And distributed to each of the FET chips 1. The RF signal amplified by each FET chip 1 is power-combined at an output terminal 15 via equivalent output matching circuits 6a and 6b formed of a transmission line formed on an alumina substrate. The input-side resistor 10 and the output-side resistor 11 are thin-film resistors formed on a dielectric substrate, and constitute equivalent input matching circuits 2a, 2b, and 2c which are arranged oppositely in a closed loop circuit between chips. Are provided between the transmission lines constituting the equivalent output matching circuits 6a and 6b and connected to each transmission line. In FIG. 7, reference numeral 4 denotes a gate terminal, 5 denotes an input side bonding wire, 7 denotes a drain terminal, and 8 denotes an output side bonding wire.

As described above, the conventional high-power amplifier comprises a plurality of FET chips 1 and equivalent output matching circuits 6a, 6b, 6
By loading a resistor in parallel in a closed loop circuit generated between c and 6d, the odd-mode oscillation power is absorbed by the resistor and the operation of the amplifier is stabilized.

In contrast to the conventional high-power amplifier described above, the high-frequency semiconductor amplifier disclosed in Japanese Patent Application Laid-Open No. 9-139,939 has a plurality of FET chips 1 and equivalent input matching circuits 2a, 2b, 2c, 2d-. Equivalent output matching circuit 6
The equivalent input matching circuits 2a, 2b, 2c, 2d are used to suppress not only the loop oscillation occurring in the closed loop circuit generated between a, 6b, 6c, 6d but also the small closed loop circuit generated in the FET chip 1. Or equivalent output matching circuit 6
Each of a, 6b, 6c, and 6d is loaded with a resistor in the form of a sheet resistor embedded in a line near a semiconductor chip.

FIG. 8 is a block diagram for explaining another embodiment of the related art, and shows only a state in the vicinity of one chip. Referring to FIG. 8, the FET chip 1 is connected to the transmission line of the equivalent input matching circuit 2 and the gate terminal 4 of the FET chip 1 via the input side bonding wire 5, and the transmission line of the equivalent output matching circuit 6 is connected to the output side. The drain terminal 7 is connected via the bonding wire 8. Output resistor 11
Are loaded in the form of sheet resistance embedded in the transmission line connected to the FET chip 1 by the equivalent output matching circuit 6.
Thereby, the configuration is such that the odd-mode oscillation powers A and B in one chip generated in the small closed loop circuit near the FET chip 1 can be absorbed. In FIG. 8, reference numeral 14 denotes an input terminal, and 15 denotes an output terminal.

[0009]

However, the prior art has the following problems. First, the first problem is that the resistor works effectively for the odd-mode oscillation power B in one chip having an electrical length corresponding to the peripheral length of the sheet resistor, but the electrical length is longer than the peripheral length of the sheet resistor. The effect cannot be exerted on the odd-mode oscillation power A in one chip having the above. The second problem is that in order to efficiently absorb the loop oscillation power with a resistor, it is necessary to load an appropriate isolation resistor between loops having an electrical length of 波長 wavelength with respect to the loop oscillation frequency. In most cases, in order to obtain a low-loss matching circuit characteristic, the matching circuit near the FET chip 1 is often a wide low-impedance line, and the matching circuit and the FET chip 1 are housed in a small package. And dimensions are limited, so
It is often difficult to secure an electrical length of 波長 wavelength with respect to a small closed loop near the FET chip 1. Therefore, with a conventional resistor embedded in a transmission line,
It is difficult to suppress loop oscillation having a relatively long electrical length.

The present invention has been made in view of the above problems, and has as its object to provide a technique for suppressing loop oscillation which is more efficient than in the past.
An object of the present invention is to provide a microwave power amplifier having a small, high-performance, and high-output FET chip that operates stably by efficiently absorbing loop oscillation power generated in the vicinity of the FET chip with a resistor.

[0011]

The gist of the present invention is to provide a slit having a predetermined peripheral length in a transmission line near a multi-cell FET chip,
A microwave power amplifier has a structure in which a sheet-shaped resistor for preventing loop oscillation is loaded in the slit. The gist of the invention described in claim 2 is that a sheet-shaped resistor for preventing loop oscillation is provided by providing a comb-shaped slit having a predetermined outer peripheral length in a transmission line near a multi-cell FET chip. A microwave power amplifier having a structure loaded in a slit. The gist of the invention described in claim 3 is that a slit of a predetermined shape having a predetermined outer peripheral length is provided in a transmission line near a multi-cell FET chip, and a resistor for preventing loop oscillation is provided in the slit. And a microwave power amplifier characterized by having a structure loaded therein. Claim 4
The gist of the invention described in (1) has a structure in which a comb-shaped slit having a predetermined outer peripheral length is provided in a transmission line near a multi-cell FET chip, and a resistor for preventing loop oscillation is loaded in the slit. A microwave power amplifier is characterized in that: The gist of the invention described in claim 5 is to provide a slit having a predetermined shape, which is loaded with a resistor by sheet resistance and has a predetermined outer peripheral length, in a transmission line near the FET chip to prevent loop oscillation. A microwave power amplifier having a structure. The gist of the invention described in claim 6 is that
A microwave power amplifier having a structure in which a comb-shaped slit having a predetermined outer peripheral length and loaded with a resistor by sheet resistance is provided in a transmission line near an FET chip to prevent loop oscillation. Exists. Also,
The gist of the invention according to claim 7 has a structure in which a resistor of a predetermined shape having a predetermined outer peripheral length and loaded with a resistor for preventing loop oscillation is provided in a transmission line near an FET chip. A microwave power amplifier characterized in that: The gist of the invention described in claim 8 is a structure provided with a comb-shaped slit provided with a resistor for preventing loop oscillation and having a predetermined outer peripheral length in a transmission line near an FET chip. Microwave power amplifier. According to a ninth aspect of the present invention, an outer peripheral length of the slit is set to a size corresponding to a frequency at which isolation between FET chips is best. A microwave power amplifier according to any one of the preceding claims.

[0012]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-cell FE.
In a high output power amplifier using a T chip, a (comb-shaped) slit is provided in a transmission line near an FET chip, and a resistor is loaded in the slit in the form of a sheet resistor. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) An embodiment will be described below with reference to the drawings. FIG. 1 is a specific configuration diagram for explaining the microwave power amplifier according to the first embodiment of the present invention. In FIG. 1, 1 is an FET chip, 2
a, 2b, 2c are equivalent input matching circuits, 4 is a gate terminal,
5 is an input-side bonding wire, 6a and 6b are equivalent output matching circuits, 7 is a drain terminal, 8 is an output-side bonding wire, 10 is an input-side resistor, 11 is an output-side resistor, 14 is an input terminal, and 15 is an output. Terminals, 16 are slits, 17 is a package, and 18 is a thin film sheet resistor in the slit.

In this embodiment, four FET chips 1
Will be described in which a high-output amplifier is configured in a small package by combining the above-described components in parallel.

Referring to FIG. 1, in the present embodiment, an RF signal input from input terminal 14 has a transmission line formed on an alumina substrate and a flat plate capacitor formed on a high dielectric constant substrate. Equivalent input matching circuits 2a, 2
The data is distributed to each of the FET chips 1 via b and 2c. The RF signal amplified by each FET chip 1 is converted to an equivalent output matching circuit 6 having a transmission line formed on an alumina substrate.
The power is synthesized to the output terminal 15 via the terminals a and 6b. The input-side resistor 10 (input-side inter-chip resistor) and the output-side resistor 11 (output-side inter-chip resistor) are thin-film resistors formed on a dielectric substrate, and oppose each other between chips in a closed loop circuit. Input matching circuits 2a,
It is provided in a part between the transmission lines forming the 2b and 2c and a part between the transmission lines forming the equivalent output matching circuits 6a and 6b, and is connected to each transmission line.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a configuration diagram for explaining the microwave power amplifier according to the embodiment, and shows a state in the vicinity of one chip. In FIG. 2, 1 is an FET chip, 2 is an equivalent input matching circuit, 4 is a gate terminal, 5 is an input side bonding wire, 6 is an equivalent output matching circuit, 7 is a drain terminal, 8 is an output side bonding wire, and 14 is an input. Terminal, 15 is an output terminal, 16 is a slit, 18 is a thin film sheet resistor in the slit, and A indicates odd mode oscillation power in one chip.

Referring to FIG. 2, the FET according to the present embodiment
The chip 1 is connected to the gate terminal 4 of the FET chip 1 via the transmission line of the equivalent input matching circuit 2 and the input side bonding wire 5, and is connected to the FET via the transmission line of the equivalent output matching circuit 6 and the output side bonding wire 8. The drain terminal 7 of the chip 1 is connected. A slit 16 is provided in the transmission line of the equivalent output matching circuit 6. The in-slit thin film sheet resistor 18 is loaded in the form of sheet resistance in the slit 16 provided in the transmission line of the equivalent output matching circuit 6. Thereby, the odd mode oscillation power generated in the small closed loop circuit near the FET chip 1 can be efficiently absorbed.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
FIG. 3 is a circuit configuration diagram for describing a microwave power amplifier according to an embodiment. This embodiment has a circuit configuration in which a comb-shaped slit 16 is provided in a transmission line and a resistor is loaded in the comb-shaped slit 16 as shown in FIG. In FIG. 3, 6 is an equivalent output matching circuit, 16 is a slit, 18 is a thin film sheet resistor in the slit, 19 is a signal output terminal, and 20 and 21 are FET-side connection terminals.

Next, when the outer peripheral length of the comb-shaped slit 16 is changed by increasing the number of combs in the comb-shaped slit 16 without changing the external dimensions of the circuit, the FET chip 1
Is connected between the FET side connection terminal 20 and the FET side connection terminal 21 (unit is [dB]) and return loss at the signal output terminal 19 (unit is [d
FIG. 4 shows the result of calculating the change in B]).

FIG. 4 shows an FET-side connection terminal 20-2 in the microwave power amplifier according to the first to third embodiments.
FIG. 5 is a graph showing the isolation characteristics between FIG.
6 is a graph showing return loss characteristics at the signal output terminal 19 of FIG. In the present embodiment, for example, a thickness of 0.25
A slit 16 having a width of 0.05 mm was provided on a transmission line having a width of 3 mm and a length of 5 mm on an alumina substrate having a width of 3 mm.
When a resistance of 4Ω is loaded with respect to the impedance of 2Ω of the T chip 1 and the slit outer peripheral length L of the slit 16 is changed, as shown in FIG. The frequency at which the best rate is obtained shifts to the lower frequency range.

On the other hand, the return loss of the signal output terminal 19 does not change much, as shown in FIG. Thus, even if the slit width is small enough not to affect the characteristics of the equivalent output matching circuit 6 for the fundamental wave, the slit outer peripheral length L of the slit 16 provided in the transmission line can be changed without changing the external dimensions of the circuit. It can be seen that by changing the frequency, the frequency at which the isolation between the FET chips 1 becomes the best can be changed.

As described above, in the small-sized and low-loss equivalent output matching circuit 6, the comb-shaped slit 16 is provided in the transmission line of the equivalent output matching circuit 6, and the slit outer peripheral length L of the comb-shaped slit 16 is determined by the loop oscillation frequency. By setting the electrical length to 波長 wavelength and loading an isolation resistor between the loops, the odd mode oscillation power generated in the small closed loop circuit near the FET chip 1 can be efficiently absorbed and the loop oscillation can be suppressed. .

It should be noted that the present invention is not limited to the above-described embodiments, and it is clear that each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0024]

Since the present invention is configured as described above, the following effects can be obtained. A small, high-performance, and high-output FET chip that can stably operate by efficiently absorbing the loop oscillation power generated near the FET chip with a resistor can be realized. As a result, a more efficient loop oscillation suppression technology than before can be realized. It has the effect that it can be realized.

[Brief description of the drawings]

FIG. 1 is a specific configuration diagram for explaining a microwave power amplifier according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a microwave power amplifier according to a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram for explaining a microwave power amplifier according to a third embodiment of the present invention.

FIG. 4 is a graph showing isolation characteristics between FET-side connection terminals in the microwave power amplifiers of the first to third embodiments.

FIG. 5 is a graph showing a return loss characteristic at a signal output terminal in the microwave power amplifier according to the first to third embodiments.

FIG. 6 is a circuit diagram illustrating a conventional embodiment.

FIG. 7 is a specific configuration diagram illustrating a conventional embodiment.

FIG. 8 is a configuration diagram illustrating another conventional embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... FET chip 2, 2a, 2b, 2c, 2d ... Equivalent input matching circuit 4 ... Gate terminal 5 ... Input side bonding wire 6, 6a, 6b, 6c, 6d ... Equivalent output matching circuit 7 ... Drain terminal 8 ... Output side Bonding wire 10 Input resistor 11 Output resistor 14 Input terminal 15 Output terminal 16 Slit 17 Package 18 Thin film sheet resistor in slit 19 Signal output terminal 20, 21 FET connection terminal A , B: Odd mode oscillation power within one chip L: Slit outer circumference length S1: Loop gain of input side excitation S2: Loop gain of output side excitation α: Odd mode oscillation power between two chips β: Odd mode oscillation power between four chips

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J067 AA01 AA04 AA41 CA35 CA36 CA54 CA92 FA16 HA09 HA25 KA29 KA68 KS11 LS01 MA19 QA04 QS06 TA03 5J069 AA01 AA04 AA41 CA35 CA36 CA54 CA92 FA16 HA09 HA25 KA29 KA68 TA19

Claims (9)

[Claims] 1. A structure in which a slit of a predetermined shape having a predetermined peripheral length is provided in a transmission line near a multi-cell FET chip, and a sheet-shaped resistor for preventing loop oscillation is loaded in the slit. A microwave power amplifier, comprising: 2. A structure in which a comb-shaped slit having a predetermined outer peripheral length is provided in a transmission line near a multi-cell FET chip, and a sheet-shaped resistor for preventing loop oscillation is loaded in the slit. A microwave power amplifier, comprising: 3. A structure in which a slit of a predetermined shape having a predetermined peripheral length is provided in a transmission line near a multi-cell FET chip, and a resistor for preventing loop oscillation is loaded in the slit. A microwave power amplifier, characterized in that: 4. A structure in which a comb-shaped slit having a predetermined outer peripheral length is provided in a transmission line near a multi-cell FET chip, and a resistor for preventing loop oscillation is loaded in the slit. A microwave power amplifier. 5. A structure in which a resistor having a predetermined peripheral length and loaded with a resistor by sheet resistance is provided in a transmission line near a FET chip to prevent loop oscillation. And a microwave power amplifier. 6. A structure in which a comb-shaped slit having a predetermined outer peripheral length and loaded with a resistor by sheet resistance is provided in a transmission line near an FET chip to prevent loop oscillation. Microwave power amplifier. 7. A FE having a predetermined shape and having a predetermined outer circumference and loaded with a resistor for preventing loop oscillation is formed in the FE.
A microwave power amplifier having a structure provided in a transmission line near a T chip. 8. A microwave having a structure in which a comb-shaped slit having a predetermined peripheral length and loaded with a resistor for preventing loop oscillation is provided in a transmission line near an FET chip. Power amplifier. 9. The micro device according to claim 1, wherein an outer peripheral length of the slit is set to a size corresponding to a frequency at which isolation between FET chips is best. Wave power amplifier.