JPS63219156A - Semiconductor device memory - Google Patents

Abstract

PURPOSE:To effectively use the periphery of a memory cell for capacity forming regions and to contrive to improve the yield and the reliability of a memory by a method wherein the memory is constituted in a structure, wherein one word line and two bit lines are passed through the region of the one-bit memory cell. CONSTITUTION:When a word line 7a is given a high potential, a back-to-back bit lines are composed of Al circuits 6c and 6b and so on. By such the constitution of a memory, a memory cell becomes long in the direction of the word line and an allowance for forming isolation oxide films 2 between transfer gates 11 and the periphery of the memory cell is generated. Therefore, even though a capacity for information charge storage is formed on the side surfaces of the memory cell using all the periphery of the memory cell as grooved isolation regions 12, there is no need to etch a polySi layer 3 on the bottoms of grooves. Accordingly, the periphery of the memory cell can be effectively utilized in an easy production process, the capacity for information charge storage is secured even in the shallow grooves and the yield and the reliability of the memory can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a memory cell configuration suitable for high integration.

[Conventional technology]

Figure 3 (aL (b) is, for example, the lecture number FAM17.4 of the 1985 International Solid State Circuits Conference (ISSCC85).
FIG. 1 is a plan view and a cross-sectional view taken along the line XX of a highly integrated dynamic semiconductor memory device proposed in . In the figure, 1 is a P-type substrate, 2 is a field oxide film, 3 is a first layer of polycrystalline silicon, 4 is a capacitor insulating film, 5 is an N+ diffusion layer provided on the P-type substrate 1, and 6 is a first layer of polycrystalline silicon. 7 is the second layer of polycrystalline silicon, 8 is the second layer of A
The resistance of the word line 9 is lowered by the L wiring, which is electrically connected to the polycrystalline silicon at regular intervals. 10 is a contact hole that electrically connects the Al wiring 6 forming the pick line and the N'' diffusion layer 5; This is an information charge storage capacitor composed of crystalline silicon 3 and a capacitor insulating film 4.

In a semiconductor memory device configured in this way, since the grooved isolation portion on the outer periphery of the memory cell is utilized as an information charge storage capacitor, the area of the flat portion that forms the capacitor CF is reduced and the chip area is reduced. Even if the groove is deepened, C
Information charge storage capacity can be ensured by increasing p. Therefore, the gist of this prior art is to keep the area of the memory cell small, but with a large operating margin and a low soft error rate. In other words, as shown in FIG. 3(a), the longer the peripheral length of the memory cell is utilized, the smaller the depth of the trench required to obtain the same amount of CF.

On the other hand, for example, JP-A-51. When this memory cell structure is combined with the folded pin configuration shown in No. 74535, the cross-sectional view taken along Y--Y in FIG. 3(a) becomes as shown in FIG.

[Problem that the invention seeks to solve]

A highly integrated dynamic semiconductor memory device in which a conventional memory cell having a structure in which an information charge storage capacitor is also formed on the side surface of a trench isolation region is applied to a folded pin I-line configuration is as follows:
Its cross section has a structure like J in Fig. 4. In this structure, (i) the first layer of polycrystalline silicon 3 must be patterned within the trench isolation region, with the trench isolation region having the minimum pattern width and the polycrystalline silicon 3 at the bottom of the trench; It is difficult to etch silicon.

(11) Both sides of the channel region of the second layer polycrystalline silicon wiring 7 (which is controlled by this) which becomes the word line become trench isolation regions, and leakage current is generated on the sides of this trench. The transistor cannot be made completely non-conductive due to current flow.

There was a problem. Therefore, if we stop trenching on both sides of transfer gate 1 of the memory cell, the capacitance formed on the sides of the trench will be reduced by +1cC1. It was necessary to deepen the groove in the separation area.

This invention was made to solve the above-mentioned problems, and the length of the groove in the grooved separation area can be adjusted without forming the grooved separation area on both sides of the 1-transfer game 1. To obtain a highly integrated dynamic semiconductor memory device having a folded bit structure consisting of memory cells having a structure in which the required capacity can be ensured by digging a shallow trench by forming a capacitor on the side surface of the trench. The purpose is

Means for solving problem C using method H] First, in the semiconductor memory device according to the invention of B, in the conventional folded pit structure, two word lines and one bit line are placed on the outer periphery of a 1-bit memory cell. The memory cell was short in the word line direction, but the word line and the bit 1 to 2 lines pass through the 1-bit memory cell area.
: By adopting a folded bit line configuration, the memory cell is made longer in the word line direction while keeping the planar area of the memory cell constant.

[For production]

In a semiconductor memory device configured in this way, since the memory cells are longer in the word line direction, there is more room to form an isolation oxide film between the transfer gate 1 of the memory cell and the periphery of the memory cell. Sign.

Therefore, even if a capacitor for information charge storage is formed on the side surface by trenching an isolation region around the memory cell, there is a flat isolation oxide film on both sides of the transfer gate 1.
It is no longer necessary to etch the first polycrystalline silicon layer at the bottom of the trench, and the leakage current of the channel in the 1-transistor can be suppressed to about the normal Locos level. Therefore, since the area around the memory cell can be effectively used as a capacitor formation region, information charge storage capacity can be easily secured even in a shallow trench.

[Embodiments of the invention]

Hereinafter, one embodiment of the invention of B will be described with reference to the drawings. 1st
In the figures, (a) is a plan view, and (b) is X-x in (a).
1(C) is a perspective view of two bits sharing a contact, viewed from the direction of the arrow in FIG. 1(a).

In the figure, ■ is a P-type silicon substrate, 2 is an oxide film for element isolation, 2a is a diffusion layer for element isolation in which impurities of the same conductivity type as the substrate formed on the side surface of the groove are diffused, and 3 is information charge storage. A first polycrystalline silicon layer forming one electrode plate of the capacitor, 4 a gapacitor insulating film, 5 an N+ diffusion layer, 6 (
The first layer of AI wiring forming the cobisoto line, 7 is the word
Second layer of polycrystalline silicon layer forming the lead wire, 10% A
11 is a channel of a transistor controlled by the word line 7, 12 is a trench isolation region, and CP is formed on the slope of the trench isolation region. N+ diffusion layer 5 and polycrystalline silicon 3
This is the capacitance between the two and forms part of the information charge storage capacity.

C' is a capacitance formed between the N+ diffusion layer in the flat part and the polycrystalline silicon 3, and also forms part of the information charge M accumulation amount.

As is clear from the plan view of FIG. 1(a), since the configuration is such that two pit lines and one word line pass through one bit area of the memory cell, for example, when the word line 7a is set to a high potential, , the AII wire 6c becomes the pin 1 wire, and the /M wire 6b
It becomes a pit line and has a folded pit line configuration. Furthermore, in this memory cell structure, there is no need to pattern the polycrystalline silicon 3 within the trench isolation region 12, which facilitates the manufacturing process. Further, since the trench isolation region 2 and the channel region 11 of the transistor are no longer in contact with each other, leakage current control of the transistor controlled by the word line 7 is facilitated, and information charge retention characteristics are not deteriorated. Further, the entire outer periphery of the memory cell becomes a trench isolation region 12, except for the isolation diffusion layer 2a formed on the side wall of the trench isolation region in order to isolate two memory cells that share a contact. Since an information charge storage capacitor CP is formed in , a large capacitance CP can be obtained even with a shallow trench. For example, in FIG. 1(a), 0
The memory cell is designed according to the 8μm rule, and the cell area is 2
．． To obtain an information charge storage capacity of 6μ x 4.2μm 10.92p2, 5ofF, when the capacitor insulating film is 100m thick, the depth of the trench isolation region is only 1.94μ, compared to the conventionally announced 4 Mbit D RAM. This means that it is possible to dig a trench shallower than the memory cell used for the purpose.

Note that in the above embodiment, a trench isolation region was formed all around the memory cells of 1 to 2 adjacent pins sharing a contact hole, but in the above embodiment (Fig. 1), a trench isolation region was formed on the side surface. In the area sandwiched between the separation and diffusion layers, there is a flat part 2b created by not digging a trench, as shown in FIGS. Even if an isolation oxide film is formed on the side surface portion 2b, and an isolation diffusion layer or an isolation oxide film in which impurities having the same conductivity type as the substrate are diffused is formed on the side surface portion 2b, the same effect as in the above embodiment can be obtained.

In the first and second embodiments described above, a memory cell having an n-type channel transfer gate 1 on a P-type semiconductor substrate has been described. In this case, if the isolation diffusion layer formed on the sidewall is an n-type conductivity type diffusion layer, the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the invention of B, the trench isolation region of the memory cell array with the folded bit line configuration is formed so that the trench length is as long as possible without contacting the channel region of the transistor. It is unnecessary to etch the polycrystalline silicon layer in the trench isolation region. In addition, the leakage current of the transistor channel is reduced to about the level of ordinary Locos, and furthermore, sufficient information charge storage capacity can be ensured even with a shallow trench. Therefore, the yield and reliability of semiconductor memory devices are improved.

[Brief explanation of the drawing]

FIG. 1(,) is a plan view showing a memory cell array of a semiconductor memory device according to an embodiment of the present invention, FIG. 1(b) is a sectional view, FIG. 1(c) is a perspective view, and FIG. A plan view of a semiconductor memory device according to another embodiment, (b) a perspective view,
FIGS. 3 and 4 are a plan view and a sectional view showing a conventional semiconductor memory device. 2 is an isolation oxide film, 2a is an isolation diffusion layer, 5 is an N+ diffusion layer,
6 is the AJ wiring, 7 is the word line, 10 is the contact hole, 1
2 is the trench isolation area. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 2 (A Ram 76% 7d6 Yu 2-・
■ − ,, −(−, 5 2 “ 56C−・Pa≧/l

('′“■ ′( 6, / 1, (Fig. 3

Claims (2)

[Claims] (1) One word line and two bit lines pass through an area corresponding to one bit of memory cell, and a trench is dug around the entire periphery of the adjacent two bits of memory cell, sharing contact with the bit line. An isolation region is formed, and in order to isolate the 2-bit memory cells from the sides of the grooved isolation region, there is no information other than the portion where a diffusion layer with a concentration higher than that of the substrate of the same conductivity type as the substrate is formed. 1. A semiconductor memory device comprising a memory cell array having a folded bit line configuration consisting of memory cells in which a capacitor for charge storage is formed. (2) A second diffusion layer, which is opposite to the first electrode with an insulating film in between, is formed on the side surface of the trench isolation region and has a conductivity type opposite to that of the substrate. 2. The semiconductor memory device according to claim 1, wherein the polysilicon layer forming the electrode is formed only within the trench isolation region.