JPS6321874A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the dimensional change of a gate electrode from occurring due to side etching by forming the gate electrode, then coating it with a photoresist, forming a pattern by photocomposing in size larger than the electrode, and implanting an impurity to both side edges of the electrode except the photoresist. CONSTITUTION:A field oxide film 2, a gate oxide film 3 and a phosphorus-doped polysilicon film 4 are formed on a P-type semiconductor substrate 1, and a gate electrode 5 is formed by etching it with a resist as a mask. After the resist which becomes unnecessary is removed, it is coated with a resist 6, and a pattern is formed by a patterning mask of desired channel length L. Then, the resist 6 of both side edges of the electrode 4 remains, and an impurity 7 is implanted to form an impurity region. The resist 6 of the part of the electrode 4 is removed, annealed by heat treating to form source, drain region 8, and the surface is covered with a PSG film 9. Thus, it can prevent the dimensional change from occurring due to side etching of the electrode 4.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" This invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
S. In a transistor, a method for manufacturing a semiconductor device in which a gate electrode is formed on a semiconductor substrate, and an impurity is selectively introduced into the semiconductor substrate using a cell line as a mask to form an impurity region. Regarding.

[Prior Art] In general, MOS t-run transistors include N-channel MO3 transistors and P-channel MOS transistors. Most of the transistors with MOS structure are silicon gate MO3 transistors because of their low switching speed and low power consumption. It is used. Also, switching speed 1
To improve performance, channel length dimensions have been scaled down to improve gm. Such a silicon gate MO3 is manufactured by the following manufacturing method.

FIGS. 28 to 2D are cross-sectional views of a silicon gate MoS at J-3 according to the conventional manufacturing method.

First, referring to FIGS. 28 to 2D, the conventional 1!
The silicon gate MO3 using the method will be explained.

First, after forming a 3i02 film on a semiconductor substrate 1 by dry oxidation, S! On top of the 02 theory, 3! 3
Inject N4 g. Then, a pattern is formed on the resist 1 using the cvoi photolithography method, and the 5laN4 film is removed by selective etching. Using the patterned 5isNs pattern as a mask, field oxidation g! 2
is grown by 1 μra/li.

After that, Si, N41! and 3102 film is removed and gate oxide 8!3 is grown to a thickness of 600A. Furthermore, a phosphorus-doped polysilicon film 4 is deposited as a gate electrode material film to a thickness of 3000 nm. Said polysilicon! ! 4 is etched by photolithography using a resist as a mask and plasma etching to form a gate bridge 5 shown in FIG. 2B. Then, in order to form sources and drains, impurities 7 are implanted by ion implantation, and a second C
As shown in the figure, source and drain 1 are connected to the self-line.
4 regions 8 are formed. Then, as shown in FIG. 2D, P
The surface is covered with an SG film 9.

[Problems to be Solved by the Invention] Since the conventional silicon gate MOS transistor is manufactured as described above, the dimensions of a single silicon transistor are as follows.
Fluctuations occur during plasma etching when forming the gate electrode 5, and the source/drain width changes, resulting in variations in source/drain breakdown voltage and threshold voltage Vrs in terms of characteristics.
Deterioration of device characteristics due to fluctuations in

Therefore, the main object of the present invention is to create a semiconductor device in which fluctuations in channel length due to plasma etching are suppressed as much as possible, and the channel length does not substantially change even if the source/drain diffusion region is expanded by heat treatment. An object of the present invention is to provide a manufacturing method.

[Means for Solving the Problems] This invention is a MOS in which a gate electrode is formed on a semiconductor substrate, and impurities are selectively introduced into the semiconductor substrate using the gate electrode as a mask in a self-line, thereby forming an impurity region W4.
A method for manufacturing a semiconductor device such as a T-run lister element, the gate 1! After forming the electrode, a photoresist is applied, a pattern larger than the gate electrode is formed using photolithography, the photoresist is left on both edges of the gate electrode, and impurities are introduced. .

[Function] In the semiconductor device manufacturing method of the present invention, since the photoresist is left on both edges of the gate electrode portion and impurities are introduced, substantial dimensional changes due to side etching of the gate bridge can be prevented. .

[Embodiments of the Invention] FIGS. 18 to 1E are cross-sectional views of each process of a MOS transistor manufactured by the manufacturing method of the present invention.

First, as shown in FIG. 2A, a 5iOz film with a thickness of 500A is formed on a P-type semiconductor substrate 1 by dry oxidation, and then a 3iOzM! A Si3N<10 film was formed on top using the CVD method.
How many necks are made with a thickness of 00A?

A resist pattern is formed on the CVDm by photolithography and selectively plasma etched to form S'sN, Il! remove. And patterned Si! Using the N4 film as a mask, field oxide film 2 is grown to a thickness of 1 μm. Then sawN, membrane and S! The Oz film is removed and a gate enhancement film 3 is formed. Further, a phosphorus-doped polysilicon film 4 is deposited as a gate electrode material film to a thickness of 3000 nm.

Next, as shown in FIG. 1B, the polysilicon film 4 is etched by photolithography using a resist as a mask and plasma etching to form a gate hole 5. and,
After removing unnecessary resist, as shown in FIG. 1C, resist 6 is applied again and a pattern is formed by photolithography using a patterning mask having a desired channel length.

Next, as shown in FIG. 1D, in order to form the source and drain by leaving the resist on both edges of the gate electrode 4,
An impurity 7 such as phosphorus is implanted by ion implantation to form an impurity region wA. Then, as shown in Figure 1E,
The resist in the gate electrode 4 portion is removed and annealing heat treatment is applied to form the source/drain 14 region 8.

After that, PSG! Cover the surface with 19.

In the above-mentioned embodiment, the present invention is applied to a case where an N''5-t□ channel MOS transistor is manufactured, but the present invention is not limited to this and can be applied to a P-channel MOS transistor.
Even when the present invention is applied to manufacturing a C-IXvl OS transistor and a C-IXvl OS transistor, the same effect can be achieved.

[Effects of the Invention] As described above, according to the present invention, after forming a gate electrode, a photoresist 1- is applied, and a pattern is formed using a W'J version of a photoresist (larger than the gate electrode). No. 1, leave photoresist on both edges of the gate 1tffi part!
Since the parts are rounded, substantial changes in dimensions due to side etching of the gate electric bridge can be prevented. Moreover, since the expansion of the source/drain expansion region due to heat treatment does not substantially change, it is possible to prevent the threshold voltage VTH from decreasing due to short channel formation.

[Brief explanation of drawings]

FIGS. 18 to 1E show N-channel M according to the present invention.
FIG. 3 is a cross-sectional view of each step of the OS transistor. FIGS. 28 to 2D are cross-sectional views of each step 9J of a MoS transistor manufactured by the conventional manufacturing method. In the figure, 1 is a semiconductor substrate, 2 is a field oxide film,
3 is a gate/oxide film, 4 is a phosphorus-doped polysilicon model,
5.6 is a resist, 7 is an impurity, 8 is a source/drain area, 9 is a PSGI, and L is a channel length.

Claims (1)

[Claims] A method for manufacturing a semiconductor device in which a MOS transistor element has a gate electrode on a semiconductor substrate, and an impurity is selectively introduced into the semiconductor substrate using the gate electrode as a mask by self-alignment to form an impurity region. After forming the gate electrode, a photoresist is applied, a pattern larger than the gate electrode is formed by photolithography, and the photoresist is left on both edges of the gate electrode portion, and impurities are introduced. A method for manufacturing a semiconductor device, characterized in that: