JPS63217665A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an LDD transistor resisting against high voltage stress by forming a section not shaped under an insulator in the side wall of a gate electrode into the second diffusion region of at least one of source and drain regions. CONSTITUTION:Source and drain regions formed by a second conductivity type first diffusion region arranged brought into contact with a channel section and a second conductivity type second diffusion region being disposed brought into contact with the first diffusion region and having concentration higher than the first diffusion region are shaped. A section where there is no second diffusion region of at least one of these regions under an insulator in the side wall of a gate electrode 5 is formed. That is, the width L' of a low- concentration diffusion region near a drain is made larger than that L of the insulator existing on the side wall of a gate. Accordingly, even when high voltage is applied to a drain electrode, a high electric field is difficult to be applied to the end sections of the gate electrode 5.

Description

[Detailed Description of the Invention] [Object of the Invention (Industrial Application Field) The present invention is directed to an LDD (Lightly Doped Dr.
The present invention relates to a semiconductor device that entirely constitutes a MOS transistor with ain) structure.

(Prior Art) In recent years, as LSIs have become highly integrated, LDD structure transistors have come into widespread use in MOS transistors due to their reliability. Figure 4 is a cross-sectional view of a conventional DD transistor, in which 1 is a P-type substrate, 2 is a gate oxide film, and 5 is a cross-sectional view of a conventional DD transistor.
is the gate '4 pole, 6 is N-7m, 7 is the S r O2 pattern on the side wall of the gate pole, and 9 is the N+ layer.

In order to guarantee high reliability, the above LDD l-Lannostar has a surface concentration of about 1X in the drain part at the end of the gate electrode.
A major feature is that it has a low concentration of diffusion due to phosphorus of 10 to 1X10. Further, normally, a SiO□ pattern 7 is formed on the side wall of the /r''-) electrode in a self-aligned manner.

(Problems to be Solved by the Invention) The above-mentioned LL)D l-lan soster has less optical drive ability and threshold voltage fluctuations than transistors of conventional structure for voltages in the normal operating range (0 to 8 V). I know that there are few. However, it has recently been found that high voltage stress, for example, voltage stress of 10 V or more, causes trannostars to break down more easily than solid structure trannostars.

The present invention has been made in view of the above-mentioned circumstances, and aims to provide an LDD (LDD) lannostar that is resistant to high voltage stress.

[Configuration of the Invention (Means and Actions for Solving Problems) The present invention consists of the first
In a MOS transistor having an insulator formed on the side wall of an r-) electrode on a conductivity type semiconductor substrate, a first diffusion region of 1g2 conductivity type disposed in contact with the channel part and a first diffusion region disposed in contact with the region. The source and drain regions are formed by second diffusion regions of a second conductivity type that are 4 degrees higher than the first diffusion region, and at least one of these regions is formed on the sidewall of the gate electrode. It is characterized by the fact that there are parts that do not exist below the 3 edges. That is, the present invention
The width of the low concentration diffusion region near the drain is made smaller than the width of the insulator existing on the gate sidewall, and the drain 'F! Even if a high tortoise pressure is applied to the electrode, high
The L field is applied.

(Embodiment) An embodiment of the invention will be described below with reference to the drawings. 1st
The figure is a process diagram of the same embodiment, but since this is an example in which Fi corresponds to that of the conventional example, the same reference numerals are used for corresponding parts. First, as shown in FIG.
4000 layers of polycrystalline silicon 3 are deposited. Then P.O.C.
After 51p+ is diffused in step 43 and a renost pattern 4 is formed by photolithography, a gate electrode 5 is formed in the dirt portion by etching using a mask as shown in FIG. 41(b). Next, using the gate electrode 5 as a mask, dose jl of 5+p+.
i 2 X l 015 cm-2, acceleration 4 pressure 40 ke
Ion implantation is performed at V to form N-)-6. Next, as shown in Figure 1 (C), CVD -8+021
1J (deposit about 3000λ. K K upper Ae,
C”/D-sto2i to RlE (Reactive
Etching with Ion Etching). As a result, a 5itJ2 pattern 7 is formed on the side wall of the r-) electrode 5. After that, a Lenost pattern 8 is formed by photolithography,
The result All is 50 ke as shown in Figure 1(d).
V , 3

Normally, as shown in Figure 1(d), N
-/m6 width is controlled. The width L' of one N'''' layer (drain side) is such that the voltage stress of the glass is on the inlet side. This is because this is desirable in order to suppress deterioration in the driving ability of the transistor. However, if a decrease in current drive capability is not a problem, the relationship L (L') may not be true. In FIG. Aa
'? It was formed by ion implantation, but as shown in Figure 2, the N no due to 75A and + on the source side is the S formed on the side wall.
It is not necessarily necessary to use the 10□ pattern 7 as a mask for ion implantation, and it is also possible to use the Renost pattern as a mask.

In addition, as an application example of a real enemy, as shown in Figure 3, the area around the field edge part (MOS) where the field edge is the strongest (the border between the rehatching area and its surrounding area) is 2 yields - the horn and the gate. It is effective to apply the configuration of the present invention to the vicinity of the intersection with the gate electrode and extend the other portions of the N layer 9 toward the gate Vl pole 5 side to increase the current drive capability.

By doing the above, N
Since there is a part where the + layer does not exist, it becomes possible to insert a resistor of N layer 6 on the drain side, and the voltage division determined by the product of the current I flowing there and the resistance R of the N layer is the voltage stress. become stronger against In other words, it will not break even if high tortoise pressure is applied.

As a result, it is possible to eliminate the drawback that the LDD transnoster is said to be susceptible to high voltage stress. In the present invention, it is important that the side wall material of the CVD-5in2 film 7 is present. This means that an LDD transnostar is always formed and the minimum N11i width is CVD -8i
This is because it has the great advantage of being determined by the 0□ film 7. By the way, it has been experimentally found that it is desirable that the N''''1-width is 1 g+ or more when there are no 5 layers under the side wall material.

[Effects of the Invention] As explained above, according to the present invention, a semiconductor device (LDT) resistant to high voltage stress can be provided.

[Brief explanation of the drawing]

Fig. 1 is a process diagram for obtaining one embodiment of the present invention, Fig. 2 is a sectional view of a different embodiment of the present invention, and Fig. 8g3 (a) is a plan view of a pattern of a different embodiment of the present invention. b) is a sectional view taken along the A-A' edge of FIG. 3(a), FIG. 3(c) is a 9M sectional view taken along B-B' and C-C'd of FIG. 3(a), Fourth
The figure is a sectional view showing a conventional LDD (Lannostar).

Claims (4)

[Claims] (1) In a MOS transistor having an insulator formed on a sidewall of a gate electrode on a semiconductor substrate of a first conductivity type, a first diffusion region of a second conductivity type disposed in contact with a channel portion; source and drain regions formed of a second diffusion region of a second conductivity type with a higher concentration than the first diffusion region disposed in contact with the first diffusion region; A semiconductor device characterized in that there is a portion where the diffusion region does not exist under the insulator of the side wall of the gate electrode. (2) The semiconductor device according to claim 1, wherein the width of one first diffusion region is larger than the width of the other first diffusion region. (3) At least one sidewall of the gate electrode on the field edge with a first diffusion region of low concentration in contact with the channel region including the field edge and a second diffusion region of high concentration in contact with the first diffusion region. 2. The semiconductor device according to claim 1, wherein only the first diffusion region exists under the insulator. (4) At least one sidewall of the gate electrode on the field edge with a first diffusion region of low concentration in contact with the channel region including the field edge and a second diffusion region of high concentration in contact with the first diffusion region. Only the first diffusion region exists under the insulator, and the second diffusion region exists under the insulator on the side wall of the gate electrode except near the intersection of the field edge and the gate electrode. A semiconductor device according to claim 3.