JPS63217447A - Deciding system for cache function - Google Patents

Abstract

PURPOSE:To omit the echange of software when boards are exchanged by diagnosing the boards to decide the presence or absence of a cache function and setting the software in response to the cache function. CONSTITUTION:The presence or absence of a cache buffer 13 is checked by a board diagnosing means. Then the presence or absence of a table comparator 10 is checked. Thus it is decided whether both checks are erroneous or not for decision of the presence or absence of a cache function. In such way of decision for presence or absence of the cache function, only the reading/writing speed varies despite the exchange of boards and it is not required to exchange the software in response to the exchange of boards. Thus the software can work smoothly in the same system.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for determining a cache function, and in particular, a method for determining whether or not a board has a cache function when the board is replaced as an option. A method for determining the cache function for selecting a method is discussed.

[Background of the invention]

Generally, the cost of a board changes depending on the presence or absence of memory, so replacing the board is an option, but conventionally, replacing the board requires purchasing new software as well. There was an inconvenience.

[Purpose of the invention]

Therefore, the present invention has been made by paying attention to the above-mentioned conventional situation, and has solved such problems.

Even if the board is replaced and the board becomes different, it will be possible to operate the same system with the same software without any problems.
The purpose is to provide a cache function determination method that eliminates the need to replace software to match the board.

[Means for solving the problem] In order to achieve this object, the cache function determination method according to the present invention is to check the presence or absence of a cache buffer by the diagnostic means of the board, and then check the presence or absence of the cache buffer by the table comparator. The cache function is characterized in that the presence or absence of the cache function is determined by checking the presence or absence of the cache function and determining whether both of the above checks result in an error.

[Effect]

By determining the presence or absence of the cache function as described above, even if the board is replaced, only the read/write speed will change, and there is no need to replace the software to match the board, and the software will remain the same. The system will now operate without any problems.

〔Example〕

Next, an example of implementation of the present invention will be described in detail with reference to FIGS. 1 to 7.

FIG. 1 is a flowchart showing the processing of the cache function determination method according to the present invention, and numeral 1 in the figure indicates a board diagnostic means. This diagnostic means 1 is initially set to be operated by a task, and is executed by reading/writing the address of the RAM to determine whether or not the board has a RAM as a cache buffer.

A board with RAM on it has a cache function, so if an error occurs, it means that the RAM is missing or broken. Next to checking the presence or absence of this cache buffer, if it is registered in the RAM area, what cylinder and what sector does it have?
That is, the presence or absence of a table comparator for finding out whether or not the desired data is actually registered is checked, and a decision is made as to whether or not one or both of the checks are errors. As a result, if there is an error in both, it means that there is no cache function, and if there is no error, it means that the cache function is present. Also, if either the cache buffer or the table comparator is checked and an error occurs, it means that the board is broken.

Moreover, what is shown in FIG. 2 is a block configuration diagram of the disk cache system, and the disk cache system is roughly divided into an initial setting section 2 (diagnosis is also performed here),
Interrupt processing unit 3, monitor part 4, command processing task 5ae5b corresponding to presence/absence of cache, background processing task 6, and hard disk 7 are connected/\-
This will be the disk driver 8. In the figure, numeral 9 is a debugger connected to a CRT connected to a keyboard and for extracting defective parts of the program. Since this disk cache system can also perform operations without using a cache, the command processing task that operates by interrupting the task file has two base columns 5 and 5 corresponding to the presence or absence of cache.
It is a and 5b.

Furthermore, FIG. 3 is a conceptual diagram showing the format of the table comparator 10.
As mentioned above, this is used to find the cache address, and cache hits/errors can be determined quickly using high-speed static RAM and 24-bit hardware comparison logic. The cache table has a 4-byte structure, and the fourth byte is unused, and this unused portion is not compared by the hardware.

Also, FIG. 4 is a conceptual diagram showing the representation state of disk addresses within the cache system.
The 2 bits of the byte are the unit number, the 10 bits from the first byte to the second byte are the cylinder number, the remaining 4 bits of the second byte are the head number, and the third byte is the unit number.
Three bits of the byte are reserved and the remaining five bits are the sector number.

Furthermore, FIG. 5 is a conceptual diagram of the carrier 7 buffer management table 11, and shows the start address in the case of one sector 512. This cache buffer management table 11 is used to establish the correspondence between the cache table and cache buffer described above, and also processes cache generation, erasure, writing, etc. by linking the blocks of each cache buffer according to the purpose. efficiency can be increased. The management block lla of this cache buffer management table 11 includes a cache block pointer 12a which is a pointer indicating one sector of the cache buffer, and a forward link pointer 12b (the number of the previous linked cache buffer management block 11a) which is a pointer indicating one sector of the cache buffer. (FFFF in the last case), a backward link pointer 12c (FFFF in the last case) indicating the number of the cache buffer management block lla linked later, and a flag 12d, and the rest are reserved. FIG. 6 shows this flag 12d, and the 8-bit flag 12d includes read sector, resident sector,
It forms part of the write wait flag and write error.

FIG. 7 also shows the table comparator 10, cache buffer management table 11, and cache bar 2 described above.
It is a conceptual diagram showing the relationship between the cache buffer 13 and the table comparator l, in which each block of the cache buffer management table 11 is connected by various links, and the cache buffer 13 and the table comparator l
Also, write waiting links and write error links are supported by battery-backed R.
It is compatible with AM.

〔Effect of the invention〕

As described above, according to the cache function determination method according to the present invention, the board is diagnosed and the presence or absence of the cache function is determined, and the software is adapted accordingly, so even if the board is replaced, there is no need to replace the software accordingly. Now, software can run on the same system without any problems, just by changing the speed.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing processing of a cache function determination method according to the present invention, and FIG. 2 is a block diagram of the disk cache system. FIG. 3 is a conceptual diagram showing the format of the table comparator, FIG. 4 is a conceptual diagram representing disk addresses in the cache system, and FIG. 5 is a conceptual diagram of the cache buffer management table. FIG. 6 is a conceptual diagram of the flag, and FIG. 7 is a conceptual diagram showing the relationship among the table comparator, cache buffer management table, and cache buffer. 1...Diagnostic means 10...Table comparator 1
1... Cache buffer management table 13... Cache buffer Figure 1 Figure 2, J2 Figure 3 p Figure 5 + 2d Figure 7

Claims (1)

[Claims] A cache function characterized in that the presence or absence of a cache buffer is checked by diagnostic means of the board, then the presence or absence of a table comparator is checked, and a decision is made as to whether both of the above checks result in an error, thereby determining the presence or absence of a cache function. Judgment method.