JPS632166A - Signal processing circuit for cd reproducing device - Google Patents

Abstract

PURPOSE:To simplify a circuit detecting the write/read state of a RAM and to decrease the number of elements in case of an integrated circuit by providing a specific counter and a specific flip-flop. CONSTITUTION:A 1st counter 1 designates a write address and a 2nd counter 3 designates a read address, but a write address is increased more than a read address by a prescribed area. After the count of the 2nd counter is preset to a 3rd counter 6, a clock pulse COMPLC is applied to 3rd and 4th counters 9 to start counting and when the 1st counter and the 3rd counter are coincident, the count output of a 4th counter is stored in plural flip-flops at every prescribed frame number. On the other hand, when the frequency division output of a frequency divider circuit 29 of a servo circuit is generated, a frequency division ratio control circuit 26 fetches the output of the flip-flop to decide the frequency division ratio of the frequency divider circuit depending on the output state and to reset the flip-flop, thereby controlling the drive of a disk motor at an optimum timing interval.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to a signal processing circuit for a CD (compact disc) playback device, and in particular, it stores symbol data read from a CD in a RAM, and The present invention relates to a signal processing circuit that reads and deinterleaves the symbol data stored in the RAM and controls the rotational speed of a disk motor based on the amount of data stored in the RAM.

(b) Conventional technology In the CD system, an error correction system called CIRC (Cross Interleaved Reed-Solomon Code) is used, and 24 information symbols (8 A total of 32 symbols are created, including 8 parity symbols (8 bits) and 8 parity symbols (8 bits). These 32 symbols (with 8-bit subcodes) are EFM-modulated and recorded on the disk as one frame along with a 24-bit hoom synchronization signal. Recording on the disk is performed using the constant linear velocity (CLV) method. will be done.

The signal processing circuit in the CD playback device decodes the EFM signal read from the disc to create 8-bit symbols, sequentially allocates the symbols to the RAM tα, and decodes the symbols stored in the RAM. The operation of reading and performing CI error correction and C6 error correction by the CIRC circuit for each frame, and storing the corrected symbols in the RAM again, and the operation of reading the corrected symbols from the RAM and applying them to the DA conversion circuit. We are doing this.

In addition, in the CLV system, the disk motor is controlled by a servo circuit so that the linear velocity of the disk is constant. That is, the phases of a signal obtained by dividing a synchronizing signal created by a PLL circuit based on an EFM signal by a frequency dividing circuit and a signal obtained by dividing a reference signal from a reference oscillator by a frequency dividing circuit are compared, and these signals are determined to be - The disc motor is controlled to match the

However, if the servo of the disk motor becomes inaccurate due to a dropout of the EFM signal, the linear velocity of the disk will no longer be constant, and jitter will occur in the EFM signal. These jitters can be absorbed by the RAM within a certain range, but beyond that range, the jitters cannot be absorbed.

Therefore, in the past, the amount of data accumulated in the RAM was detected, and the frequency division ratio of the frequency divider circuit that divided the frequency of the synchronization signal created based on the EFM signal was increased or decreased depending on the amount of accumulation, or the reference signal was divided. By increasing or decreasing the dividing ratio of the frequency divider circuit,
It was controlling the de-r fuel motor. This allows R
The disk motor can be servoed so as not to exceed the AM jitter absorption amount.

The above technique is described in Japanese Patent Application Laid-Open No. 59-90262.

(c) Problems to be Solved by the Invention However, conventionally, in order to detect the amount of data stored in the RAM, an arithmetic circuit for calculating the difference between the write address and the read address of an address counter that controls the address of the RAM has been used. This has the disadvantage of increasing the number of elements.

(d) Means for solving the problems The present invention has been made in view of the above-mentioned points, and the RA
a first counter that determines the write address of M;
a second counter that determines the AM read address;
a third counter to which the contents of the second counter (or the first counter) can be preset; a fourth counter that counts the number of clock pulses until the contents match; a plurality of flip-flops that store control signals for increasing/decreasing the frequency division ratio according to the count value of the fourth counter at predetermined timings; and a disk motor. A frequency division ratio control circuit receives the output of the flip-flop using a frequency division output pulse of a frequency division circuit constituting the servo circuit, determines a frequency division ratio, and resets the flip-flop.

(N) Effect According to the above-mentioned means, the first counter receives the write request pulse 32LP generated based on the synchronization signal of the EFM signal.
The second counter specifies the read address by counting up based on the reference clock pulse from the crystal oscillation circuit, but the write address is set in a predetermined area (e.g. It is larger by "6" area). Therefore, after presetting the count value of the second counter to the third counter by a preset pulse PS generated at a certain timing, a clock pulse COMPCL is applied to the third counter and the fourth counter to perform counting. When starting, if the disk is rotating normally, coincidence between the first counter and the third counter is detected by six clock pulses COMPCL. That is, the rotational status of the differential motor can be determined based on the count value of the fourth counter when the -match signal is reached, and the count output of the 40th counter is used as control information for the servo circuit based on the -match signal. Then, the control information is stored in a plurality of flip-flops for each predetermined number of frames. - On the other hand, when the frequency division output of the frequency division circuit of the servo circuit is generated, the frequency division ratio control circuit takes in the output of the flip-flop, determines the frequency division ratio of the frequency division circuit according to the output state, and further By resetting the flip-flop, the rotation of the disk motor can be controlled at optimal timing intervals.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
The counter (FCTRH) (1) specifies the address area of the RAM (not shown) in which 24 information symbols and 8 parity symbols for one frame demodulated from the EFM signal are written. It is made up of bits. In addition, the count input CL of the first counter (1) has the following values:
A counter (
FCTRL) (2> Carry output is fully applied.

That is, the first counter (1) specifies the upper address of the RAM where one symbol for one frame is written, and the counter (2) specifies the lower address where one symbol is written in that address area. be. Here, the write request signal 32LP is set to PL in synchronization with the EFM signal.
Synchronous signal PLCK (4
, 3218M) 1□), so the EFM
Due to the jitter in the signal, jitter also occurs in the counts of the counter (2) and the first counter (1).

- On the other hand, the second counter (XCTR) (3) is composed of 7 bits, and in order to read out the symbols for one frame written in the RAM, the address area where one frame worth of symbols is stored. Specify.

The counting input CL of this second counter (3) has a clock pulse φ2M (2, 1609MM
The carry output of a hexadecimal counter (TnS R) (5) which is continuously connected to a 49-decimal counter (49CTR) (4) which counts z) is applied.

That is, the timings for signal processing of symbols of one frame are 49 timings t0 to t4. When the processing of one frame is completed, the second counter (3) counts up by "1", and the counting is extremely accurate because it is based on a crystal oscillation circuit. .

The third counter (COMPCTR) (6) is a 7-bit presettable counter, and the second counter (COMPCTR) (6) is a 7-bit presettable counter.
) is applied to the preset input terminal, and the preset control input P is an AND gate (7) to which the timing signal Ts and the signal 5INT generated at the first timing t0 of each timing T, -T, are applied. A preset pulse PS is applied to the clock input CL, and a timing signal T6 and timings t0 to t4 . The output pulse COMPCL of the AND gate (8) to which the pulse 5YNDCL, which is output in synchronization with the timing of , is applied is applied. The fourth counter (C
LCTR) (9) counts the clock pulses COMPCL that are applied to the third counter (6) and are uncountable.
It is a bit counter, and a preset pulse PS is applied to the reset manual power R, and a clock pulse COMPCL is applied to the clock manual power CL.

By the way, in the embodiment shown in FIG.
There is a difference of 11 minutes between the write address and the read address from the RAM.In other words, when the disk is rotating at a normal linear velocity, the 10th counter (1) The count value of the second counter is always greater than the count value of the second counter by "6''. Therefore, the third
When the counter (6) and the fourth counter (9) count six clock pulses COMPCL, the first counter (
1) and the count value of the third counter (6) should match, and at that time, the count value of the fourth counter (9) should be “6”.
Therefore, the status of the disk motor can be known by determining whether or not the count value of the fourth counter (9) deviates from "6" as the center. For this purpose, the 7-bit output of the first counter (1) and the 7-bit output of the third counter (6) are connected to a coincidence detection circuit (
10) to obtain the coincidence detection output DET, and the fourth
The counter (9) outputs an output CT that becomes ``H'' when the count value is 2'' to ``4''.
An output CT(-) that becomes "H" when the count value is "8" to "10" and an output CTC-) that becomes "H" when the count value is "8" to "10" are extracted.

Output CT(-), CT, from the fourth counter (9).

2, CT<-> is applied to the AND gates (11), (12), and (13) to which the match detection output DET is applied, and each output of the AND gates (11, 12, and 13) is These are applied to the inputs of D-F F (14), (15), and (16), respectively. Also, D −F F (14) (15)
The clock manual power CL of (16) has D −F F (1
4) NOR to which the outputs Q of (Is) (16) are respectively applied.
Output of gate (17) and clock pulse COMPCL
is applied to the output of the AND gate (18),
Further, a preset pulse PS is applied to the reset human power R. Therefore, after the preset pulse ps is generated,
Since D −F F (t4) (ts) (ts) is reset, the clock pulse COM is output through the AND gate (18) at the same time as the third and 40th counters (6) and (9).
PCL is applied to the clock input CL of D -F F (14)<15) (16), and D -F according to the count contents of the fourth counter (9) when the -match detection output DET is generated.
F (14), (15), and (16) can be set.

Also, the output of the NOR gate (17) is at timing T,
and the output T of the AND gate (19) to which the signal 5INT is applied, and the D-FF to which CL is applied to the clock input CL.
(20) can be read directly as input. That is, timing T,
, the count value of the fourth counter (9) is "2" to "
When it is outside the range of 10”, D −F F (14)
(15) and (16) cannot be set, that is, this state is determined as a state in which the rotation of the disk is significantly deviated, and the D-FF (20) stores this. and,
Since the symbols stored in the RAM are unreliable, the output Q of D-F F (20) can be used as a muting signal MUTE for preventing noise generation. On the other hand, the outputs Q of D-FF (14) and (16) are connected to the inputs of D-F F (21) and (22), respectively. That is, D -F F (21) and (22) are flip-flops that store control signals that control increases and decreases in the frequency division ratio, and the control signals are taken in once every 128 frames. Therefore, the "0" detection circuit (2) detects that the count value of the second counter (3) becomes "O".
3) is provided, and the output of the AND gate (24) to which the 'O' detection output DET 'O' and the timing output T I CL are applied, T and CL are D - F F (21)
(22) is applied to the clock input CL. In addition, the outputs, T, and CL are connected to the AN along with the muting signal MUTE.
The output PS "6" of the AND gate (25) is applied to the D gate (25) and is applied to the preset manual power P of the first counter (1). That is, the muting signal M
If a UTE occurs, the second counter (3) will be “
0', the first counter (1) and the second counter (1) are preset to "6" at timing t of the timing frame T6.
counter (3) is forcibly returned to its normal state.

Furthermore, the outputs of D −F F (21) (22), i.e.
A control signal (+) for increasing the frequency division ratio and a control signal <-) for decreasing the frequency division ratio are applied to the frequency division ratio control circuit (26). The frequency division ratio control circuit (26) is provided with a D-FF (27) to which a control signal (+) is applied and a D-FF (28) to which a control signal (-) is applied. ing. Further, the frequency dividing circuit (29) constitutes a part of the servo circuit of the disk motor and counts the synchronization signal PLCK of the EFM signal.
Consists of two stages of T-FFs, all T-FF outputs are “1”
By detecting this and setting D-FF (30), the output PLCKPD of D-FF (30) can be obtained as motor speed information.
D is used as a preset signal to set or reset 10 stages of T-FF, and D -F F
(27) It is applied to the clock input CL of (2B) and can be used as a capture signal for control signals (+) and (-).

The output of D-FF (2B> is a preset data signal to set the frequency division ratio to "587°", and the output of D-FF (27) is the preset data signal to set the frequency division ratio to "589°'" If D -F F (27) and (28) are not both set, the frequency division ratio will be "58B", that is, the output PLCKPD of the frequency division circuit (29) will be one per frame. The data that determines the frequency division ratio is preset for each frame, and the clock pulse φ4M (4,32
The phase is compared with the frequency-divided output of a frequency dividing circuit (not shown) that divides 18 MHz by 588, and the speed of the disk motor can be controlled based on the difference. Furthermore, D −F F (27)
The output of (28) is passed through the OR gate (31) to the signal P
The voltage is applied to the AND gate (32) to which LCKPD is applied, and the output R (+) (-) of the AND gate (32) becomes D.
-F Connected to the reset human power R of (21) and (22). Therefore, when D-FF (21) or (22) is set, the control signal (+) or (-) will change to D-FF depending on the generation timing of the divided output PLCKPD.
F F (27) (28) and AND
D-FF (2
1) (22) is reset.

Next, referring to FIG. 2, the operation shown in FIG. 1 will be explained in an easy-to-understand manner. As described above, the signal processing of the symbols of one frame is performed at timings T1 to T, and one RAM address check is performed during this one frame. That is, when the preset pulse PS is generated at timing t of timing T6, the contents of the second counter (3) are preset to the third counter (6), and the contents of the fourth counter (9) and D- F F
(14), (15), and (16) can be reset. Clock S for syndrome calculation during the same timing T6
When the clock pulse COMPCL is generated by INDCL, the third counter (6) and the fourth counter (9
) counts up. The first counter (1) and the third
When the count value of the counter (6) matches, the detection output DET
is output, but at this time, when the count value of the fourth counter (9) is "5" to "7", only the output CT (,) is "H", so it is outputted via the AND gate (12). TeD
-F F (15) and the fourth counter (9
) is between "2" and "4", the rotation of the disk becomes slow and the output CT<+> becomes H, and the AN
It is set in the D-FF (14) via the D gate (11), and on the - side, the count value of the fourth counter (9) is "8" ~
When it is "10", when the disk rotation becomes faster, the output CT(-) becomes "H" and the AND gate (13)
is set to D - F F (16) via . Furthermore,
When the fourth counter (9) has a count value other than "2" to "10" degrees, output CT. 3. CT. 3.CT,-,
None of them becomes 'H'', and D - F F (14) (
15) and (16) remain in the reset state. In this case, the output of the NOR gate (17) is "H", and the output T generated at timing t0 of timing T6
s CL is set to D −F F (20>) and the muting signal MUTE is output. The above operation is repeated for each frame, but the actual frequency division ratio is controlled once every 128 frames. In other words, the disk motor is normally servoed by accurate lock pulses from the crystal oscillation circuit, so the rotational speed does not drop significantly, so correction of jitter of about ±4 frames takes 128 frames. One time is sufficient.

Therefore, "OI?" occurs in the frame where the count value of the second counter (3) becomes "0°". Detection circuit (23
) detection output DET "O°", the output D0T, CL
is applied to D −F F (21) (22), and D −F
F (21) (22) is D −F F (14)<16
). Therefore, when the rotation of the disk motor has not recovered to its normal state within a period of 128 frames, a control signal (+) or -) is generated.

Also, at this timing, the muting signal M
When UTE occurs, the preset signal PS "6" is outputted, the first counter (1) is forcibly preset to "6", and the address state is returned to normal. −
On the other hand, in this frame, when the frequency dividing output PLCKPD is output from the frequency dividing circuit (29), D −F F (2
7) (28) takes in the control signal (+) or (=). When the control signals (+) and (-> are both "L II", the outputs of D -F F (27) and (28) are both "L'", and the frequency dividing circuit (29) has a frequency division ratio of 588. The data that determines the
+) is "H", the output of the D-FF (27) becomes "H", and the frequency dividing circuit (29) is preset with data with a frequency division ratio of 589, and the AND gate (3
2) output R(+)(-) is generated, and D −F F (
21) (22) is reset. Similarly, the control signal (
-) is "H11", the output of D-FF (2g) becomes "H", the frequency division ratio becomes 587, and D -F
F (21) and (22) can be reset.

In this way, the frequency division ratio is controlled once every 128 frames, making it possible to precisely control the disk motor.

(G) Effects of the Invention As described above, the present invention has the advantage that the circuit for detecting the write and read states of the RAM is simplified, and the number of elements when integrated is reduced. It becomes possible to delicately control the motor's servo circuit, and accurate CLV servo can be obtained.
D. The reliability of the playback device is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation. (1)...first counter, (2)...counter, (3)...second counter, (4)...49
Base counter, (5)...Hex counter, (6)...
・Third counter, (9)...Fourth counter, (
10)...-match detection circuit, (14) (15) (16)
...D −F F , (20)<21)<22)
...D-FF, (23) ...“0” detection circuit,
(Competition)... Frequency division ratio control circuit, (29)... Frequency division circuit.

Claims (1)

[Claims] 1. The symbol data obtained by demodulating the EFM signal read from the disk is stored in a RAM, the symbol data is read from the RAM and deinterleaved, and the data is stored in the disk based on the amount of data stored in the RAM. A signal processing circuit of a CD playback device that corrects the rotational speed of a motor includes a first counter that determines a write address of the RAM, a second counter that determines a read address of the RAM, and a second counter that determines a read address of the RAM. a third counter to which the contents of the counter (or the first counter) are preset; and a clock pulse is applied to the third counter to set the contents of the first counter (or the second counter) and the third counter A fourth counter that counts the number until the contents match, a plurality of flip-flops that store at predetermined timing control signals that increase or decrease the frequency division ratio according to the count value of the fourth counter, and a servo of the disk motor. A frequency division ratio control circuit that receives the output of the flip-flop using a frequency division output pulse of a frequency division circuit constituting the circuit, determines a frequency division ratio of the frequency division circuit, and resets the flip-flop. A signal processing circuit for a CD playback device.