JPS63213340A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63213340A JPS63213340A JP4700687A JP4700687A JPS63213340A JP S63213340 A JPS63213340 A JP S63213340A JP 4700687 A JP4700687 A JP 4700687A JP 4700687 A JP4700687 A JP 4700687A JP S63213340 A JPS63213340 A JP S63213340A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive layer
- base layer
- insulating film
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000000470 constituent Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 4
- 239000002344 surface layer Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000007711 solidification Methods 0.000 abstract 1
- 230000008023 solidification Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関し、特に絶縁膜を挾んで形
成される導電層間の導通部が、レジストを用いないで形
成されてい゛るものに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly relates to a semiconductor device in which a conductive portion between conductive layers formed with an insulating film sandwiched therebetween is formed without using a resist. .
第８図は、従来のレジスタにおける一実施例の断面図を
示す。図において、（１）はシリコン半導体基板よりな
る基層、（２）は基層（１）に例えば選択酸化法により
形成された二酸化シリコンより成る分離絶縁膜、（３）
は基層（１）及び分離絶縁膜（２）上に例えば熱酸化法
やＣＶＤ法により形成された二酸化シリコンや窒化シリ
コン等の非晶質絶縁膜より成る層間絶縁膜、（４）は眉
間絶縁膜（３）上に例えば真空蒸着法により形成された
多結晶シリコンより成る導電層、（５）は層間絶縁膜１
：１月こ明けられ、導電層（４）の一部を形成させて基
層（１）に接続し導通を図るためのコンタクトホールで
ある。なお、コンタクトホール（５）の形成は、層間絶
縁膜（３）上にレジスト層（図示せず）を塗布し、加熱
・乾燥させた後マスク合せして紫外線露光し、この後エ
ツチング処理することにより行なわれる。FIG. 8 shows a cross-sectional view of one embodiment of a conventional register. In the figure, (1) is a base layer made of a silicon semiconductor substrate, (2) is an isolation insulating film made of silicon dioxide formed on the base layer (1) by, for example, a selective oxidation method, and (3) is a base layer made of a silicon semiconductor substrate.
(4) is an interlayer insulating film made of an amorphous insulating film such as silicon dioxide or silicon nitride formed by thermal oxidation or CVD on the base layer (1) and isolation insulating film (2), and (4) is an insulating film between the eyebrows. (3) a conductive layer made of polycrystalline silicon formed by vacuum evaporation, for example; (5) an interlayer insulating film 1;
: Opened in January, this is a contact hole for forming a part of the conductive layer (4) and connecting it to the base layer (1) for electrical continuity. The contact hole (5) is formed by applying a resist layer (not shown) on the interlayer insulating film (3), heating and drying it, applying a mask, exposing it to ultraviolet light, and then etching it. This is done by
従来の半導体装置は上記のように構成され、基層（１）
と導電層（４）との導通がとられている。A conventional semiconductor device is constructed as described above, and includes a base layer (1)
The conductive layer (4) is electrically connected to the conductive layer (4).
従来のトランジスタは上記のように構成され、コンタク
トホール（５）の形成をいわゆるフォトリソグラフィ法
により行なっている。このため、層間絶縁膜（３）とレ
ジストとの間の密着性が悪いとアンダーカットを生じた
り、又、レジスト上に紫外線を照射してパターニングを
行なう工程で光の回折や干渉などによりパターン幅が広
がり正確なパターニングができないなどの欠点がある。The conventional transistor is constructed as described above, and the contact hole (5) is formed by a so-called photolithography method. For this reason, if the adhesion between the interlayer insulating film (3) and the resist is poor, undercuts may occur, and in the process of patterning by irradiating ultraviolet rays onto the resist, the pattern width may be reduced due to light diffraction or interference. There are drawbacks such as spreading and making it impossible to perform accurate patterning.
光の回折や干渉の影響を無くするためにレジスト厚みを
薄くするとピンホールができてレジストの役目を果さな
くなる等の問題点もあり、パターンが微細化する程これ
らの欠点が大きな問題となってくる。If the thickness of the resist is made thinner to eliminate the effects of light diffraction and interference, there are problems such as pinholes forming and the resist no longer functioning as a resist.As the pattern becomes finer, these drawbacks become more serious. It's coming.
更に、有機物質であるレジストは、その後の工程に進む
前に十分洗浄しておく必要があり、従って、それだけ製
造工程が増えてコストが上る欠点もある。Furthermore, the resist, which is an organic material, needs to be thoroughly cleaned before proceeding to subsequent steps, which has the drawback of increasing the number of manufacturing steps and increasing costs.
この発明は、上記のような問題点を解消するためになさ
れたもので、レジストを用いないで形成される導！１間
の導通部を有する半導体装置を得ることを目的とする。This invention was made in order to solve the above-mentioned problems. An object of the present invention is to obtain a semiconductor device having a conduction portion between 1 and 2.
この発明）こおける半導体装置は、絶縁膜を挾んで形成
される導電層と基層との導通部を、導電層、絶縁膜及び
基層にエネルギー線を選択的に加熱し、導電層又は基層
の加熱部と同質化して形成させたものである。The semiconductor device according to the present invention heats the conductive layer or the base layer by selectively heating the conductive layer, the insulating film, and the base layer with an energy beam to form a conductive part between the conductive layer and the base layer, which are formed by sandwiching an insulating film. It was formed by homogenizing the area.
この発明においては、導電層と基層との導通部がエネル
ギー線により両者を選択的に加熱し、導［層又は基層の
加熱部と同質化されるので、形成過程でパターン欠陥を
生じることがなく、かつ短時間で形成できる。In this invention, the conductive part between the conductive layer and the base layer is selectively heated by energy rays and becomes homogenized with the heated part of the conductive layer or the base layer, so no pattern defects occur during the formation process. , and can be formed in a short time.
第１図は、この発明の一実施例を示す断面図であり、（
１）〜（４）は上記従来装置と全く同一のものである。FIG. 1 is a sectional view showing an embodiment of the present invention.
Items 1) to (4) are completely the same as the conventional device described above.
（６）はレーザ光線、（７）は基層（１）と導Ｗ１層（
４）の導通部で、図に示すようＩこレーザ光線（６）を
導通部（７）が形成される範囲に照射して導電層（４）
１層間絶縁膜（３）及び基層（１）の表面層を融解した
後徐冷すると、再固化の際にシリコン単結晶成長が基層
（１）の表面層から導通部（７）を経て、更に導電層（
４）の融解部へと進み一体に単結晶化して形成される。(6) is the laser beam, (7) is the base layer (1) and the guiding W1 layer (
4), the area where the conductive part (7) is to be formed is irradiated with a laser beam (6) as shown in the figure to form the conductive layer (4).
When the first interlayer insulating film (3) and the surface layer of the base layer (1) are melted and then slowly cooled, upon resolidification, the silicon single crystal grows from the surface layer of the base layer (1) through the conductive part (7) and further. Conductive layer (
It advances to the melting part of 4) and is integrally formed into a single crystal.
なお、上記実施例では、シリコン半導体基板より成る基
層（１）と多結晶シリコンより成る導電層（４）との導
通部（７）が形成されるものを示したが、第２図に示す
他の実施例のように層間絶縁膜（３）を挾んで形成され
る導電層（４）間の導通部（７）であっても同様に形成
できる。また、基層（１）及び導電層（４）共単結晶シ
リコン或いは多結晶シリコンのいずれにより成るもので
あっても良く、同様に導通部（４）の形成ができる。In the above embodiment, the conductive portion (7) between the base layer (1) made of a silicon semiconductor substrate and the conductive layer (4) made of polycrystalline silicon is formed, but other examples shown in FIG. The conductive portion (7) between the conductive layers (4) sandwiching the interlayer insulating film (3) as in the embodiment described above can be formed in the same manner. Further, the base layer (1) and the conductive layer (4) may be made of either single crystal silicon or polycrystalline silicon, and the conductive portion (4) can be formed in the same manner.
更に、上記実施例では導通部（７）を単結晶シリコンと
して形成されるものを示したが、融解状態からの冷却速
度を早くし、多結晶シリコンとして形成させることもで
きる。Further, in the above embodiment, the conductive part (7) is formed of single crystal silicon, but it can also be formed of polycrystalline silicon by increasing the cooling rate from the molten state.
この発明は以上説明したとおり、絶縁膜を挾んで形成さ
れる基層と導電層間の導通部を、エネルギー線によりこ
れらを選択的に加熱し、導電層又は基層の加熱部と同質
化して形成されるものとすることにより、パターン欠陥
を防止して製造歩留りを向上できるとともに製造工程の
簡単化により安価な半導体装置が得られる効果がある。As explained above, this invention is formed by selectively heating the conductive part between the base layer and the conductive layer, which are formed by sandwiching an insulating film, with an energy beam to make them homogeneous with the heated part of the conductive layer or the base layer. By doing so, pattern defects can be prevented and manufacturing yields can be improved, and the manufacturing process can be simplified to obtain an inexpensive semiconductor device.
【図面の簡単な説明】
第１図はこの発明の一実施例を示す断面図、第２図はこ
の発明の他の実施例を示す断面図、第８図は従来のトラ
ンジスターにおける一実施例の断面図である。
図において、（１）は基層、（３）は眉間絶縁膜、（４
）は導電層、（６）はレーザ光線、（７）は導通部であ
る。
なお、各図中、同一符号は同一、又は相当部分を示す。[Brief Description of the Drawings] Fig. 1 is a sectional view showing one embodiment of the present invention, Fig. 2 is a sectional view showing another embodiment of the invention, and Fig. 8 is a sectional view showing an embodiment of a conventional transistor. FIG. In the figure, (1) is the base layer, (3) is the glabella insulating film, and (4) is the base layer.
) is a conductive layer, (6) is a laser beam, and (7) is a conductive part. In each figure, the same reference numerals indicate the same or equivalent parts.
Claims (5)
し、上記絶縁膜を、上記基層又は導電層の構成元素を含
む材料にて形成し、上記導電層、絶縁膜及び基層とをエ
ネルギー線により選択的に加熱して該部の絶縁膜を該部
の基層又は導電層と同質化し、該部に上記基層と導電層
とを接続する導通部を形成して成る半導体装置。(1) A base layer and a conductive layer formed by sandwiching an insulating film, the insulating film being formed of a material containing a constituent element of the base layer or the conductive layer, and the conductive layer, the insulating film, and the base layer A semiconductor device comprising selectively heating an insulating film with an energy beam to make the insulating film in the part homogeneous with a base layer or a conductive layer in the part, and forming a conductive part connecting the base layer and the conductive layer in the part.
リコンにより、それぞれ形成されていることを特徴とす
る特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the base layer is formed of single crystal silicon, and the conductive layer is formed of polycrystalline silicon.
ていることを特徴とする特許請求の範囲第１項記載の半
導体装置。(3) The semiconductor device according to claim 1, wherein the base layer and the conductive layer are made of polycrystalline silicon.
リコンによりそれぞれ形成されていることを特徴とする
特許請求の範囲第１項記載の半導体装置。(4) The semiconductor device according to claim 1, wherein the base layer is made of polycrystalline silicon and the conductive layer is made of single crystal silicon.
ていることを特徴とする特許請求の範囲第１項記載の半
導体装置。(5) The semiconductor device according to claim 1, wherein the base layer and the conductive layer are made of single crystal silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4700687A JPS63213340A (en) | 1987-03-02 | 1987-03-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4700687A JPS63213340A (en) | 1987-03-02 | 1987-03-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63213340A true JPS63213340A (en) | 1988-09-06 |
Family
ID=12763082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4700687A Pending JPS63213340A (en) | 1987-03-02 | 1987-03-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63213340A (en) |
-
1987
- 1987-03-02 JP JP4700687A patent/JPS63213340A/en active Pending
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