JPS63213050A - Parallel processing system - Google Patents

Abstract

PURPOSE:To shorten the parallel processing time by executing an estimated process in parallel with a process where the processing request given from an external device or the answer contents are analyzed and the propriety is decided for an estimated process before said processing request or answer contents are analyzed and the processing contents are fixed. CONSTITUTION:A processor 3-2 identifies a start instruction given from a CPU and shifts its own state in an active state. Then the processor 3-2 starts immediately the process when an I/O start command (start I/O) is received regardless of the contents (starting and resetting instructions to an I/O, etc.) of an operation instructed actually by the CPU and a fact whether the contents of the operation show the improper commands (start of unpackaged I/O, violation of specifications, etc.). While a processor 3-1 receives a processing request and an answer from the CPU and decides a state report given from the I/O or the data transferred from the I/O. Then the processor 3-1 sets its own state active and checks the abnormality.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parallel processing method, and particularly relates to a parallel processing method, and particularly to processing requests from an external device or responses from the external device when a processing request is made to the external device. The present invention relates to a parallel processing method that enables high-speed processing by making predictions in a processing device that receives data, analyzes these contents, and determines processing contents based on the analysis results.

[Conventional technology]

In conventional processing devices, when receiving a processing request from an external device or a response to a processing request to an external device, the processing device performs 5 content analyzes of the processing request or response, and then sequentially executes processing based on the analysis results. . Therefore, the processing time of the processing device for a processing request or response from one external device becomes longer, and the response to the external device that issued the processing request or response becomes slower. In addition, in order to improve the processing capacity of the processing device in order to speed up this response, (a) it is necessary to increase the hardware control part, which results in an increase in the price of the processing device. (B)
It is necessary to apply horizontal microinstructions to microinstructions, but as a result, the number of steps for developing microprograms increases.

FIG. 4 is a conventional processing flowchart in the input/output processing section for activation from the central processing unit.

Hereinafter, a case in which an input/output processing unit (hereinafter referred to as IOP) receives a startup instruction from a central processing unit (hereinafter referred to as CPU) will be described in detail. In response to a startup instruction from the CPU, the IOP reads command codes and command groups (channel command word CCW, etc.) stored in advance in the main memory (hereinafter referred to as MEM), executes them, and activates the magnetic disk device. , magnetic disk device, magnetic tape device,
Input/output devices such as printing devices or image input devices (I 1
0) and control them.

In FIG. 4, when a processing request (startup instruction) is received from the CPU (step 101), the CPU inputs a command code (for example, St, art■/○, Te
5tI/○, etc.), reading and decoding of startup ■/○ numbers, etc., determining the status of the own device, selecting and executing processing based on the results,
As a result of this processing, the newly acquired data (CCW in FIG. 4) is sequentially decoded, etc., and input/output operations are controlled. That is, when there is a processing request or response, the processing request or response is analyzed in step 102.
), status report from Ilo (step 110), and data transfer (step 111). When a startup command is issued from the CPU, the DAW (data word) and CAW
(channel word) from the MEM (step 103), details of the activation contents are analyzed, and abnormalities are checked (step 104).

If normal, reset the MEM reading circuit (step 112), report the status (step 113),
If it is abnormal, notify startup failure (step 114)
. If normal, Ilo is activated, the CCW is read from the MEM (step 105), and an abnormality check for this CCW is performed (step 106). If it is abnormal, a notification of startup failure is sent (step 115). If normal,
The CCW is saved (step 107), the I10 interface section is initialized (step 108), and a startup instruction is given to Ilo (step 109). Then, the process returns to the beginning of the routine and monitors processing requests and responses from the CPU and Ilo (step 101).

[Problem that the invention seeks to solve]

As described above, conventional IOP processing has the following problems.

(a) Data fetching from the MEM or ■10 interface unit is necessary for analyzing the content of processing requests or responses from the CPU or ■/○ (step 103 in FIG. 4). (b) The CCW, I10 status information, etc. given with the processing request or response may contain data that violates the specifications, so it is necessary for the IOP to check the format and content of these (see Step 106 in Figure 4).

Therefore, the processing time required to decipher and check the processing request or response from the CPU or Ilo becomes large, and the proportion of the entire ■○P processing time becomes relatively large. If the IOP also serves as part of the function of an input/output control device (IOC), it is necessary to further check command rejection conditions, and the above ratio increases further.

Therefore, as shown in Fig. 4, when the content analysis of the processing request or response from the CPU or ■/○ and the processing instructed by the processing request or response from the CPU or Ilo are performed sequentially, (i) The response time to activation from the CPU becomes longer. (11) The number of Ilo units that can be controlled simultaneously is reduced. (iii) In order to prevent the occurrence of overruns, more hardware controls are required. Problems such as this arise.

Conventionally, in other methods, (a) horizontal microprograms are applied to increase the amount of work in one cycle.

(b) When executing a conditional branch instruction, perform advance processing assuming whether the condition is satisfied or not. There are also examples of speeding up 10P processing by, for example, However, even in these methods, (
1) The number of steps required to design firmware increases. (11) The configuration of control hardware becomes complicated and the amount of hardware increases. There were other problems.

An object of the present invention is to improve these problems and reduce the time required to analyze processing requests or responses from external devices, thereby increasing the number of external devices that can be connected to the processing device at the same time, and preventing overruns from occurring. The object of the present invention is to provide a parallel processing method that can reduce the probability.

[Means for solving problems]

In order to achieve the above object, the parallel processing method of the present invention provides a first parallel processing system that executes predicted processing before analyzing the content of a processing request or response from an external device and determining the processing content.
and a second means for analyzing the content of an actual processing request or response from an external device to determine the validity of the predicted processing, and the processing of the first means and the second means is If they are executed in parallel and the prediction is incorrect as a result of content analysis, the second means notifies the first means to suspend the processing, and the state of the processing device is sent to the processing request or response from the external device. It is characterized by recovering to the same state as when it was received and restarting the process.

[For production]

In the present invention, before analyzing the content of a processing request from an external device or a response from an external device and determining the processing content, one process estimated in advance and the content of a processing request or response from an external device are analyzed. (a) If the prediction is correct, wait for the predicted processing to finish and issue a new processing request from the external device. Or monitor the occurrence of a response. (b) If the prediction is incorrect, the means for determining the validity of the prediction processing notifies the prediction processing execution means, and the state of the device is changed to the same as when the processing request or response was received from the external device. state and resume processing. That is, the present invention differs from the conventional method in that (1
) In response to a processing request or response from an external device, before determining the processing content by analyzing the content of the processing request or response, executing the predicted processing by another means, (
11) Determine the processing based on prediction and the validity of the prediction. This determines whether the processing request or response from the external device is processed within the processing time from receiving the processing request or response from the external device to completing the processing. To realize a high-performance processing device with a short response time to a processing request by reducing the proportion of time occupied by processing required for decoding the contents of the file.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an input/output processing device showing an embodiment of the present invention. In Figure 1, 1 is the cPU/MEM interface section, -1 is the MEM address register, and 1-
2 is a data register, 2 is a trigger queue management section, 3-1
．． 3-2 is a processor that executes microprograms while mutually synchronizing each checkpoint; 4-
1 and 4-2 are control memories that store microprograms executed by the processors 3-1.3-2, respectively; 5-1.5;
-2 is a memory for storing control information such as channel command words (CCWs) managed by the processors 3-1 and 3-2 and the processing progress status of the CCWs; 6 is a CPU/M
EM interface section and processor 3-1.3-2. Internal bus 9 interconnecting memories 5-1 and 5-2 is ■
/○ interface control unit, 7 is ■ /○ interface control unit 9 and processor 3-1.3-2. An internal bus 8-1.8-2 interconnects the memories 5-1 and 5-2, and is a progress display register that indicates that the processor 3-1.3-2 has completed processing up to the checkpoint. .

Next, the operation of the apparatus shown in FIG. 1 will be explained.

When the CPU/MEM interface unit 1 or I10 interface unit 9 detects a processing request or response,
A trigger code responsive thereto is sent to the trigger queue management section 2. Processing requests and responses from the CPU include activation instructions and interrupt acceptance responses, and processing requests and responses from ■/○ include status information reports, data transfer requests, and the like.

The trigger queue management unit 2 has first-in, first-out (FIFO) type trigger storage registers corresponding to microprogram operation levels (processing levels), and the processor 3-1 processes processing requests or responses. It is possible to read out and process the registers sequentially starting from the register with the highest priority.

Processor 3-1.3-2 is idle,
Active, Wait,
The processor is in one of four trouble states, and both processors operate with clocks synchronized, for example, by receiving clock signals from the same oscillator. Here, a trouble state is a state in which the OP is inoperable due to a hardware failure, and an active state is a state in which processing is being executed based on a processing request or response from the CPU or Ilo, and a wait state is a state in which the OP is inoperable due to a hardware failure. is a state in which it has finished processing based on a processing request or response and is waiting for the other processor to finish its processing. An idle state is a state in which neither of the above is the case, and CPIJ, Ilo It is in the state of waiting and monitoring processing requests or responses from.

FIG. 2 is a state transition diagram of both processors in FIG. 1.

As shown in FIG. 2 (1), when the processor 3-1 is in an idle state, it accesses the trigger queue management unit 2, sets up a flag that indicates the presence or absence of a processing request or response, reads out this flag, and analyzes it. By doing so, it is determined whether there is a processing request or response.

When the processor 3-1 receives a valid trigger code from the trigger queue management section 2, it updates its own state from an idle state to an active state.

The trigger code is set in the processor 3-2 at the same time as it is taken into the processor 3-1.

As shown in FIG. 2 (2), the processor 3-2 does not issue a trigger code read request.
-1 monitors the state of the processor 3-1, takes the transition from the idle state to the active state of the processor 3-1 as a trigger, transitions its own state to the active state, and sends the trigger code read out to a predetermined location within the own processor. The trigger code is analyzed and a predetermined process is started based on the contents of the trigger code.

Next, the memory 5-1.5-2 is connected to the processor 3-1.3.
-2 is divided into an area that holds common contents and an area that holds individual contents. Processor 3-1 or 3-2 is CPU/MEM interface unit 1 or I1
When data is imported from an external device via the 0 interface unit 9, the memory 5-1 or 5-
The same data is captured not only in the area holding the common contents of the memory 5-2 or 5-1 of the other processor side but also in the area holding the common contents of the memory 5-2 or 5-1 on the other processor side.

FIG. 3 is an operation flowchart of the processor of FIG. 1. FIG. 3 (1) shows the operation of the processor 3-1, in which the processors 3-1 analyze the contents of processing requests or responses from external devices, determine the processing contents, and 3-2 determines whether the prediction of the processes executed in parallel is correct. Further, FIG. 3 (2) shows the operation of the processor 3-2.
2 executes the predicted process immediately upon receiving the process request or response. FIGS. 3(3) and 3(4) show the suspension instruction sending process and the process upon receiving the suspension instruction, respectively.

As a specific example, a case will be described in which the OP receives a startup instruction from the CPU.

(b) Start-up instructions from the CPU include I10 start-up, reset instructions, and status report instructions. The processor 3-2 is
Upon identifying the activation instruction from the CPU, that is, upon identifying that the partner state has become active (step 14).
1), after transitioning its own state to active (step 14
2), the contents of the operation actually instructed by the CPU (
For example, r/○ startup instructions, reset instructions, status report instructions, etc.) and regardless of whether the contents of the operation are illegal commands (startup to an unrealized device 10, violation of specifications, etc.), the ■/○ startup command ( St, arLIlo) is received. This processing includes (i) initialization of the relevant portion of the memory 5-2 that stores the state of the own processor, and (11) reading a command (CCV) to the main memory (step 143).

On the other hand, when the processor 3-1 receives a processing request and response from the CPU (step 121), it analyzes the processing request and response (step 122).

This analysis identifies whether it is a status report from Ilo, a data transfer, or an interrupt acceptance.

Next, after reading the DAW and CAW from the MEM (step 123) and changing their state from the idle state to the active state (step 124), detailed analysis of the startup contents and abnormality check are performed (step 125). After the abnormality check, if there is an abnormality, as shown in Figure 3 (3),
Performs processing to send an interruption instruction. First, send F to the other processor.
It sends the W execution address (step 131) and issues an interruption instruction to the other processor (step 132). Then, the process continues (step 133).

That is, when the processor 3-1 enters the active state, (1) the operation command to be started is executed by the I10 start command (Start) executed by the processor 3-2.
l10) Check whether or not (11) Next IOP
and the status of the channel for which activation was instructed, Ilo (can accept activation, in use, failure, unimplemented), and (m
) Checks the sufficiency of the specifications of data indicating details of the activation instruction (for example, does the CCW storage address indicate an 8-byte boundary, etc.).

(b) In order to read the CCW, the processor 3-2
Set the CCW address in the address register 1-1 in the CPU/MEM interface section 1, and then
The CCW monitors the status of the EM interface section 1 and
Data register 1 in PU/MEM interface section 1
Wait for it to be read out at -2. Next, processor 3-2
When detecting that the CCW has been read into the data register 1-2, it stores the CCW in the memory 5-2 and reads the CCW.
A progress display register 8-2 is used to indicate fetch completion.
Add 1 to the contents of. At this time, the processor 3-1 or 3-2 connects to the memory 5-1 via the internal bus 6 or 7.
Or, when writing data to 5-2, the same data is simultaneously written to memory 5-2 or 5-1 on the other processor side.
Therefore, the CCW fetched from the MEM by the processor 3-2 is also stored in the memory 5-2.

(c) The processor 3-1 checks that there is no error in the data content read from the MEM, and that the content of the startup instruction from the CPU matches the content currently being processed by the processor 3-2. , then performs synchronization processing with the processor 3-2 (step 134). That is, the processor 3-1 performs synchronization by referring to the progress display register 8-2 of the processor 3-2.

If the progress display register 8-2 does not indicate completion of CCW fetch, the processor 3-1 registers the progress display register 8.
register 8 until -2 indicates CCW fetch complete.
-2 reading and checking are repeated.

The processor 3-1 has the progress display register 8-2 set to CCW.
When it is confirmed that the fetch completion is displayed, the progress display register 8-1 of the own processor is updated, and at the same time, the flag register of the own processor is reset, and then the next process is started.

Processor 3-2 also registers CCW fetch completion in register 8.
-2K is displayed, and at the same time, synchronization processing similar to that described above is performed (step 134).

(d) After confirming that the processor 3-1 has updated the register 8-1 and synchronizing with the processor 3-1, the processor 3-2 saves the CCW in preparation for retry processing, etc. (Step 144).

On the other hand, the processor 3-1 retrieves the CCW from the memory 5-1 and performs an abnormality check on the CCW (step 1
2G).

Here, when an abnormality is detected, as shown in FIG. 3 (3), the FW (firmware) execution address is sent to the partner processor 3-2 (Step 131), and the step 132 is issued to issue an interruption instruction to the partner processor. ), processing continues (step 133).

Further, in steps 143 and 144 of FIG. 3(2), when the processor 3-2 receives the above-mentioned interruption instruction, the processor 3-2 changes the control table to the state of the immediately previous synchronization point, as shown in FIG. 3(4). step 151), update the microinstruction address (step 152), and restart the process (step 152).
Step 153).

Next, the processor 3-2 waits for the processor 3-1 to display the completion of the command abnormality check in the progress display register 8-1, and then issues an initialization instruction to the I10 interface control unit 9 and a startup instruction to Ilo. (Step 145).

(E) After completing the scheduled processing for the processing request or response, each processor 3-1, 3-2 displays its own processor in a wait state and monitors the other processor's transition to a wait state (step 127, 128,1.
46,147).

When the processor 3-1.3-2 in the wait state detects that the other processor has also entered the wait state,
Step 1 to transition the processor state to idle state
29, 1.48), wait for the next processing request or response (
121, 141).

(F) When the processor 3-1 detects that the processor 3-2 is performing a process different from the actual instruction, the processor 3-1 changes the process execution routine (FW) to be executed by the processor 3-2, as described above. After storing the address AO in a predetermined location of the processor 3-2, it instructs the processor 3-2 to suspend processing.

For example, when the microprogram of the processor 3-2 is started from the CPU, the startup content is I10 startup, and the actual instruction is different from the actual instruction. C.P.
The startup content from U is not I10 startup but a reset instruction, or the first CCW is TIC: ] command
This is a case where it is detected that there is a program check factor in the CCW, such as Transfer in Command). In this case, the processing execution routine to be executed by the processor 3-2 includes, for example, IOP reset, error processing for startup, and the like.

Further, when the processor 3-2 receives an instruction to suspend processing from the processor 3-1, the processor 3-2 returns the state of its own processor to the state in which it received the processing request or response from the external device, as described above. Processing starts from the address AO set by No.1.

During this time, both processors 3-1 and 3-2 maintain the active state, and thereafter perform the same operations as when the content being processed by the processor 3-2 is correct.

(g) Also, in the middle of processing, the processor 3-2
For example, even if there is an error response from the EM during CCWC F-etch, the processor 3-2 will send the microprogram address to the processor 3-1 to cause the processor 3-1 to execute MEM error processing, as described above. After setting at a predetermined location, an interrupt instruction is given to the processor 3-1, and thereafter the same processing as that of the processor 3-1 in the above (v) as shown in FIG. 3(3) is performed. Further, the processor 3-1 also performs the same processing as the processor 3-2 in (v) above as shown in FIG. 3(4).

(H) Regarding booting other than from the CPU, for example, 10
When P receives a response from Ilo while P is waiting for a response from Ilo to complete command processing, processor 3-
2 immediately starts command chain processing, and
The processor 3-1 performs command chain processing based on (1) whether a command chain is specified, (11) whether the previous command has completed normally, or performs channel program termination processing (report information to the CPU). editing, CPU
(interruption, etc.).

In this way, the processor 3-1.3-2 executes the prediction process and the prediction content check in parallel while maintaining mutual synchronization, just as when receiving the activation request from the CPU.

(S) Therefore, if the content of the processing request or response to the IOP matches the content of the processing being executed by processor 3-2, processor 3-1 or 3-2, whichever is longer, It can be completed in the same processing time.

In this embodiment, the case where the present invention is applied to an IOP has been described, but the present invention is not limited to an IOP, and can be applied to a CPU, a CCU, etc.
Of course, the present invention can be applied to other devices such as (communication control device).

Moreover, the processor 3-1 in the embodiment. ．． 3-2 to C
PU, and one CPU realizes the functions of controlling the CPU/MEM interface section 1, trigger queue management section 2, and I10 interface section 9, and the memory 4-1.
．． It goes without saying that the present invention can also be applied to a system in which 4-2.5-1.5-2 is used as a MEM, and other external devices include another CPU, Ilo, etc.

In addition, in the embodiment, the case where the number of processors is two has been explained, but by increasing the number of processors, multiple processes (I10 startup success, startup instruction, It is also possible to improve the prediction accuracy rate by executing the IOP (interrupt pending, etc.) regarding the input/output device (IOP).

Furthermore, as for the processing of the processor 3-2 in the embodiment, the processing content for the trigger code is determined when the microprogram is executed in the embodiment, but in some cases, for example, command (CCW) At the time of termination, the processor itself determines whether to perform command chain processing or input/output operation termination processing (raises an interrupt to the CPU and reports termination) based on the type of CCW that has completed its operation. In this embodiment, the processor 3-2 decodes the detailed contents of the processing request or response from the external device and part of the state of the own device and selects the process to be executed, thereby improving the prediction accuracy rate. It is also possible.

In this way, in the present invention, before analyzing the content of a processing request or response from an external device and determining the processing content, one process assumed in advance and the content of the processing request or response from the external device are analyzed. Since the process of analyzing and determining the validity of the prediction process is executed in parallel, the proportion of time spent analyzing the contents of the process request or response in the processing time for the process request or response from the external device is This can reduce the processing time of the processing device for one processing request or response.

In particular, the present invention provides the following advantages: (1) When the frequency of appearance of detailed contents in processing requests or responses from external devices is large, (11) Rate of processing for determining detailed contents of processing requests or responses from external devices. If there are many (iit
) If applied to processing with characteristics such as when processing must be performed on the assumption that data that violates the specifications will be mixed in with data that specifies the details of a processing request or response from an external device, it will be extremely useful. Great effects can be expected.

〔Effect of the invention〕

As explained above, according to the present invention, the processing time of the processing device for processing requests or responses from external devices can be shortened, so the number of external devices that can be connected simultaneously to this processing device can be increased. Furthermore, by applying the present invention to devices that require real-time processing, the probability of overrun occurrence can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a hardware configuration diagram of an input/output processing device showing an embodiment of the present invention, FIG. 2 is a state transition diagram of the input/output processing device in FIG. 1, and FIG. 3 is the input/output processing shown in FIG. 1. Processing Flowchart of Device FIG. 4 is a processing flowchart of a conventional input/output processing device. 1: Interface control unit between IOP and CPU/MEM, 2: Trigger queue management unit that manages the trigger code to be processed next by the processor, 3-1.3-2: Startup from CPU under microprogram control 4-1.4-2: Control memory for storing microprograms executed by processor 3-1.3-2; 5-1.5-2: MEM for channel command words, etc.; A memory for storing read information from Ilo, input information from Ilo such as device status bytes, execution status of commands being processed by the processors 3-1 and 3-2, etc.
6, 7: Internal bus, 8-1.8-2: Processor 3-1
．． Register that displays the status of 3-2, 9: IOP and Il
an interface control unit between the Part 3 1) Operation of processor 3-1 (2) Operation of cassette 3-2 (Note) DAW: Operation contents, activation target cha CAW: CCW storage address specified, I10 specified.

Claims (1)

[Claims] (1) A processing device that receives a processing request from an external device or a response to a processing request to an external device, analyzes the content of the processing request or response, determines the processing content based on the analysis result, and performs the processing. In this step, before analyzing the above contents and determining the processing contents, a first means for executing the predicted processing and the contents of the actual processing request or response from the external device are analyzed to perform the above predicted processing. and a second means for determining validity, executes the processing of the first means and the second means in parallel, and when the prediction is incorrect as a result of the content analysis, the second means The method is characterized in that the first means is notified of the interruption of the processing, the state of the processing device is restored to the same state as when the processing request or response was received from the external device, and the processing is resumed. Parallel processing method.