JPS61120256A - Channel control system - Google Patents

Abstract

PURPOSE:To perform channel control with high efficiency by using plural microprocessors for multi-channel control and performing the control of an I/O interface as well as the control of a CPU and an MSU interface respectively. CONSTITUTION:The 1st microprocessor MPC1 which gives processing successively to many channels in the prescribed order is provided together with the 2nd microprocessor MPC2 which executes properly the processing requests for each channel. The control lines of many input/output devices I/O are connected to the MPC1 with the data lines connected to a data buffer storage DBS respectively. The MPC2 controls the interface signal between a central processing unit CPU and a main memory MS and channels respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling a plurality of channels using a microprocessor.

[Conventional technology]

In a general-purpose computer system, a central processing unit CPU, a main storage unit MSU, and a large number of input/output devices I10 are connected as shown in FIG. 4 via a main control unit MCU and a channel device CH. Channel CH and input/output device I1
In this example, it is assumed that there are n+1 0's, and this number is a large number such as 16,32°64, for example.

The operation of the channel is as shown in Figure 5.
Activation of 10 instructions, ■ CCW (Channel) from MSU
l Command Word) Fetch, ■I1
0 device startup, ■Data transfer, ■CCW fetch by data chaining, ■Data transfer, ■CCW quench by command chaining, ■I10 startup by command chaining (waiting for recombination), ■(10 These are interrupts, acceptance of processing requests from I10 equipment, and (1) command chaining (same as (2)).

[Problem that the invention seeks to solve]

The operation of such channels is carried out by the microprocessor MPC.
To perform this control, simply provide one MPC for a large number of channels. However, this method is insufficient. In other words, among the channel functions, monitoring of processing requests from 110 devices must be performed constantly, while data transfer is performed only after the transferred data has been collected and is therefore intermittent. , single-MPC
method is not sufficient.

In the past, there have been examples in which channel processing is divided by function and configured with a plurality of microprocessors. That is, control of the 0 interface and the interface with the CPU, and control of access to the main memory and subchannels are assigned to separate microprocessors. In this case, one channel requires two microprocessors, and 2N (N is the number of channels) of control memory is required. Also, divide the channels of the entire system into groups, and let the number of groups be m and l.
It is also possible to realize this by using a +m micropro sensor. In recent years, there has been an increasing demand for larger scale systems, that is, an increase in the number of channels and faster channel processing. A one channel two microprocessor or an N channel l+m microprocessor increases the amount of material. An N-channel 1 microprocessor cannot sufficiently handle high speeds.

The present invention has been made in view of these points, and by providing a plurality of microprocessors and performing processing by function,
The purpose is to provide appropriate control of channel operations.

[Means for solving problems]

The present invention provides a control method using a microprocessor for a plurality of channels that connect a central processing unit, a main memory, and a large number of input/output devices. A plurality of microprocessors are provided, including a first microprocessor and a second microprocessor that controls signals of an interface between the central processing unit and the main memory, and the channels, and the first microprocessor sequentially processes each channel.
Processing requests generated for each channel are processed periodically by the second microprocessor, and the processing requests generated for each channel are processed by the second microprocessor at regular intervals. The transmission of processing requests and control information between the second microprocessors is performed by registers provided corresponding to channels.

〔Example〕

To explain it with the drawings, as shown in FIG. 1, the present invention includes a first microprocessor that sequentially processes a large number of affiliated channels in a predetermined order (controls all signals of the I10 interface other than data transfer). MPC1 and a second microprocessor MPC2 are provided which execute processing requests generated for each channel at any time. A large number of input/output devices 10 have their control lines (tag lines) connected to the MPCI, and their data lines connected to the data block storage DBS. The DBS is a data buffer between the MS and the I10, and temporarily stores the I10 data of each channel for each channel. RG is a group of registers, which includes a large number of registers corresponding to each channel, and stores control information for each channel, including DBS pointers for each channel and control information for communication between MPCI and MPC2.

L:S (Loca I S Lorage) is M
A storage area provided between PCl and MPC2.
It stores processing request codes from the MPC2 to the MPC2, and can be accessed from both of them.

As shown in FIG. 2, the microprocessor Mpci executes processing on the channel CHO" CHn at sequential timings t Q w t n. This can be done as follows. In general, the microprocessor has a control memory. CS (ControlStorage
e), the MPCI cs stores microprograms for various processes for each channel, and in this storage, the microprograms for each type of processing, regardless of the channel, are stored in the C8. The system is set such that the address of O8 is set to address i - i + a, and that of other processes is set to address j - j + b of O8. Then, as shown in FIG. 3(a), address counters CHO, CHI, . . . C
Hn is provided, a CS address determined by determining the processing content of each channel (the start address of the relevant microprogram or routine, such as 1.j described above) is set in the corresponding counter, and timings tQ, tl, . . .
・・・・・・Sequential counter CHO, CHI, ・・・・・・
, execute the microinstruction that reads and outputs C3 sequentially using the values of those counters, simultaneously increments the value of the counter, and repeats the above operation to perform the process shown in Figure 2. can do. FIG. 3(b) is a diagram illustrating the processing status of MPCI in another format. The processing is performed in the order of ■, ■, .

I10 activation, data transfer, and termination are processes performed by CHO, and each consists of multiple steps (microinstructions).

FIG. 3C shows the processing of channels in a further different manner.

The work performed by the microprocessor MPCI is phase 1 in FIG. 5, that is, taking in processing requests from the I10 device and instructing the I10 device to start up. In this example, data transfer is performed by hardware, so the work performed by the microprocessor MPC2 is shown in Figure 5.
, (2), and updating of the store data address and remaining hide count number performed at the time of data transfer to the MSU. Note that when controlling 16 channels, for example, the data transfer control circuit performs parallel processing in units of 4 channels to increase the transfer speed between the I10 device and the channels. I
Since we do not know when there will be a 10 request, MPCI uses all l1
0 (channel) is always scanned at regular intervals. When a processing request is received from an I10 device, the MPCI scan
10 (channel) - It is detected when it comes around,
MPCI has local storage LS and register group R
Write the processing request to the corresponding channel part of G (processing request code to the former, control information to the latter). When a processing request from the device is written to the LS and RG, the microprocessor MPC2 starts executing the processing (this is known by the means described later), contacts the CPU or MS, and exchanges data with the MS, for example. Start the transfer and send the result to R
G is written, thereby data transfer between the DBS and the concerned I10 is performed.

Channel number 0 is schematically shown as CNTl and CNT2.
,1,2. Timing LO, t corresponding to...
l, t2. In . means 2 for assigning execution priorities to respective requests;
MPC by processing request selected according to its priority.
Means 3 is provided for reading the register group RG when the DBS 2 or DBS starts operation and updating the register group RG after the operation is completed. This means 1 controls the data transfer between the I10 device and the channel during data transfer of each channel, and updates the data address and number of bytes in the LS and updates the number of bytes to the MS under the control of the MPC2 program started by means 2. Activate access.

The CPU or MPC
The MPC2 controls the interface of the CPU or MSU from I through the register group RG. MPC2 is I
During LO startup, command chaining, and data chaining, the CCW is fetched from the MSU and various checks are performed.

Data transfer between channels and 110 may be controlled by a microprocessor, but since the amount of data is large, it can be processed faster by using dedicated hardware, which is even faster by parallel processing on multiple channels. The speed can be increased. Since the control on the MSU side or the CPU side operates less frequently per channel than the control on the Ilo side, multiple channels may be serially controlled. Further, if a priority circuit is provided for processing requests from the MPCI to the MPC2, the priority order can be changed depending on the data storage condition of the DBS. Processing requests from MPC2 to MPC1 can be written at any timing, and MPCI
is read and what to do with it is determined at its own timing.

FIG. 6 shows a detailed block diagram of this device which performs periodic control sequentially in the order of channel numbers. The register group can be roughly divided into (11DBS pointers) for each channel, (2) communication control information between the microprocessors MPCI and MPC2,
and (3) data is stored and read every time the channel number is updated (+1), and its contents are updated. For example, when a certain number of bytes or more of data is stored or consumed, the periodic control section issues a processing request to the non-periodic control section, and the non-periodic control section stores the data in the main memory. and issues a processing request to MPC2. Alternatively, after issuing a processing request to the MPC 2, the output data is sequentially stored in the DBS while reading data from the main memory. In addition, the readout and update timing of the register group is synchronized with the readout and update of the MPct CS address and the readout and update of the MPCI CS data.
By storing processing instructions to CI and presence or absence of processing requests from MPCI to MPC2 in a group of registers,
Communication between MPCI and MPC2 becomes possible. In this case, detailed information is received and passed using an LS (local storage) provided for each channel.

The MPCI also periodically controls the tag line on the IO interface of each channel in sequence, and starts up the ro device and
Execute the sequence of processing requests from the device. The IO device address, ■0 command, or ■○ status at this time is stored in the LS of each channel.

FIG. 7 is a block diagram of the irregular control section. The register group, DBS, and LS in FIG. 6 are physically the same as those in FIG. ), but regular access should always be prioritized. That is, if there is no regular access, non-regular access is enabled continuously. The non-periodic control section can be roughly divided into (1)
The processing unit of MPC2 and (21become the pre-processing or post-processing unit of MPC2 processing.When a processing request to MPC2 is generated by activation from the regular control unit or CPU,
Channel control information is read from the register group based on the channel number, and the CS address control section of the MPC 2 is activated to start processing of the MPC 2. At the end of a certain process, control information is updated or initialized and stored in a register group. During processing of MPC2, access to LS or access to MS is performed. −
When data is transferred between the MS and the DBS of the channel, during Read 0operation, the data to the DBS is aligned (as instructed by the CCW) and then the MPC2 is activated, and a write operation (Write 0operation) is performed. Sometimes it takes a wake-up to the MPC2 to fetch data from the MS and then align the data and store it in the DBS. In this case, the DBS pointer and lower bits of the data address are read from the register group and updated by the data alignment control section.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of microprocessors are used for multi-channel control, and one controls the I10 interface, and the other controls the CPU and MSU interfaces. Efficient channel control becomes possible, such as being able to quickly capture data and smoothly processing data transfer with the MSU.

[Brief explanation of drawings]

Figure 1 is a block diagram explaining the present invention, Figures 2 and 3 are
5 is an explanatory diagram of the operation of the processor, FIGS. 4 and 5 are explanatory diagrams of channels, and FIGS. 6 and 7 are block diagrams showing details of the main parts of FIG. 1. In the drawing, CPU is the central processing unit, MSU is the main storage unit, and I
Lo is an input/output device, MPCl and MPC2 are first and second microprocessors, and RG and LS are registers.

Claims (1)

[Claims] In a control system using a microprocessor for a plurality of channels that connect a central processing unit, a main memory, and a large number of input/output devices, the microprocessor is controlled by signals for interfaces between the channels and the input/output devices. A first microprocessor for controlling a plurality of microprocessors and a second microprocessor for controlling signals of an interface between the central processing unit and the main memory device and the channels, and the first microprocessor sequentially processes each channel. The processing requests generated for each channel are processed by the second microprocessor at regular intervals, and the processing requests and control information between the first and second microprocessors are transmitted by registers provided corresponding to the channels. A channel control method characterized by: