JPS63211168A - Record detecting circuit - Google Patents

Abstract

PURPOSE:To use crystal oscillation or the like for a reference clock, to easily attain LSI and to miniaturize a recording detecting circuit by constituting all circuits such as a counter and gates in the detecting circuit of digital circuits. CONSTITUTION:A signal 17 read out from a recording medium is inputted to FFs 4-6 constituting a shift register and successively transferred based on a reference clock A 18. The outputs of the FFs 4-6 are inputted to EORs 8, 9 in a short time data detecting part 1, signals corresponding to the leading and trailing edges of the clock A are outputted and the contents of a counter 10 are counted up by the inverse signal of the clock A. An output signal 22 from the detecting part 1 is inputted to a counter 12 in a long time data detecting part 2, the contents of the counter 23 are counted up by a reference clock B 23 and an output 25 from an FF 13 and the inverse output are respectively inputted to FFs 14, 15 in a continuous time detecting part 3. The FFs 14, 15 count up the output of the detecting part 2 at a reference clock C 26 and a detecting signal 29 is outputted from the FF 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a record detection circuit, and more particularly to a record detection circuit suitable for use in a signal demodulation circuit of a magnetic tape recording device.

[Conventional technology]

2. Description of the Related Art In magnetic tape recording devices and the like, there is a record detection circuit that detects data blocks, tape marks, etc. from signals read from a medium.

In a conventional record detection circuit, a capacitor is charged and discharged according to the cycle of a read signal, and by reaching a predetermined voltage, it is detected that the read signal matches the data cycle of a data block, tape mark, or the like. Further, the capacitor is charged while the data periods match, and by detecting that the voltage of the capacitor exceeds a predetermined voltage for a predetermined period of time, it is determined that the read signal is a record (data block, tape mark, etc.).

As this type of circuit, for example, Japanese Patent Publication No. 51-4576
No. 7 is mentioned.

[Problem that the invention seeks to solve]

The conventional method described above consists of analog circuits such as capacitors, resistors, and comparators, so it requires high integration and
Difficult to implement into LSI. In addition, variations in detection characteristics occur due to variations in each element, variations in power supply voltage, variations in temperature, and the like.

An object of the present invention is to provide a record detection circuit that is suitable for LSI implementation and has less variation and variation in detection characteristics.

- [Means for solving the problem] The above purpose is to check that the period of the read signal matches the data period using a reference clock and a counter, and to check that the duration of the detection signal is longer than a predetermined time. This is achieved by using a method of checking the value using another counter.

[Effect]

By configuring the record detection circuit with all digital circuits such as counters and logic gates, it can be easily integrated into an LSI and can be significantly miniaturized. Further, by using the output signal of a highly accurate oscillator such as a crystal oscillator as the reference clock, extremely stable detection characteristics can be achieved.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 2 shows a block diagram of the record detection circuit, FIG. 1 shows its specific circuit, and FIG. 3 shows signal waveforms 8 of each part in FIG.

As shown in Fig. 2, the record detection circuit includes a short-cycle data detection unit that detects when the cycle of the read signal is shorter than the data cycle, and a long-cycle data detector that detects when the cycle of the read signal is longer than the data cycle. and a duration detection section that detects that the read signal, which is not detected by either of the two detection sections and is confirmed to match the data period, continues for a predetermined period of time or more.

The specific operation will be explained using FIGS. 1 and 3.

The readout signal 17 read out from the recording medium and converted into an NRZI signal is sent to a flip and flop 4 (hereinafter referred to as F, F).
, abbreviated as). F, F, 4.5.6 are shift registers, and are sequentially sent by the reference clock A18. Shift register (F, F, 4-6
) is input to E OR8,9, and E OR8,9
The output 1920 is a signal corresponding to the rising edge and falling edge of the read signal 17.

The counter 10 of the short period data detection section 1 is counted up by the inverted signal of the reference clock A18, outputs a carry signal 21, and stops.

When the output signal 19 of the EOR 8 is output, a preset LOAD value ('12') 30 is loaded into the counter 10, and counting starts again. At this time 1AN
A pulse is output to the output signal 22 of the D gate 11. If the inversion period of the read signal 17 is shorter than the data period, the carry signal 21 is not output.

That is, if the inversion period of the readout signal 17 is longer than a predetermined time, that period is directly input to the long-period data detection section 2 as the pulse period of the signal 22.

The counter 12 of the long-period data detection section 2 is incremented by the reference clock B23, and stops when the carry signal 24 is output. The AND' gate 11
When the output signal 22 of
The AD value ('10') 31 is loaded into the counter 12, and the counter 12 starts counting again.

The carry signal 24 of the counter 12 is F, F, 13
is connected to the D input and set input of -10,000, F
.

The output 20 of the EOR 9 is connected to the trigger input of F, 13. Therefore, when the inversion period of the read signal 17 is longer than the data period, the carry signal 24 is output, and the output signal 25 of F, F, 13 becomes 1'.

On the other hand, if the inversion period of the read signal 17 is less than the predetermined time, the carry signal 24 is not output and F, F, 13
The output signal 25 of is 10.

That is, the output signal 25 of F, F, 13 becomes ``0'' when the inversion period of the read signal matches the data period, and conversely becomes 1 when it is shorter or longer than the data period.

The duration detecting section 3 includes a counter 14 that counts the 10' time of the signal 25, and a counter 15 that counts the 1' time T of the signal 25.

The counter 14 receives a predetermined LOA when the signal 25 is 11'.
It is stopped with D value ('8') 32 loaded. When the read signal matches the data period, the signal 25 becomes 0 and the counter 14 starts counting up. When the read signal that matches the data period continues for a predetermined period of time or more, the counter 14 outputs a carry signal 27. When Carry No. 15 27 is output, F, F,
16 is set and the detection signal 27 becomes 1'. First, is it detected that a read signal that matches the data cycle has been read for a predetermined period of time or more, and that the read signal is a record such as a data block or tape mark? Detected.

Counter 15 is opposite to counter 14 when signal 25 is 1.
11, and it is detected that no read signal is input for a predetermined period of time, and the recording is completed? To detect.

According to this embodiment, in the range where the period of the read signal is determined to be the data period, the L OA D (130
, and the LOAD value 31 of the counter 12 can be easily changed by changing the LOAD value 31 of the counter 12.
LOAD value 62, counter 15 LOAD value 35 total 3
[Effects of the Invention] According to the present invention, the record detection circuit can be completely digitalized, so there is less variation and variation in the detection characteristics. Significant downsizing can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a block diagram of FIG. 1, and FIG. 6 is a diagram showing each part of FIG. 1. FIG. 1... Short cycle data detection section, 2... Long cycle data detection section, 3... Duration detection section, 4, 5.6.13.16... Flip, flop, 7
...Inverter, 8,9...EOR gate, 10,
12.14.15... Counter, 11... AND gate, 17... Read signal, 18... Reference clock A123... Reference clock B1 24... Reference clock C129... Detection signal.

Claims (1)

[Claims] 1. In a magnetic tape recording device, there is a detection circuit that uses a reference clock signal and a counter to detect that the cycle of a read signal is within a predetermined range, and a reference clock that detects that the output signal of the detection circuit continues for a predetermined time or more. A record detection circuit comprising a detection circuit that detects by a counter.