JPS63211040A - Storage device - Google Patents

Abstract

PURPOSE:To quickly perform the read operation by constituting an information storage part of plural memory blocks consisting of a main memory whose operation speed is low and capacity is large, an auxiliary memory whose operation speed is high and capacity is small, and a data buffer. CONSTITUTION:An information storage part MB consists of plural memory blocks of a main memory MM whose operation speed is relatively low and capacity is large, an auxiliary memory HSM whose operation speed is relatively high and capacity is small, and a data buffer FF. With respect to the read operation, address information is compared with that of the preceding operation cycle and a read signal is outputted from the data buffer FF, the auxiliary memory HSM, or the main memory MM through the data buffer FF, and information to be next read is transferred in one information storage part MB while the other information storage part MB is accessed, thus increasing the operation speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an effective technology that can be used in a memory board that is installed in a storage device, for example, on a mounting board such as a printed circuit board. .

[Conventional technology]

An example of a memory board used as a main storage device in a micro combinator or the like is ``Memory Board for Expansion H64EMBO2 User's Manual J'' published by Hitachi, Ltd. in March 1985.

[Problem that the invention seeks to solve]

As described above, a dynamic RAM having a large storage capacity is used as a memory board used as a main storage device or the like. Although such a memory board can have a large storage capacity, it has the disadvantage of slow operation speed.

An object of the present invention is to provide a storage device that achieves a large storage capacity and high-speed operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the main memory is relatively slow in operation and has a large storage capacity, whereas the auxiliary memory is relatively fast in operation and has a smaller storage capacity than the main memory, and the units in the memory. A data buffer is provided that has an information retention function corresponding to the information bits accessed in If the addresses of the upper bits excluding the data buffer specification are the same, a read signal is output from the data buffer, and if the addresses of the upper bits specifying the auxiliary memory are the same, the data buffer is read from the auxiliary memory. and outputs a read signal from the main memory via the data buffer when the addresses of the upper bits specifying the auxiliary memory are different, and also outputs the read signal from the main memory via the data buffer or the auxiliary memory of one of the information storage units. When access is made to the other information storage unit, data corresponding to the next address is transferred from the auxiliary memory to the data buffer or from the main memory to the auxiliary memory, respectively. It is something to do.

[For production]

According to the above-mentioned means, when reading from consecutive addresses or repeatedly reading within a certain address range, such as when executing a program, the operation speed is increased by transferring the information to be read next to the data buffer. The probability of being able to send out a read signal from the data buffer or auxiliary memory is increased, and it is noted! !
The actual operating speed of the device can be increased.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment of a storage device according to the present invention. Each circuit block in the figure is mounted on a mounting board such as a printed circuit board.

In this embodiment, although not particularly limited, the information storage unit MB
consists of two circuit blocks, each consisting of the following circuit blocks. The main memories MMO to MM3 are configured, for example, by dynamic RAMs having a ×8 bit configuration. This dynamic RAM has a storage capacity of about 32 bytes, so the address terminals are made up of 16 bits, including AO to A14 and the chip selection terminal C8, which serves as the actual address terminal. . Note that in a dynamic RAM, generally, a row-related address signal and a column-related address signal are supplied in time series from the same address terminal, and the actual address signal is composed of 8 bits. The main memories MMO to MM3 in the same figure are
This does not show the dynamic RAM itself, but the 16-bit address terminals mentioned above are multiplexed by an appropriate address generation circuit and R
It should be understood that it is supplied to an AM chip.

In this way, the main memories MMO to MM3 shown in the figure include various control circuits for accessing the dynamic RAM.

One memory circuit of the main memories MMO to MM3 is accessed by output signals YO to Y3 formed by a decoder circuit DCR receiving address signals of the upper two pits. In one information storage unit MB, the four main memories MMO to MM3 are provided.

In this embodiment, in order to speed up the read operation,
Auxiliary memory H8M is provided. This auxiliary memory H3M
For example, a static type RAM is used in which the peripheral circuit is constituted by bipolar transistors and the memory cell is constituted by an 0MO3 (complementary MO3) circuit, which enables high-speed operation with low power consumption. As such a static type RAM, for example, the product name 'HM6788J sold by Hitachi, Ltd. can be used. Since this RAM has a ×4 bit configuration, two 0w! The auxiliary memory HSM has a storage capacity of about 16 bytes by using the two RAMs mentioned above. One information storage unit MB includes the auxiliary memory H3M.
Also, four memory cells are provided corresponding to the number of the main memories MMO to MM3. The data terminals of these main memories MMO-MM3 and the auxiliary memory are coupled by an internal bus consisting of 8 bits.

Among the address signals for the storage device, address signal A
The 14-bit address signals 3-A16 are supplied to address terminals AO-A13 of the auxiliary memory H3M via an internal address bus.

Further, address signals A3 to A17 are supplied to the main memory MM.
It is supplied to the address terminal AD-A14 of O to MM3.

Further, a data buffer FF constituted by a TTL (transistor-transistor-logic) circuit is provided as a data output section. This data buffer FF is constituted by a through latch circuit, and has both a data output function and a data holding function. An input terminal of this data buffer FF is coupled to the data bus. ``The output terminal Q of this data buffer FF is coupled to the data terminals DO to D7 of the storage device. This data terminal DO-D7 is coupled to the input terminal of data input buffer IB. This data input buffer IB is constituted by a TTL circuit as described above, and its output terminal is coupled to the data bus. In one information storage unit MB, such a crowded cover sofa also has the above-mentioned main memories MMO to MM.
3 and auxiliary memory I (4 pieces are provided corresponding to the number of SMs).

Each circuit block with the above configuration constitutes a unit memory block, which is divided into two information storage units MB (X2).
A storage section is configured by providing four for each.

Among the addresses AO to A2, which are substantially the lower three bits of the address signals for the storage device, the address signals A1 and A2 are used, although not particularly limited, for the data buffer FF and the data input buffer ! in the memory block. It is used as a selection signal for B. As a result, the main memories MMO to MM3 and the auxiliary memory H3M in each memory block are accessed in parallel by the remaining address signal A3NA19. In addition, the address signal AO of the least significant bit (LDS, UDS as described later)
) is used as a selection signal for the information storage section MB.

For the two information storage units MB as described above, the control unit C
0NT is provided. A typical function of this control unit C0NT is to include a memory circuit that stores the address of the previous memory access, and as will be described later, the address signal and the address signal are retained in the memory circuit during a read operation to the memory device. If the address is the same, a read signal is sent from the data buffer, and if the address is the same as the auxiliary memory address, the data in the auxiliary memory is transferred to the data buffer in each memory block, and the specified data buffer is The data buffer F stores the data in the data buffer of each memory block and takes the address into the storage circuit.
If the address is different from the addresses of F, auxiliary memory, and H3M, the data read from the main memory is outputted via the data buffer in the same manner as above. Furthermore, when the data buffer or auxiliary memory of one of the information storage sections is accessed, data corresponding to the next address is transferred from the auxiliary memory to the data buffer in the other information storage section. Alternatively, data is transferred from the main memory to the auxiliary memory.

The following signals are supplied to the control unit C0NT. The signal As is an address strobe signal, and indicates that a valid address signal exists on the address bus to which the storage device is coupled. Signals UDS and LDS are used to detect the upper 8 bits D8 to D8 of the 16-bit data. D15
This is a signal that specifies the lower 8 bits DO to D7, and 68
Since it is output from the 000 series microprocessor and is formed from the address signal AO, it is equivalent to the address signal AO. These signals UDS and LDS are control signals for realizing access in units of 8 bits (bytes) in the above-mentioned 16-bit microprocessor. Signal R/W is a control signal that specifies reading/writing to the storage device. The signal R3T is
This is a reset signal. Signal CLK is a clock signal. Signals A1 and A2 are address signals for the remaining lower bits.

FIG. 2 shows a block diagram of an embodiment of the address comparison section included in the control section C0NT.

Of the address terminals A1 to A19 of the storage device, address signals A3 to A19 excluding the address signal for specifying the data buffer FF are used as the data buffer FF.
This is an address signal corresponding to the data stored in F. Therefore, the address terminals A3 to A19 are coupled to the data terminals of the flip-flop circuit FFI.

The flip-flop circuit FFI has a clock terminal supplied with an address strobe signal As. Further, the clear terminal CLH is supplied with an output signal of a NOR gate circuit Gl that receives a reset signal R3T and an inverted signal of the control signal R/W. That is, the flip-flop circuit FFI is reset during a reset operation and when a write mode is designated. The flip-flop circuit F1 takes in an address signal when the address strobe signal As rises from a low level to a high level. Therefore, the flip-flop circuit F1
captures the address signal at the end of the memory access, and when the next memory access is performed by changing the address strobe signal As from high level to low level, it retrieves the address used in the previous memory access. It will memorize the signal. The output signal of the flip-flop circuit FFI is transmitted to the first comparator C.
It is supplied to one input terminal P of OMP1. The other input terminal Q of the comparator COMP is supplied with the address signals A3 to A19. Note that in order to operate the comparator COMP1 substantially during a read operation, a control signal R/W is supplied to one input terminal P side thereof. A power supply voltage Vcc (high level) is constantly supplied to the other input terminal Q side corresponding to this via a resistor. As a result, when the read mode in which the control signal R/W is set to high level is specified, the match signal (
P-Q) will be output, and the above comparator C
The operation of OMPI is effectively enabled.

The coincidence output (P-Q) outputs a low level signal when both signals match. This signal is output as signal FFR via inverter circuit N1. This signal F
FR is a control signal that instructs data output from the data balance FF.

Further, the inverted signal is formed via the inverter circuit N2, and is sent to the auxiliary memory H3 as a mismatch signal.
The signal is supplied to a comparator COMP3 that performs the same address comparison operation as described above corresponding to M.

Among the address terminals Al to A19 of the storage device, the address signals AI7 to A19 excluding the address signal for specifying the auxiliary memory H3M are the auxiliary memory H3M.
The address signal corresponds to the data stored in the address signal. Therefore, the address terminals AI7 to A19 are coupled to the data terminal of the flip-flop circuit FF2.

In this flip-flop circuit FF2, the address strobe signal As is supplied to the clock terminal as described above, and the reset signals R3T and 11 are supplied to the clear terminal CLR.
J? 11 NOR receives the inverted signal of signal R/W
An output signal of gate circuit G1 is supplied. As a result, the flip-flop circuit FF2 performs the same address signal storage operation as the flip-flop circuit FFI, and the output signal of the flip-flop circuit FF2 is supplied to one input terminal P of the third comparator COMP3. Ru. The other input terminal Q of this comparator COMP3 is supplied with the address signals A3 to A19.

Note that when the first comparator COMP1 sends out a discrepancy signal, in other words, when there is no data to be read in the data buffer FF, the comparator COMP3 selects the auxiliary memory! (In order to determine whether or not the data exists in the SM, the first comparator COMP1 is connected to one input terminal P side of the SM.
The output signal of the inverter circuit N2, which is the mismatch output of the inverter circuit N2, is supplied. A power supply voltage Vcc (high level) is constantly supplied to the other input terminal Q side corresponding to this via a resistor. Accordingly, the first comparator COMP
When the mismatch signal is sent out in step 1, the third comparator COMP3 becomes substantially active and other address comparison results become valid.

-LIJ(P-Q) of the above comparator COMP3 is
When both signals match, a low level signal is output. This signal is output as signal H8MR via inverter circuit N3. The high level of this signal H3MR is used as a control signal instructing data reading from the auxiliary memory H3M.

Note that the low level of the signals FFR and H3MR is used as a control signal for instructing data reading from the main memories MMO to MM3.

In this embodiment, there are two information storage units MB as described above, and when reading is performed to the data buffer FF or auxiliary memory H3M in one information storage unit, data corresponding to the next address is transferred to the other information storage unit. A function is added in which the data is transferred in advance to the data buffer 1FF of the information storage section and the auxiliary memory H3M. In order to realize such a function, the above address terminals A3 to A19 and the lower address terminal Al
and A2 are supplied to the address adder circuit AD.

This address addition circuit AD outputs address signals A3'' to A19°, which are obtained by excluding the lower address signal corresponding to the data buffer FF from the result of the addition (+1). A19゛ is
It is supplied to the input Q of the second comparator COMP2.

The other input P of this comparator COMP2 is the address signal A held in the flip-flop circuit FFI.
3 to A19 are supplied. As a result, when address signals A1 and A2 are both logic @1'', in other words, when the highest address in the data buffer 1FF is accessed, by performing the above +1, the address signal A3'' is Change. Comparator COMP2 detects this and sends out a mismatch output.

The auxiliary memory control circuit H3MC is connected to the comparator CO
In response to the output of MP2 and the address signal AO of the least significant bit (A3~A19 and A3°~A19''), the auxiliary memory outputs control signals H3MRO, A3°~A19'' which instructs to read H3M.
Address signals A3” to A for HSMRI and data transfer
16'' is generated to transfer data corresponding to the address to be accessed next to the data buffer 1FF as described later.

Further, the address addition circuit AD performs the addition (+1)
Among the results, address signals A17' to A19' excluding the lower address signals corresponding to the auxiliary memory 1 (SM) are sent to the input Q of the fourth comparator COMP4.

The other input P of this comparator COMP4 is the address signal A held in the flip-flop circuit FF2.
I7 to A19 are supplied. As a result, when address signals AI to A16 are both logic "1", in other words, when the highest address in the auxiliary memory HSM is accessed, by performing the above +1, the address signal A17'' is The comparator COMP4 detects this and sends out a mismatch output.The main memory control circuit MMC outputs signals LDS and UDS corresponding to the output of the comparator COMP4 and the address signal of the least significant bit, and the address signal A17.
~A19 and A17° ~A19°, the main memory outputs a control signal MMRO instructing to read MMO~MM3.
.

From main memory MMO to MM3 as above to auxiliary memory H
For data transfer operations to 3M, auxiliary memory) (SM
An address generation circuit (not shown) is provided that sequentially generates address signals A3 to A16 corresponding to the address signals A3 to A16. The generated address signals A3 to A16 and the control circuit MMC
a memory control circuit (not shown) that accesses the main memories MMO to MM3 by address signals AI7'' to A19'' supplied from the address signals A3 to A16 and writes the read data to the auxiliary memory H3M accessed by the address signals A3 to A16; is provided.

An outline of the read operation of the memory device having the above configuration will be described next with reference to the memory configuration diagram shown in FIG.

In this embodiment, as described above, the signal LDS formed in response to the address signal AO of the least significant bit corresponds to one information storage section MBO, and the signal UDS corresponds to the other information storage section MBI. . In other words, the main memory MM, auxiliary memory H3M, and data buffer of one of the information storage units MBO are associated with even-numbered addresses, and the main memory MM, auxiliary memory H5 of the other information storage unit MBI are associated with even-numbered addresses.
M and the data buffer are associated with odd addresses.

As an initial setting operation after a program etc. is written to the main memory MM, although not particularly limited, the auxiliary memory H in each of the two information storage units MBO and MBI is
3M has a first memory area MO in main memory MM.
and Ml data are transferred. As a result, the flip-flop circuit FF2 serving as an address storage circuit receives address signals A17 to A1 corresponding to the memory areas MO and Ml.
19 is set to 000. Furthermore, information on the starting address of the auxiliary memory H3M is transferred to each data buffer FF. Correspondingly, flip-flop circuit FFI
Address signals A3 to A16 stored in are all set to 0.

After the program is stored in the main memory MM,
When executing the program, for example, to simplify the explanation, when reading instruction words sequentially from the first address of the main memory MM (AO to A19 are all O), the signal LD
The information storage unit MBO side is accessed by the low level of S. Since the address signals A3 to A19 are 0, a match signal is generated from the comparator COMP1. As a result, a signal FFR instructing access to data buffer 1FF is formed, and a selection signal OCO is formed by 0 of address signals A1 and A2. Therefore, the read signal of one data buffer 1FF to which the smallest address (00) is assigned among the four data buffers FF is output.

Similarly, when reading the next address, the signal UDS corresponding to the address signal AO among the lower bit address signals AO to A3 is set to a low level. As a result, the information storage unit MBI is accessed. And since address signal person 3-A19 is O,
A coincidence signal is formed from comparator COMP1. As a result, a signal FFR instructing access to the data buffer 1FF is formed, and a selection signal OCO is similarly formed by 0 of the address signals A1 and A2.

Therefore, a read signal from one data buffer FF to which the smallest address (00) is assigned among the four data buffers FF is output.

Thereafter, the address signal is changed in the same manner, and when the address signals A1 and A2 are set to 1, the address signal A3° to which +1 is added changes from 0 to 1. That is, when the data buffer FF to which the largest address (11) corresponding to the selection signal OC3 is assigned is specified in the information storage units MBO and MBI, a mismatch signal is generated from the comparator COMP2. The auxiliary memory control circuit H3MC generates the signal H3MTRO based on this mismatch signal and the low level of the signal UDS specifying the odd-numbered information storage unit MBI. As a result, in parallel with the memory access to the odd-numbered information storage section MB1, the auxiliary memory H3M of the even-numbered information storage section MBO is read out by the address signals A3' to A16° formed by the adder circuit AD. Transferred to data buffer FF. In addition, due to the mismatch signal, the added address signal is stored in the free circuit FFI at the end timing of the memory access.

Therefore, the next time the address signal is incremented and the even-numbered information storage unit MBO is accessed, the instruction word to be read has already been transferred to the data buffer 1FF.
Similarly to the above, it is output from the data buffer 1FF. When accessing this even-numbered information storage unit MBO, the auxiliary memory control circuit H3MG sets the low level of the signal LDS to 1.
With the mismatch signal formed before the cycle, the signal H
Generate 5MTRI. As a result, in parallel with the memory access to the even information storage section MBO, the auxiliary memory H3M of the odd information storage section MBI is read out using the address signals A3 to Ale and transferred to the data buffer FF.

Therefore, the next time the address signal is incremented and the odd-numbered information storage unit MBI is accessed, the instruction word to be read has already been transferred to the data buffer FF.
Similarly to the above, it is output from the data buffer FF.

As a result, reading of consecutive instruction words in the range corresponding to the storage capacity of the above-mentioned auxiliary memory (ISM) (16 bytes in the example in Figure 1) is all output from the data buffer FF, resulting in extremely high speed reading. Reading can be achieved.

In addition, address signals A3 to A1 are
When any one or more of 6 changes, a mismatch signal is output from the comparator COMP1. As a result, the operation of the comparator COMP3 is substantially enabled, and since the upper addresses AI7 to A19 have not changed, a match signal is generated. As a result, in response to the address signal AO (LDS, UDS) of the least significant bit, even or odd information storage unit MBO or auxiliary memory of MBI) IsM
is accessed and the data buffer FF is accessed in units of 4 bytes.
will be forwarded to. Among these, lower address signals A1 and A
The output of one data buffing FF designated by 2 is sent out, and the transferred read signal is held.

Due to the address walk operation, all addresses A3 to A16 corresponding to the auxiliary memory H3M become 1, and when the address signal A17 changes by adding +1 to the lower addresses A1 and A2 or by executing a jump instruction,
A mismatch signal is generated from the comparator COMP4. Main memory control circuit MMC generates signal MMTRO based on this mismatch signal and the low level of signal UDS specifying the odd-numbered information storage section MBI. As a result, in parallel with the memory access to the odd-numbered information storage unit MBI, the main memory M of the even-numbered information storage unit MBO is
M is an address signal A formed by the adder circuit AD.
Memory area M2 specified by 17' to A19°
is read out by the incremented address signals ^3 to A16 generated by the address generation circuit and transferred to the auxiliary memory H3M. Since such an information transfer operation takes time, it is often not in time for the next readout. Therefore, in this case, the above transfer operation is interrupted and readout is performed directly from the main memory MM, and the data buffer is Output via FF. This also applies to the transfer operation from the main memory of the odd-numbered information storage unit MBI to the auxiliary memory H3M, which is performed in the next address specification.

In this embodiment, since reading is performed from the main memory in units of 4 bytes as described above, during the reading of a total of 8 bytes, the even and odd information storage units MBQ and M
Main memory MM to auxiliary memory H5M alternately in BI
The transfer operation will be performed.

Generally, when reading a program like the one above,
Since a loop is formed in a relatively small address range and reading is repeatedly performed under the same address A17 to A19, most of the above reading is output from the data buffer FF or auxiliary memory, so extremely high-speed reading can be performed. Become something that will be loved.

Note that the write operation is performed in the main memories MMO to MMO in FIG. 1 above.
This is done for MM3. In the write operation, the auxiliary memory) is controlled by the low level of the control signal R/W.
No write signal is formed in the ISM, so that the write data supplied from the external terminal DO-D7 is transferred to the information storage unit MBO or MBI, which is selectively accessed in accordance with the address signals LDS and UDS of the least significant bit.
Only one data input cover sofa IB in the selection signal B
In response to UFWO-3, the main memories MMO-MM3 are brought into an operating state, and one of the main memories MMO-MM3 is instructed to write.

The effects obtained from the above examples are as follows. That is, (1) the main memory is relatively slow in operation and has a large storage capacity; the auxiliary memory is relatively fast in operation and has a smaller storage capacity than the main memory; A data buffer having an information holding function corresponding to the information bit of unit access in the memory is provided, and this is constructed as one memory block, or an information storage unit consisting of a plurality of memory blocks is configured,
In a read operation, compare the address information from the previous operation cycle, and if the addresses of the upper bits excluding the data buffer specification are the same, a read signal is output from the data buffer, and if the addresses of the upper bits specifying the auxiliary memory are the same, then A read signal is output from the auxiliary memory via the data buffer, and when the addresses of the upper bits specifying the auxiliary memory are different, a read signal is output from the main memory via the data buffer, and one of the information storage sections When an access is made to the data buffer or auxiliary memory, the data corresponding to the next address is transferred from the auxiliary memory to data buffer 1 or from the main memory to the auxiliary memory in the other information storage section. By transferring each data, when reading from consecutive addresses or repeatedly reading within a certain address range as in the execution of a program, the operating speed is increased by transferring the information to be read next to the data buffer and storing it. The probability that a read signal can be sent from the data buffer or the auxiliary memory, which has a high speed, is increased, and the effect that the actual operating speed of the storage device can be increased is obtained.

(2) Since the data is automatically transferred by the storage device, the microprocessor etc. does not have to consider which storage means holds the data to be read.
Can perform memory access. This has the effect that the burden on the software and hardware of the system can be significantly reduced, as in the case of using cache memory.

(3) The above (1) provides the effect of realizing a high-speed information processing system by increasing the speed of the microprocessor.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. For example, in FIG. 1, the information storage units MBO and MBI may be separated by the address signal A2. In this configuration, up to 4 bytes can be read continuously from one information storage unit. , the transfer operation of the information to be read next from the auxiliary memory or the main memory in the other information storage section is performed in parallel. In addition to the dynamic RAM, the main memory may be a read-only memory such as an EPROM that has a large storage capacity and has a slow operating speed. Since only read operations are performed, by adding an auxiliary memory or data buffer as described above, it is possible to significantly speed up memory access.

In addition, as the auxiliary memory H3M, as described above,
In addition to static RAM with 0MO3 configuration, it can be anything that is faster than the read speed of the main memory used, such as CMOS static RAM, and controls these auxiliary memories and data buffers. The specific configuration of the control circuit can take various embodiments. Furthermore, in order to increase the storage capacity, the information storage section may be composed of a plurality of memory boards, and the control section may be composed of an independent printed circuit board or the like.

The present invention can be widely used as a storage device in various information processing systems such as microcomputer systems.

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by typical inventions are as follows. In other words, compared to a main memory such as dynamic RAM or EFROM which has a relatively slow operating speed (and a large storage capacity), a main memory which has a comparatively fast operating speed and a smaller storage capacity than the main memory mentioned above. An auxiliary memory and a data buffer having an information holding function corresponding to the information bit of unit access in the memory are provided, and this is used as one memory block to configure an information storage unit consisting of a plurality of memory blocks. In the read operation, the address information from the previous operation cycle is compared and the data buffer specification is removed (if the upper bit addresses are the same, a read signal is output from the data buffer, and the upper bit address that specifies the auxiliary memory is If they are the same, a read signal is output from the auxiliary memory via the data buffer, and if the addresses of the upper bits specifying the auxiliary memory are different, a read signal is output from the main memory via the data buffer, and one of the above When the data buffer or auxiliary memory of the information storage section is accessed, the data corresponding to the next address is transferred from the auxiliary memory to the data buffer or from the main memory to the auxiliary memory in the other information storage section. By transferring each data to memory, when reading from consecutive addresses or repeatedly reading from a certain address range as in the execution of a program, by transferring the information to be read next to the data buffer and storing it. The probability that a read signal can be sent from the data buffer or the auxiliary memory, which operates at a high speed, is increased, and the actual operating speed of the storage device can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of an address comparison circuit in the control section, and FIG. 3 is a block diagram showing an example of the operation. FIG. 2 is a memory configuration diagram. MBO, MBl...information storage unit, MMO~MM3, MM
・・Main memory, H3M・・Auxiliary memory, FF・・Data buffer, IB・・Data input buffer, DCR・・Decoder, C0NT・・am section, FFI, FF2・・Flip‐flop circuit, COMP 1 to COMP4・・Comparator, AD... adder circuit, ISMC... auxiliary memory control circuit, MMC... main memory control circuit Figure 2 Figure 3 MBOMe 1

Claims (1)

[Scope of Claims] 1. A main memory that is relatively slow in operation and has a large storage capacity; an auxiliary memory that is relatively fast in operation and has a smaller storage capacity than the main memory; It has an information storage section composed of one or more memory blocks, with a data buffer having an information holding function corresponding to the information bit of a unit access in the memory as one memory block, and in a read operation, Compare the address information and if the addresses of the upper bits excluding the data buffer specification are the same, a read signal is output from the data buffer, and if the addresses of the upper bits specifying the auxiliary memory are the same, the read signal is output from the auxiliary memory via the data buffer. A read signal is output, and when the addresses of the upper bits specifying the auxiliary memory are different, a read signal is output from the main memory via the data buffer, and at the same time, the read signal is output to the data buffer of one of the information storage units or the auxiliary memory. When an access is made, data corresponding to the next address in the other information storage section is transferred from the auxiliary memory to the data buffer or from the main memory to the auxiliary memory, respectively. storage device. 2. The storage device according to claim 1, wherein the data buffer is composed of a through latch circuit composed of a TTL circuit, and the auxiliary memory is composed of a static RAM. .