JPS63209098A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize the stable operation of a circuit without the reduction of operating speed by providing a delay circuit between a chip enable buffer circuit and an output buffer control circuit. CONSTITUTION:The delay circuit D is inserted between the chip enable buffer circuit C and the output buffer control circuit E, and a delay time is set so that a time, at which an output buffer circuit N goes to an active state after the output of the output buffer control circuit E goes to a high level and to a low level respectively, is delayed and made to be the same as the time, at which a data, read out from a memory cell M, appears at the output DO of an amplification circuit K. Accordingly, the output of the output buffer control circuit E can be delayed until a true decided data appears in the output of the output buffer circuit N. Thus, even if any kind of the data is read out from the selected memory cell, the voltage of an output terminal O never fluctuates violently between the high level and the low level in a short time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and particularly relates to an electrically rewritable semiconductor memory device (hereinafter referred to as an EP ROM). The type of EPROM shown in Figure 6 is known.
First, the configuration of M will be explained.

In FIG. 6, CE (over par) is an input terminal for a chip enable signal supplied from the outside, and OE (
Overpar) is an input terminal for the output enable signal. A1 to A13 are input terminals for address signals, and indicate data input/output terminals 01 to 08, respectively. C is a CE (over par) buffer circuit,
It detects whether the chip enable signal supplied to the input terminal CE (over par) is at a low level or a high level, and shapes its waveform. B is an OE (over par) buffer circuit, which detects whether the output enable signal supplied to the input terminal OE (over par) is at a low level or a high level, and shapes its waveform. A
Address buffer circuits dl to Ad13 detect whether the address signals supplied to the address input terminals A1 to A13 are at low level or high level, and shape their waveforms. The embodiment of FIG.
Since it has a storage capacity of 8 bits), it has 13 address input terminals. Output buffer control circuit E
receives the outputs of buffer circuits B and C and controls whether to activate or deactivate the output buffer circuits. F is an X decoder circuit block that decodes address signals supplied to address input terminals A1 to A5, and G is an X decoder circuit block that decodes address signals supplied to address input terminals A6 to A13. Therefore, 1 byte of memory cells constituting the memory cell block M can be specified in the Y decoder circuit block F and the X decoder circuit block G, and data is read from the specified memory cell and Y select is performed. It is supplied to the sense amplifier circuit J via the circuit block H.

The sense amplifier circuit J determines whether the data stored in the selected memory cell is a logic "0" or a logic "1".

The sense amplifier circuit J differentially amplifies the voltage level of the data read from the memory cell and outputs an output Von (for example, IV) if the read data is logic "O", and an output Voff if the data is logic "1". (e.g. 3V) is sent to the comparison detector of the amplifier circuit, and the comparison detector is sent to the intermediate voltage level RO (e.g. 2V) output from the reference circuit.
Compare with. The output Do from the amplifier circuit is sent to input/output terminals ol to 08 via an output buffer circuit N. 2 is an input buffer circuit that determines whether the input data supplied to the input/output terminals Ol to 08 is at a low level or a high level and shapes the waveform.

The EPROM functions in read mode, standby mode, write mode, etc., and these mode settings are selected based on the voltage levels of signals appearing at input terminals CE (over par) and OE (over par). Among the EPROM modes, typical modes are shown in the table below.

Leaving Each of the above modes will be explained in detail below.

In read mode, address buffer circuits Adl to Ad
13. X decoder circuit block GSY decoder circuit block F, sense amplifier circuit J, amplifier circuit K, and output buffer circuit N become active, and the data stored in the memory cell selected based on the address signal is transferred to input/output terminal 01. It is output from 08 to 08. On the other hand, in standby mode most circuits are inactive and EPRO
M becomes inactive. On the other hand, in the write mode, the address buffer circuits Adl to Ad13, the The data is written to the memory cell specified by the signal. In this conventional example, input/output terminals 01 to 08 (hereinafter represented by Oi) are common for data input and output, so input buffer circuit ■ and output buffer circuit N are selectively controlled by control signals. There is a need to.

Figure 7 shows a CE (over par) buffer circuit C and an OE
(Over par) A specific configuration of a buffer circuit B, an output buffer control circuit E, an amplifier circuit, and an output buffer circuit N is shown. CE (over par) buffer circuit C is a p-channel enhancement insulated gate field effect transistor (hereinafter referred to as PE-I GFET) Q
c 1 t Q c 3sQ c 5 , Q c 7
tQc9 and n-channel enhancement insulated gate field effect transistor (NE-IGF
ET) Q C2, Q CLQc6. Qc8. Q
The chip enable signal CE (
output buffer control circuit E, address buffer circuits Adl to Ad13. X
Decoder circuit block GS Y decoder circuit block F
, sense amplifier circuit J, and amplifier circuit K, internal chip enable signals ce and ce (over par) are generated. As shown in the table, in read mode, ce goes to high level and ce (over par) goes to low level, and in standby mode, ce goes to low level.
ce (over par) moves to a higher level.

On the other hand, CE (over par) buffer circuit B is PE-I
GFETQBI, QB3. QB5. QB7, QB9 and N
E-IGFETQB2. QB4゜QB6. QB8. QB
IO, and an internal output enable signal oe based on the output enable signal OE (over par).

Forming an oe (over par), these oe,.

e (over par) is supplied to the output buffer control circuit E. As is clear from the above table, in read mode, Oe goes to a high level and oe (over par) goes to a low level, and in standby mode, Oe goes to a high or low level, and oe (over par) goes to a low level. Or it shifts to a high level, and in the light mode, Oe shifts to a low level and Oe (over par) shifts to a high level.

The output buffer control circuit E is PE-IGFETQEl,Q
E2. QE5. QE7. QE9 and NE-IGFETQE
3. QE4. QE6. QE8. Based on the above two internal enable signals Ce and Oe, output signals ce"oe and Ce・Oe (over par) are formed, and these output signals ce・Oe and ce-o
e (over par) is supplied to the output buffer circuit N to activate or deactivate the output buffer circuit N. As is clear from the above table, in read mode, ce/Oe goes to a high level, ce/oe (over par) goes to a low level, and in standby mode and write mode, ce'.

e moves to a low level, and ce-oe (over par) moves to a high level.

Furthermore, the amplifier circuit includes PE-IGFETQKI, QK3. Q
K6. QK7. QKIO, QK12 and NE-IGFET
QK2. QK4. QK5. QK8゜QK9. QKII,
QK13, IGFETQKI to Q
K5 constitutes a comparison detector that compares and amplifies the output SO from the sense amplifier circuit and the output RO from the reference circuit. This comparison detector is controlled by the signal ce and is active when ce is high.

Since ce is high level in read mode, the logic “0”
” is selected, the voltage of the output SO of the sense amplifier circuit becomes the voltage R of the reference circuit.
0, and the output DO of the amplifier circuit shifts to a low level. On the other hand, when a memory cell storing logic "1" is selected, the voltage of the output SO of the sense amplifier circuit becomes higher than the output voltage of the reference circuit, so the output Do of the amplifier circuit is output at a high level. be done. On the other hand, in standby mode, ce (over par) is at a high level, so IGFET QK9 becomes conductive, and a low level is output to the amplifier circuit.

Also, the comparison detector becomes inactive.

On the other hand, in the write mode, Ce becomes high level and the comparison detector becomes active, but in the write mode, the output of the sense amplifier circuit is always lower than the output of the reference circuit, so a low level is output to the amplifier circuit. do.

Output buffer circuit N is PE-IGFETQNI.

QN3. QN4. QN7. QN9. QNIO,QNI3
．． QNI5 and NE-IGFETQN2. QN5. QN6
．． QN8. QNI 1. QNI2. QNI4. QNI6
In the read mode, the output ce'oe of the output buffer circuit is at a high level, and ce・oe (over par) is at a low level, so IGFETQN3
．． QN4゜QN5. The 2NOR circuit composed of QN6 and the 2NAND circuit composed of QN9, QNIO, and QNI L QNI2 become active, and the voltage of the output DO to the amplifier circuit is transmitted to the data input/output terminal Oi. That is, when a memory cell storing a logic "0" is selected, DO goes low, so the output O1 of the output buffer N goes low. On the other hand, logic “1”
When the memory cell storing . . . is selected, the output DO becomes high level, and the output buffer N outputs a high level. On the other hand, in standby mode, the output ce and Oe are at low level and the output ce and Oe (over par) are at high level, so IGFETQN6 becomes conductive, node N1 goes to low level, and IGFETQNI
O is also conductive and node N2 becomes high level. Therefore, the last stage IGFETQN15. Both QNI6 become non-conductive, and the input/output terminal O1 becomes a floating state. As a result, the data output of the previous read cycle is held at the input/output terminal O1. In the write mode, the output ce"oe goes to the low level, and the output ce/oe (over par) goes to the rear level. Therefore,
IGFETQN15.Same as during standby. Both QNI6 become non-conductive, and write data can be input to the input/output terminal Oi. The input data is transmitted to the input buffer circuit I.

There are three times to display the read characteristics of the EPROM as described below. In other words, tacc represents the time from when human power is applied to the address terminal until data appears at the input/output terminal Oi (at this time, the two terminals CE (over par) and OE (over par) both shift to a low level. ), until data is output to input/output terminal O1 when the signal input to the CE (over par) input terminal changes from high level to low level and the chip changes from standby mode to read mode. tce representing the time of
(At this time, a signal with a determined level is already applied to each address input terminal, and a low level is applied to the OE (over par) terminal.) toe(
At this time, a low level is applied to the CE (over par) input terminal, and the level of the signal supplied to each address input terminal has already been determined.

The standard regarding these times is, for example, tacc=25
0nsS tce=2i50ns, toe=100ns
It is determined as follows.

Next, with reference to FIGS. 6, 7, and 8, the above tce
The operation in mode (CE (over par) transitions from high level to low level) will be explained.

(1) CE (over par) In the buffer circuit C, ce transitions from a low level to a high level, and ce (over par) transitions from a high level to a low level.

The transmission delay time t(
Let ce) be Ions.

(2) OE (over par) In buffer circuit B, oe is at a low level and oe (over par) is at a high level.

(3) In the output buffer circuit E, ce is transitioning from a low level to a high level, and ce (over par) is transitioning from a high level to a low level. (over par) moves from a high level to a low level. The transmission delay time t(ce-oe) of the output buffer control circuit E is assumed to be 10 ns.

(4) Address buffer circuits Adl to Ad13 are ce
is at a high level and ce (over par) is at a low level, so it becomes active and the signal supplied to the address input terminal is transmitted to the address buffer circuit. The transmission delay time t (ad) of the address buffer circuit is 10n
Let it be s.

(5) The x decoder circuit and the Y decoder circuit are in an active state because ce has shifted to a high level and ce (over par) has shifted to a low level, and the output signals of the address buffer circuits Adl to Ad13 are decoded. be done. The transmission delay time t(xy) between the X decoder circuit and the X decoder circuit at this time is assumed to be 40 ns.

(6) The sense amplifier circuit J becomes active when ce becomes high level and Ce (over par) becomes low level, and the memory contents of the memory cell selected by the X decoder circuit and the X decoder circuit are read out. A voltage corresponding to the stored contents appears at the output SO of the sense amplifier circuit. At this time, the transmission delay time t(s
ence) is 20ns.

(7) The amplifier circuit becomes active when ce goes to high level and ce (over par) goes to low level, and the voltage of the output SO of the sense amplifier circuit and the voltage of the output RO of the reference circuit change. are compared and detected, and the data read from the selected memory cell appears at the output DO.

The transmission delay time t (diff) of this amplifier circuit is 20 ns.
shall be.

(8) The output buffer circuit N has ceφOe at a high level,
Since ce·oe (over par) becomes a low level, it becomes active, and the voltage appearing at the output Do of the amplifier circuit is transmitted to the input/output terminal Oi.

At this time, the transmission delay time t of the output buffer circuit (.

ut) is 50ns.

As explained above, in conventional EFROM,
During operation in the tce mode, the time t(outact) until the output buffer circuit becomes active is expressed as t(outact)=t(ce)+t(ceoe), which is 20 ns in this example. Also, tce
is tce=t (ce)+t (ad)+t (xy)+
t (s enc e) +t (d i f f)+
t(out), which in this example is 1δOns.

Next, in standby mode, the input/output terminal Oi2 is held at a high level in the previous read cycle, and then
The operation of the amplifier circuit and the output buffer circuit N when a memory cell storing logic "1" in the ce mode is selected by an address signal will be explained. In standby mode, the output to the amplifier circuit is at a low level as shown in Figure 7, and CE (over par) shifts from a high level to a low level and enters the tce mode; as described above. Since ce·Oe becomes high level and ce·oe (over par) becomes low level in 20 ns, the output buffer circuit becomes active. However, although the sense amplifier circuit is in the active state, the memory cell selected based on the address signal is not connected to the output Do of the amplifier circuit.
In this example, it takes 100 ns to output the data. Therefore, in standby mode, the output voltage (low level) of the amplifier circuit is transmitted to the output buffer circuit N, and the output voltage (0UT) in FIG.
As shown by the waveform I, the level temporarily becomes low. Note that the delay time during which the output changes from high level to low level is represented by t (outact), which is 70 ns in this example. Next, the data (high level) of the memory cell selected by the address signal is transferred to the output DO of the amplifier circuit.
appears, so it becomes high level again. The delay time for the output to change from low level to high level is expressed as tce, and in this example is 150 ns.

[Problems to be Solved by the Invention] As explained above, in the conventional EPROM, a logic "1" is stored in the TCE mode when the input/output terminal O1 is held at a high level in the standby mode. When a memory cell is selected, the voltage at the input/output terminal Oi shifts from a high level to a low level as shown at 0UTI in FIG. 8, and then returns to a high level again. Therefore, the voltage at the input/output terminal temporarily becomes low level, a so-called "whisker" occurs, and during the period A in Figure 8, the IGF
ETQNlB becomes conductive, and the charge stored in the input/output terminal Oi is discharged to the ground terminal. On the other hand, in period B, I
GFET QN15 becomes conductive, and input/output terminal O1 is charged from the power supply. However, these switchings are completely meaningless in terms of circuit logic. Moreover, IGFETQN1
5. QN16 has a gate width/gate length ratio of, for example, 1000 in order to charge the input/output terminal O1 with a large load capacity.
Since it is set to 15, if all bits in one byte are at high level, a very large discharge current flows from the input/output terminal to the ground terminal during the period , and the ground potential temporarily rises. On the other hand, during period B, a very large charging current flows from the power supply to the input/output terminal Oi, causing a temporary drop in the power supply voltage.

Such voltage fluctuations generate noise, which results in unstable circuit operation, such as deterioration of the input level of the input buffer circuit or malfunction of the comparison detector.
In extreme cases, there is a problem in that positive feedback is applied to the circuit, causing the output buffer circuit to oscillate.

On the other hand, if the noise margin is set large to prevent malfunctions in the circuit, there is a problem in that the operating speed decreases.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of stable circuit operation and high-speed operation.

[Means for solving the problem] A chip enable buffer circuit to which an externally supplied chip enable signal is supplied, an output enable buffer circuit to which an output enable signal is supplied, and a chip enable buffer circuit which is selected based on an address signal. an output buffer circuit to which the determined data read from the memory cell is supplied; an output terminal which supplies the determined data held in the output buffer circuit to the outside; and an output terminal for the chip enable buffer signal. and an output buffer control circuit that controls the transfer of determined data from the output buffer circuit to the output terminal based on the output of the output enable buffer circuit. A semiconductor memory device characterized in that a delay circuit is provided between the output buffer control circuit and the output buffer control circuit.

[Operation of the Invention] In the semiconductor memory device having the above configuration, the output of the output buffer control circuit can be delayed until true determined data appears at the output of the output buffer circuit. Therefore, no matter what data is read from a memory cell selected in TCE mode when the output terminal is at a high level, the voltage at the output terminal will not change drastically between high and low levels in a short period of time. do not have.

[Example code] The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. Components that are the same as those in the conventional example described above are given the same reference numerals and explanations will be omitted. The difference in structure between the conventional example and the first embodiment is that a delay circuit is inserted between the CE (over par) buffer circuit C and the output buffer control circuit E.

The specific configuration of the delay circuit is shown in FIGS. 3 and 4, respectively. In FIG. 3, QDI, QD3°QD5. QD7
are PE-I GFETs, QD2, QD4 . QD6
．． QD8 indicates NE-IGFET. CDI,C
D2. CD3. CD4 is a capacitive element. output signal ce
When transitions from a low level to a high level, IGFETQ
Since D2 is turned on and the capacitive element CDI is grounded, the next stage IGFET QD3 is turned on and the capacitive element CD2 is charged. Thereafter, similar discharging and charging is repeated to generate a small delay time. In FIG. 4, QDll, QDI3.
CD15. QDI7 is an N-channel depletion type IGFET, QDI2, QDI4 . QDI6. Q
DI8 is NE-IGFET. CD4. CD5. C
D6 indicates a capacitive element. The delay circuit shown in FIG. 4 is also an IGFETQD12. QDI4. QDI6. Q
DI8 turns on and off alternately and capacitive element CD4゜CD
5. The CD 6 is repeatedly discharged and charged to generate a predetermined delay time.

As already explained with respect to the prior art, conventional EPRO
In M, in the tce mode, the output buffer circuit reads information from the memory cell selected by the address signal and outputs it to the amplifier circuit.

Since it becomes active earlier than the time at which it appears, it appears at the output DO to the amplifier circuit in standby mode before the true data is output. As a result, depending on the data stored in the memory cell, the voltage at the input/output terminal Oi shifts from a high level to a low level and then back to a high level, causing the above-mentioned problem. However, in this example, t
Output ce/Oe of output buffer control circuit in ce mode
After ce and oe (over par) transition to a high level and a low level, respectively, the time when the output buffer circuit becomes active is delayed, and the data read from the memory cell appears at the output DO to the amplifier circuit. Set the delay time to match the time. In the example explained in connection with the conventional example, the transmission delay time between the CE (over par) buffer circuit and the output buffer control circuit is 20 ns, and the tc
Since the time it takes for read data to appear at the output of the amplifier circuit in the e mode is 100 ns, the delay time based on the delay circuit is set to 80 ns. In the case of the delay circuit shown in FIG. 3, the specific delay time is set by selecting the gate width/gate length ratio of the IGFETs QDl to QD8 and the capacitance values of the capacitive elements CDI to CD4. In the case of the delay circuit shown in FIG. 4, the gate width/gate length ratio of QDll to QD18 and the capacitance values of the capacitive elements CD5 to CD8 are selected. Further, the number of stages connected in series can be increased or decreased arbitrarily.

The voltage change at the input/output terminal O1 of this embodiment equipped with the above-mentioned delay circuit is shown by OUT in FIG. As is clear from FIG. 5, in this embodiment, the time when the output buffer circuit becomes active in the TCE mode is delayed until the time when the data read from the memory cell appears at the output of the amplifier circuit. Therefore, the input/output terminal O in standby mode
Even if data is read from a memory cell that stores logic ``1'' while the logic ``1'' is held at a high level, the voltage at the input/output terminal O1 will always be at a high level, and noise etc. will not occur. Prevented.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention. In the case of the embodiment shown in FIG. 2, a delay circuit D1 is provided between a CE (over par) buffer circuit C and an output buffer control circuit E, and a delay circuit D1 is provided between an OE (over par) buffer circuit B and an output buffer control circuit E. A delay circuit D2 is inserted between them, and is adopted in an EPROM whose speed standard defines TOE to be equal to TCE.

[Effects of the Invention] As explained above, the present invention provides a delay circuit between at least the chip enable buffer circuit and the output buffer control circuit, so when the output terminal is held at a high level, the TCE mode is activated. Therefore, even if a memory cell holding logic "1" data is selected, a low-level voltage is not transmitted to the output terminal, and so-called "whiskers" do not occur at the output terminal. As a result, fluctuations in the power supply or ground voltage are prevented, and stable operation of the circuit can be achieved without reducing the operating speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention, and FIG. 3 is an electric circuit diagram showing the configuration of a delay circuit. FIG. 6 is a block diagram showing the configuration of the conventional example, FIG. 7 is an electric circuit diagram showing the detailed configuration of the conventional example, and FIG. 8 is a graph showing voltages at input and output terminals of the conventional example. B...Output enable buffer circuit, C...Chip enable buffer circuit, D...
...Delay circuit, DI, D2...Delay circuit, E...Output buffer control circuit, M...
Memory cell block N... Output buffer circuit, 01 to 08... Input/output terminal (output terminal). Patent Applicant NEC Corporation Agent Patent Attorney Kiyoshi Kuwai − □ Figure 1 Figure 2 Figure 5 (110)

Claims (1)

[Claims] A chip enable buffer circuit to which an externally supplied chip enable signal is supplied; an output enable buffer circuit to which an output enable signal is supplied; and a chip enable buffer circuit to which a chip enable signal is supplied from the outside. an output buffer circuit to which the output and determined data is supplied; an output terminal that supplies the determined data held in the output buffer circuit to the outside; and an output terminal for outputting the chip enable buffer signal and outputting the output enable signal. and an output buffer control circuit that controls transfer of determined data from the output buffer circuit to the output terminal based on the output of the buffer circuit, at least the chip enable buffer circuit and the output buffer control circuit. A semiconductor memory device characterized in that a delay circuit is provided between the semiconductor memory device and the circuit.