JPS59188890A - Control circuit of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress the noise of the power supply voltage or an input signal and improve the margin of the power supply by providing a delay circuit to either one of input routes of two external control signals forming the working signal of an output circuit. CONSTITUTION:A delay circuit 10 is set at the next stage of a buffer circuit 9a of the chip enable signal CE' of an EPROM, and the output signal is supplied to an AND gate G1 together with the output signal of a buffer circuit 9b of an out-enable signal OE. An output buffer circuit 7b is controlled by the output signal OE'. The circuit 7b is actuated with a delay of a fixed time compared with decoder circuits k3a and 3b and address buffer circuits 2a and 2b which are actuated synchronously with the fall of the signal CE'. Thus the circuit 7b is never actuated synchronously with other internal circuits, and therefore the variation of the power supply voltage is reduced. This reduces the peak value of the noise generated to the power supply voltage, the address input signal, etc. As a result, a malfunction is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for forming signals for controlling specific circuits such as output circuits in semiconductor integrated circuits.

[Background technology]

For example, in dynamic conductor memory such as RoM (read only memory), output cover 1. The operating state of the fa circuit is determined based on a chip enable signal or a chip select signal and an out enable signal supplied from outside the chip.

In such a semiconductor memory, when reading data, the output buffer is activated by dropping the chip enable signal and the out enable signal synchronously, or by fixing the out enable signal to a low level in advance and then letting the chip enable signal fall. Generally, a method is used in which the circuit is enabled.

However, when the enable signal falls to low level, other internal circuits other than the output cover 1 and 77 circuits often become operational at the same time. When the enable signal falls, a relatively large current flows through the internal circuit, causing the source voltage to fluctuate. Further, when the output buffer circuit is activated, current suddenly flows into the output circuit.

Therefore, as mentioned above, the falling edge of the chip enable signal is synchronized with the falling edge of the output buffer circuit. It was found that there were many problems such as noise occurring in the power supply voltage and input signal, distorted data being easily output, and the margin of the circuit's power supply voltage decreasing. .

However, in conventional semiconductor memories, the above-mentioned problems have hardly been considered.

[Purpose of the invention]

This invention was made with the above-mentioned background in mind. For example, even if two external control signals such as the chip enable signal and the out enable signal change to low level at the same time, the output circuit and the lower one This prevents external internal circuits from being activated at the same time, reduces noise generated in the power supply voltage and input signals, and prevents the output of erroneous data. The purpose is to improve margins.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the invention of C is achieved by providing a delay circuit in the middle of the input path of one of the two external control signals that form the signal sound corresponding to the operating state of the output circuit. , Even if two external control signals are changed at the same time, the output circuit and other internal circuits are always activated with an appropriate time difference, and by kneading, the noise f of the power supply voltage and input signal is suppressed, and the power supply voltage is This will improve margins.

Is this invention based on the drawings below? explain.

〔Example〕

FIG. 1 shows a practical example of the present invention when it is applied to an EPROM (Electrically Programmable Read Only Memory) device.

In the figure, 1 is the 70-ring gate electrode and the contact a-
A FAM that has a floating gate electrode and stores information through lightning and charges that are injected and accumulated in the floating gate electrode.
This is a memory array in which memory elements such as O8 are arranged in a matrix or 2x shape.

2a and 2b are address signals AX1 supplied from the outside.
．． Internal address signal aX, received by Ay, j'.

aXi ' aVj 1 stone -? Address to form 1
．． It is a fa circuit. Further, 3a is an address bar, an internal address signal ax1゜ζ〒 supplied from the 7-fur circuit 2a.
In response to this, an X decoder circuit 3b selects a corresponding word in the memory array 1. Internal address signal a7 output from fufu circuit 2b
j, the corresponding pin in memory array 1) 1
This is a Y decoder circuit for selecting fRk. The output from the Y decoder circuit 3b turns on one column switch in the column switch circuit 4, and the bit line in the memory array 1 is connected to the common bit line, thereby selecting a bit line. .

5 is a write circuit connected to the common bit line, 6 is a read circuit consisting of a sense amplifier, etc. connected to the common bit line M-J, and write circuit 5 and read circuit 6.
are connected to a common input/output terminal 10 via an input buffer circuit 7a and an output buffer circuit 71)'.

Further, reference numeral 8 denotes a control circuit which receives externally supplied enable signals Ti, program control signals PGM, etc., and forms appropriate control signals.

The address buffers 2a, 2b and address decoder circuits 3a, 3b are connected to the circuits 1. When the enable signal OK is changed to low level, the internal control signal outputted from the control circuit 8 is operated. In addition, the write circuit 5
is also put into an operating state by an internal diameter signal from the control circuit 8, and the memory element located at the intersection of the word line and bit line selected at that time is activated in response to a data signal from the input/output terminal 10. A write current km is used to inject information charges into the floating gate.

In this embodiment, a buffer circuit 9a that shapes the waveform of the chip enable signal OFi'i supplied from the outside.
A delay circuit 10 is provided at the next stage, and the output signal of this delay circuit 10 and the output signal of the buffer circuit 9b that shapes the waveform of the out enable signal ogl are input to an AND gate G1, and the output signal of the AND gate G1 is input to the AND gate G1. The output sofa circuit 7b can be controlled by the signal OE'.

Therefore, the externally supplied out enable signal OE
When the chip enable signal τj is changed from high level to low level while reaching the low level as shown by the solid line in FIG. 2(C), or as shown by the broken line in FIG. 2(C), the chip enable signal τj When changed to low level in synchronization with 011C, AND gate G! As shown in FIG. 2(D), the output signal OB' falls after a delay time T (1 (approximately 50 to 100 ne)) 9 in the delay circuit 1o, even when the chip enable signal 1 falls. Therefore, the output buffer circuit 7b is operated by the control signal output from the control circuit 8 in synchronization with the falling edge of chip enable -qcx, and the address buffer circuits 2a and 2b and the decoder circuit 3a.
, 3b, T (is brought into operation state one hour later than T).

As a result, the output buffer circuit 7b and other internal circuits are no longer activated at the same time, and the current flowing at the fall of the chip enable signal OF is reduced by that amount. The fluctuation of 0 is reduced. As a result, the peak value of noise generated in the power supply voltage, address input signal, etc. is reduced, and an imposed operation is prevented.

In addition, in EFROM, multiple bits (for example, 8 bits) of data are output in parallel, so multiple output ports 1. In this case, delay circuits with different delay times are provided, and the timing is different. It will be more effective if the output buffer is operated while shifting. As the delay circuit 10, in addition to an OR circuit, an inverter? You can use this book.

FIG. 3 shows an example of the output buffer circuit 7b. This output buffer circuit 7b is composed of a three-stage pull circuit. The gate terminals of MO8F:)iiTQ and Q2, which contain the entire first stage block circuit, are the output of the read signal (data) Sa sensed by the sense 7° amplifier 6 and the inverter V that inverts it. A signal Sa is applied to each of them. It's a moat, the MO8FET that makes up the next stage bush pull circuit.
The read signal Sa is applied to the gate terminals of IQ4 and Qs.
and first step 1. The output signals of the pull and pull circuits can be applied respectively. Furthermore, the output signal of the first-stage push-pull circuit and the output signal of the next-stage push-pull circuit are applied to the gate terminals of MO8FETQ, 6, and Q7 that make up the final-stage push-pull circuit, respectively. has been done.

And, in the embodiment with, MO, 5FETQ, +, Q5 +Q on the ground side of each push-pull circuit described above.
A switch MO is connected between each date terminal of 6 and the ground.
S F ET Q B + Q 91 Q r o are respectively provided, and these M OS F' ET Q
p + Q 91 Q io is the AND gate G1
It can be turned on and off by the output signal og'.

In addition, each of the above MO8FETQ+, Q, 2, Q4~Q
Although the IO is not particularly limited, it is formed as a D channel confirmation type. 1, the level of node nl? In order to increase the power supply voltage V. A Depres-John type MOEIFET Q3 is provided between the node nI and the node nI.

In the output buffer circuit 71:I, when one of the input enable signal @CE or the out enable signal om is set to high level, the output signal of the AND gate G becomes high level, and MO8FFiTQs Q9,
Since Q and to are turned on, MO8FETQ+ +
The gate voltage of Q5 + Qa is set to low level and turned off. As a result, the output node n2 of the middle stage push pull circuit is brought to a low level, and the final stage push pull circuit is brought to a low level.
・MO8FETs Q, 6 and Q7 that make up the pull circuit are both turned off, and the output is placed in a floating state. Also, when both the output enable signal OB and the output enable signal OE are set to low level, the AND
Since the output of gate GI is changed to high level, MO
8F]1CTQ,~Q+o are turned off.

As a result, the bush-pull circuits at each stage in the output buffer circuit 7b are pulled into an operating state, and the output signal V is at a level corresponding to the read signal S8. ut will now be output.

In the above embodiment, a switch M○5F is connected between the gate terminal of MO8F1111iTQ, Q, 5゜Q6 constituting the bush-pull circuit of each stage of the output circuit and the ground.
KTQs~Q, +o are provided, but this is MO8
Gate terminals of FETQ2, Q4, Q7 and power supply frost, voltage ■. It is also possible to provide it between 0 and 0, or to provide it on both sides. In this case, the new MO8F
It is preferable that FliT be of a p-channel type and turned on and off by a signal having a phase opposite to the output signal of the AID gate Gl.

Furthermore, a depression-type MO8FF that uses an inverter instead of the bush-pull circuit described above! TQ, 3
i can also be omitted.

〔effect〕

As explained above, is this invention an output circuit? Since the delay circuit ki can be installed in the middle of the input path of either one of the two external control signals (1.
Even if two external control signals are simultaneously changed to low level,
Since the output circuit and other internal circuits are always brought into operation with an appropriate time difference, a sudden large current is not allowed to flow, and noise generated in the power supply voltage and input signals can be reduced. Therefore, malfunctions due to noise are prevented even in a state where the power supply voltage is high, where noise is likely to be present, and the margin on the high power supply voltage side is improved.

It should be noted that the conventional EF, which does not take measures like the present invention,
Similarly to the present invention, in the ROM, the user can form and supply an out enable signal OFi such that the output enable signal OFi falls with a reasonable delay after the fall of the enable signal CE. effect can be obtained. However, according to the present invention, such troublesome measures? It has the advantage of being extremely easy to use since there is no need for the user to do anything.

Although the present invention has been specifically explained above based on practical examples of the invention made by the present inventor, the present invention is not limited to the above-mentioned examples. It goes without saying that various changes can be made within a wide range. For example, in the above embodiment, the case was explained in which the output cover and buffer circuits were controlled, but what about other circuits such as the input buffer circuit? It can also be applied when controlling.

[Application field]

Is the above explanation mainly an invention made by the inventor? Although we have explained the application field behind this, such as semiconductor memory such as EPROM, it is not limited to this, and examples include RAM (random access memory) and other chip enable signals or chip select signals and outputs. This invention can be applied to all semiconductor Toshiba circuits in which the output circuit is controlled based on the enable signal.

[Brief explanation of the drawing]

FIG. 1 shows an example of an IPROM to which the undiscovered technology is applied. 2 is a timing chart showing the timing of various signals in the FliP ROM, and FIG. 3 is a circuit diagram showing an example of an output buffer circuit. 1...Memory array, 7b...Specific circuit (output cover, F circuit), 8...Control circuit, 10...Delay circuit, i...Control code (chi, block enable signal)
, END1...Control signal (out enable signal).

Claims (1)

[Claims] 1. In a semiconductor integrated circuit equipped with a specific circuit whose operating state is determined based on two control signals supplied from the outside, the input path of one of the two control signals is A delay circuit is provided in the middle, so that even if two control signals are changed at the same time, the internal control signal that operates the above-mentioned specific circuit and the internal control signal that operates the other internal circuits are formed with an appropriate time difference. A control circuit in a semiconductor integrated circuit, which is characterized by its characteristics.