JPS63208939A - Decimal arithmetic circuit - Google Patents

Abstract

PURPOSE:To increase processing speed with the adding and subtracting instructions by controlling the overflow detection so that the number of object digits is decreased by one compared with a conventional case when a decimal adding/subtracting instruction of the variable operand length is carried out. CONSTITUTION:An instruction execution control circuit 12 fetches an instruction from a main memory 11 and starts a program executing circuit 13 based on an instruction code. In the case of a decimal adding/subtracting instruction, the circuit 13 sets the parameters L1 and N contained in the instruction at a decimal arithmetic circuit 14 and then reads a 2nd operand out of the memory 11. This reading action is carried out at every byte at and after the most significant rank byte and held by a register 31 at every time. The selection output data on a selector 33 are led to the 0, 1 and 2-9 detecting circuits 34, 35 and 36 respectively. The detecting results for the object digits of the 2nd operand are latched by registers 38 and 39 and then supplied to an overflow detecting circuit 40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a decimal arithmetic circuit that performs shifted decimal addition and subtraction.

(Prior Art) Generally, a decimal addition/subtraction instruction with a variable operand length is executed as follows. First, the second operand specified by the addition/subtraction instruction is read from the main memory and temporarily held in the register of the arithmetic circuit, and then shifted by the number of shift digits specified by the instruction. Next, the first operand specified by the addition/subtraction instruction is fetched from the main memory in order from its lower digits, and addition/subtraction is performed with the shifted second operand. This addition/subtraction is performed for the number of bytes of the first operand + 1 byte for reasons to be described later.

When the addition/subtraction sieve is completed, if it is a subtraction and the result is negative, the result is converted to an absolute value, and in other cases, the addition/subtraction result is stored in the ascending 1 operand in the main memory. is stored in the storage area.

Also, at the same time as the above operation, a check is made to see whether the operation result can be stored in the storage area of the first operand, that is, whether it will overflow or not, and the result (indicating the execution state of the corresponding instruction) is checked. Stored in the condition code register. In this overflow check, first, it is checked whether the number of digits (effective number of digits) of the second operand after the shift is greater than the number of digits of the first operand + 1, and if so, it is determined that there is an overflow. This determination (check) is called an overflow precheck to distinguish it from overflow detection after addition and subtraction.

Here, the reason why the number of digits of the second operand after the shift is compared with the number of digits of the first operand + 1 instead of the number of digits of the first operand is because the number of digits of the second operand after the shift is Even if the number of digits is greater than the number of digits in the first operand, the difference is 1
This is because, in the case of subtraction (when subtracting the first operand from the second operand after shifting), there is a possibility that the result of the subtraction will not be O-puff 0-.

As mentioned above, in the conventional decimal addition 'g calculation process, the first
One more digit than the number of digits in the operand must be calculated. In the case of addition, if one byte of the most significant digit of the result is not 0, or if a carry occurs from that digit when calculating the most significant digit, an overflow occurs.
In the case of subtraction, an overflow occurs if the result is not negative and the most significant byte of the result is not O.

Now, in the case of addition, if the number of digits of the second operand after the shift is greater than the number of digits of the first operand, it is clear that an overflow will occur, and the number of digits of the first operand +
Performing single-digit additions is wasteful. Therefore, the processing is separated into cases where it is actually an addition and cases where it is a subtraction, and in the case of an actual addition, an overflow check is performed using the number of digits of the first operand, and an addition corresponding to the number of digits of the first operand is performed. It is also conceivable that an overflow occurs if a carry occurs when calculating the most significant digit. However, even if this method is applied, it is still necessary to calculate the number of digits of the first operand plus one digit during actual subtraction, and it is not possible to speed up the processing of decimal addition/subtraction instructions.

(Problem to be Solved by the Invention) As mentioned above, in conventional shifted decimal operations, in consideration of the possibility that overflow will not occur, one digit from the number of digits of the decimal value string that is not to be shifted. There is a problem in that the processing speed of decimal addition/subtraction instructions cannot be increased because extra calculations must be performed.

This invention was made in view of the above circumstances, and its purpose is to increase the number of target digits for shifted decimal addition and subtraction by 1 compared to the conventional method.
It is an object of the present invention to provide a decimal arithmetic circuit that can reduce the number of digits and thereby improve the processing speed of decimal addition/subtraction instructions.

[Structure of the invention] (Means and effects for solving the problems) This invention provides a third decimal value sequence obtained by shifting a first decimal value string and a second decimal value sequence by a specified number of digits. The reason why there is a possibility that an overflow will not occur even if the number of digits in the third decimal value string is larger than the number of digits in the first decimal value string in addition and subtraction between the decimal value string and the decimal value string is that case and the third 10
By focusing on the fact that the number of digits in the least significant digit of the part of the decimal value string that exceeds the number of digits in the first decimal value string is 1, and by performing efficient overflow detection, This eliminates the need to add or subtract one digit more than the number of digits in the first decimal value string. A detection means is provided for detecting whether the numerical value of the least significant digit of the part exceeding the number of digits is 1 or 2 or more, and the detection result of this detection means is the first decimal value string and the third decimal value string. An overflow of the operation result is determined based on the carry output from the most significant digit when calculating the number of digits of the first decimal value string with the decimal value string and whether or not the operation content is actual addition. It is designed to perform detection.

(Embodiment) FIG. 1 shows a block configuration of a decimal arithmetic circuit according to an embodiment of the present invention, and FIG. 2 shows a block configuration of a data processing device equipped with the decimal arithmetic circuit of FIG.

In FIG. 2, 11 is a main memory, and 12 is an instruction execution control circuit that etches seven various instructions such as decimal addition/subtraction instructions from the main memory 11 and controls the execution of the instructions. A microprogram execution circuit 13 is activated by the instruction execution control circuit 12 to perform microprogram control processing.
14 is a decimal arithmetic circuit that performs one 10-selection operation in accordance with the microprogram control process of the μ program execution circuit 13.

The decimal addition/subtraction instruction is composed of 64 bits as shown in the format of FIG. 3, for example, and includes an instruction code oP indicating the instruction type, the storage address EA1 in the main memory 11 of the first operand, and the length of the first operand. Length value L1 indicating (number of bytes) -1, storage address EA2 of the second operand in the main memory 11, and length value L2 indicating (number of bytes) -1 of the second operand (here, the byte of the second operand) -1) and the shift number N (bits 40 to 43) for the second operand. Ll.

Both L2s have a 4-bit configuration, so the lengths of the first and second operands are 1 to 16 bytes. Further, bit 34 of the decimal addition/subtraction instruction shown in the third factor is N
If N is positive, it indicates a left shift, and if N is negative, it indicates a right shift. When it is negative, it is expressed in two's complement, so
One range of N is -32≦N×32.

FIG. 4 shows the format when the decimal value string handled by the above-mentioned decimal addition/subtraction instruction is a packed decimal number. In back format, 4 bits = 1 decimal digit (dO to dn)
, two digits are shown in one byte, and the code S is shown in the lower four bits of the least significant byte.

Now, as shown in FIG. 1, the decimal arithmetic circuit 14 in FIG.
Byte (8 bit) register 31 and this register 31
A code check circuit 32 that recognizes the code and removes the code when the byte data held in the byte is the least significant byte containing the code S, and the output data of this code check circuit 32 or the data held in the register 21. and a selector 33 for selecting either one. 10 more
The decimal calculation circuit 14 includes a 0 detection circuit 3 that detects whether each digit of data selectively output from the selector 33 is O or not.
4, a 1 detection circuit 35 that detects whether or not it is 1, and 2
2 to 9 detection circuit 36 that detects whether the
It has Furthermore, the decimal arithmetic circuit 14 includes an effective number of digits calculation circuit 37 that calculates the effective number of digits EDL of the second operand based on the O detection result of the 0 detection circuit 34, and a timing signal TM that uses the detection result of the 1 detection circuit 35. It has a 1-bit register 38 that latches in accordance with the timing signal TM, a 1-bit register 39 that latches the detection result of the output circuit 36 in accordance with the timing signal TM, and an overflow detection circuit 40. This overflow detection circuit 40 detects the length value L1 of the first operand, the shift number N of the second operand, the effective number of digits EDL which is the calculation result of the calculation circuit 37, and the fact that the addition/subtraction between the first operand and the second operand is A signal ACTA indicating whether or not it will be a virtual addition (or a substantial subtraction)
DD, carry output CARRY of the adder/subtracter (not shown) (in the decimal arithmetic circuit 14) that performs the above addition/subtraction, 1 detection result XD1 which is the data held in the register 38, and 2 to 9 which is the data held in the register 39. Detection result XD
29, overflow is detected and an overflow signal @0VFL indicating the result is output. This overflow detection circuit 49 is constructed using, for example, a gate array, and its overflow detection logic is shown in pseudo-coding form in FIG.

Next, the operation of one embodiment of the present invention will be explained with reference to the flowchart of FIG. 6 as appropriate.

Assume that the instruction execution control circuit 12 has now fetched an instruction from the main memory 11. When the instruction execution control circuit 12 fetches an instruction, it activates the μ program execution circuit 13 according to the instruction code. Instruction execution control circuit 12
If the instruction fetched by is a decimal addition/subtraction instruction shown in the format of FIG. 3, the μ program execution circuit 13 first retrieves the parameter values Ll, L2 in the decimal addition/subtraction instruction.

A process is performed to set N in a working register (not shown) of the decimal arithmetic circuit 14 (step 81).

Next, the μ program execution circuit 13 reads the second operand from the main memory 11 (step S2).The second operand is read one byte at a time starting from the most significant byte, and the read byte data is held in the register 31 of the decimal arithmetic circuit 14 each time. If the byte data held in this register 31 is the least significant byte of the second operand, that is, if it is a byte containing the code S, the code is recognized and removed by the code check circuit 32, and the selector 33 is fed to one input of The other input of this selector 33 is supplied with the byte data held in the register 31.

The selector 33 selects the data held in the register 31 if the byte data held in the selector 33 is not the least significant byte of the second operand, and selects the output data of the sign check circuit 32 if it is the least significant byte. select.

The selected output data of the selector 33 is guided to a 0 detection circuit 34.1 detection circuit 35 and a 2-9 detection circuit 36, and it is determined whether the value of each digit is 0 or 1.

Or any one of 2 to 9 is detected and held in a work register (not shown).

The 0 detection result of the 0 detection circuit 34 is led to the effective digit number calculation circuit 37, which calculates the effective digit number of the second operand by calculating the number of consecutive 0s (the number of leading 0 digits) from the most significant digit of the second operand. The number EDL is calculated. This effective number of digits EDL is supplied to an overflow detection circuit 40. On the other hand, the 1 detection result of the 1 detection circuit 35 is stored in the register 38.
The 2 to 9 detection results of the ~9 detection circuit 36 are led to the register 39, and by the timing signal TM given under the control of the μ program execution circuit 13, the 5 digits of the above result are shifted into the second operand. Only the least significant digit of the portion exceeding the area (length) of the first operand (this is called the phase to be checked from 1.2 to 9) is latched.

Here, the above-mentioned check target digit will be explained with reference to FIG. First, the number of digits of the second operand is shown in Figure 7 (
As shown in FIG. 7(b), the L2 tree is 2+1, and the number of digits of the first operand is 2+1, as shown in FIG. 7(b). The number of digits of the second operand after the shift is 12 trees 2+1+N as shown in FIG. 7(C). In this case, the phase to be checked is shown in Fig. 7 (d
), it is the L2 tree 2-L1 tree 10th Nth digit from the most significant digit of the second operand after the shift. That is, in this embodiment, the 1 detection result (by the 1 detection circuit 35) of the L2 tree 2 - L1 tree + Nth digit from the most significant digit of the second operand is stored in the register 38, and the 2 detection result (by the 2 to 9 detection circuit 36) is stored in the register 38. ~9 detection results are latched into the register 39. 1 detection result XDI of the phase to be checked of the second operand, which is the latch data of registers 38 and 39
, 2 to 9 detection results XD29 are the overflow detection circuit 40
supplied to Note that the values of registers 38 and 39 (XDI, XD
29) makes no sense.

Now, in step S2, the above-mentioned sign check, calculation of the effective number of digits EDL, and detection of phases 1, 2 to 9 to be checked are performed on the second operand that is sequentially read from the main memory 11 in 1-byte units. (Step $
3) The first operand is read from the main memory 11 by the μ program execution circuit 13 in order from the least significant byte (step 84). Then, the second
The code is checked and removed by the code check circuit 32 in the same manner as in the case of the operand, and the result is held in the work register via the selector 33 (step 8).
5). Next, types of decimal addition/subtraction instructions (addition/subtraction)
and the sign check result of the 1.2nd operand in step 33 and S5, it is determined whether the operation of the addition/subtraction circuit (not shown) in the decimal arithmetic circuit 14 is substantially addition or subtraction. Then, it outputs a signal ACTADD to that effect (that is, indicating the actual calculation mode) (step S6). This signal ACTADD is applied to the decimal arithmetic circuit 1.
The signal is supplied to the overflow detection circuit 40 of No. 4.

When the actual operation mode is determined by the μ program execution circuit 13, the decimal operation circuit 14 takes into account the shift number N so that the second operand held in the working register matches the scale of the first operand. Then, addition and subtraction by the number of digits of the first operand are performed in an addition/subtraction circuit (not shown) (step S7). A carry output CARRY during calculation of the most significant digit (the most significant digit of the actual operation target digit) in this addition/subtraction circuit is supplied to the overflow detection circuit 40.

When step S7 is completed, it is determined whether the operation in step S7 is actually a subtraction and the result is negative (step 88). If the determination in step $8 is YES, the result is converted into an absolute value (step S9), and an overflow check using the overflow detection circuit 40 is performed (step 510).On the other hand,
If the determination in step S8 is No, step S9 is skipped and an overflow check is performed in step 810.

As is clear from the overflow detection logic shown in FIG. ), the logic “1” indicates that there is an overflow, as in the past.
outputs an overflow signal 0VFL.

On the other hand, if the number of digits of the first operand +1 is not smaller than the number of digits of the second operand (effective part only) after shifting, the signal ACTADD is logic "1" (i.e., addition is not actually possible). Yes), and carry output CARRY, 1
If at least one of the detection result XD1 and 2 to 9 detection results or if the check umbrella digit is not O), the overflow signal of logic "1" is 0
VFL is output, and if it is not otherwise (i.e., no carry occurs when calculating the most significant digit and the digit to be checked is O)
If so), the overflow signal 0VFL becomes logic "ON".

Further, if the number of digits of the first operand + 1 is not smaller than the number of digits of the second operand (effective part only) after shifting, and the signal ACTADD is logic "011" (that is, if it is substantially a subtraction), , the carry output CARRY is logic “1” (correctly drawn), and the 1 detection result XD
If at least one of 1 and 2 to 9 detection results x D29 is logic "1" (that is, the digit to be checked is not 0), or the carry output CARRY is logic "OII" (that is, a borrow has occurred). ), and 2 to 9 detection results XD29
If is logic "1" (that is, the digit to be checked is not O or 1), overflow signal 0VFL of logic "1" is output, and otherwise, overflow signal 0VFL is logic "0". Become.

For example, as shown in Figure 8, if the first operand is 0000001 (Ll -3) and the second operand is 000000001 (, L2 -4), and N-7, the effective value of the second operand after the shift is The number of digits is
Exceed by one digit than the number of digits below the first operan. However, the result of subtraction in the above case (the value obtained by subtracting the first operand from the second operand after the shift) is as follows, which does not result in O-puff 0-. Conventionally, in consideration of this possibility, an operation (subtraction) with one digit more than the first operand was performed in order to correctly detect overflow.
was being carried out. On the other hand, in this embodiment, for example, in the case of the subtraction shown in FIG. Since the fact that the value of the digit to be checked is 1 (1 detection result There is no fear that

When the overflow check in step 310 is completed,
The sign of the addition/subtraction result is determined (step 511), a sign is added to the result based on this determination, the result with the sign added is stored in the first operand area in the main memory 11, and the overflow check result is stored in the condition code register. A store is performed (step 512) and one 10
The base addition/subtraction instruction processing ends.

In addition, in the above embodiment, 1, which is handled by the decimal addition/subtraction instruction,
The decimal value string (operation target, land) is in back format 10
Although the case of a base number has been described, the present invention can also be applied to the case of a zoned decimal number in which one byte represents one digit of the decimal number. In the zone format, as shown in the format of Figure 9, the lower 4 bits of each byte (excluding the least significant byte) represent a single decimal value, and the upper 4 bits (zone field) 2 represent a constant value. is set to the value of This 2 has no meaning for the numerical value represented by the decimal value string. Furthermore, the least significant byte represents a numerical value and a sign. Therefore, in the case of the zone format, the first . Second
The number of digits of the operand is Ll +1. It becomes Ll +2.

[Effects of the Invention] As detailed above, according to the present invention, the third decimal value string is obtained by shifting the first decimal value string and the second decimal value string by a specified number of digits. In addition and subtraction between and □, detect in advance whether or not the lowest digit of the part of the third decimal value string that exceeds the number of digits of the first decimal value string is 1. By adding this detection result to the overflow check of the addition/subtraction results described above, overflow detection can be performed correctly even if addition/subtraction II is performed one digit less than before (i.e., addition/subtraction for the number of digits in the first decimal value string). be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a decimal 'e4 arithmetic circuit according to an embodiment of the present invention, FIG. 2 is a schematic block diagram of a data processing device equipped with the decimal arithmetic circuit of FIG. 1, and FIG. 10
A diagram showing the format of the base addition/subtraction instruction, Figure 4 is the same as 1 above.
A diagram showing the format of a back-format decimal number handled by the 0-base addition/subtraction instruction. FIG. 5 is a diagram showing the overflow detection logic of the overflow detection circuit 40 shown in FIG. 1 in the form of pseudo coding. FIG. 6 is a diagram showing the decimal addition/subtraction A flowchart showing the instruction processing procedure, FIG. 7 is a diagram explaining the phases to be checked, and FIG. 8 shows an example of subtraction that does not cause an overflow even when the number of digits of the second operand after shifting is greater than the number of digits of the first operand. 9 are diagrams showing the format of zoned decimal numbers. 11... Main memory, 12... Instruction execution control circuit, 13
... μ program execution circuit, 14 ... Decimal calculation circuit, 34 ... 0 detection circuit, 35 ... 1 detection circuit, 3
6... 2 to 9 detection circuit, 31... Effective digit number calculation circuit, 40... Overflow detection circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 1 Pieced, logical sum &... logical product Figure 6 N digit Figure 7

Claims (1)

[Claims] Between the first decimal value string and the third decimal value string obtained by shifting the second decimal value string by a specified number of digits, the number of digits in the first decimal value string is Addition and subtraction means for performing addition or subtraction operations, and a number of least significant digits of the portion of the third decimal value string that exceeds the number of digits of the first decimal value string is 1 or 2 or more; Based on the detection result of the first detection means, the last carry output from the arithmetic means, and whether the content of the arithmetic operation of the arithmetic means is substantially addition, A decimal arithmetic circuit comprising: second detection means for detecting overflow of arithmetic results.