JPS61285539A - Information processor - Google Patents

Abstract

PURPOSE:To secure the accurate synchronism between an instruction and the exceptional information on the instruction despite the increase of the number of stages, by giving the stage control to the exceptional information detected by each control unit of a pipeline. CONSTITUTION:The exception detected by an advance control unit 1 is reported to an encoder 40. Then the encoder 40 resets an FF 70 to invalidate the stage C of a control storage unit 2 and at the same time transmits the produced representative exceptions and their codes successively to registers 50-54. While the exception detected by an arithmetic unit 3 is reported to an encoder 41 at the stage F. The encoder 41 produces the representative exceptions and their codes and applies the holding signals to registers 56 and 58. Thus the 1st step of the microinstruction corresponding to the exceptional code held by an address register 21 is given to a control storage register 22. Then an exception processing microinstruction routine is started.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device using a pipeline control method.

[Conventional technology]

Conventionally, in this type of information processing apparatus, the number of pipeline stages is small, and there is no need for stage management of exception information by hardware.

[Problem that the invention seeks to solve]

However, in recent years, when the number of pipeline stages has been increased as clock cycles have become faster, a problem has arisen in that an instruction and the exception information of this instruction cannot be synchronized, making it impossible to manage the exception information. For this reason,
solve this problem.

There has been a demand for an information processing device that can efficiently perform exception identification control.

[Means for solving problems]

In order to solve these problems, the present invention provides a preceding control unit that detects exception information, a control storage unit that can operate according to instructions from this preceding control unit, an arithmetic unit that detects arithmetic exceptions, and a preceding control unit that detects exception information. The exception identification control unit encodes the exception information reported from the unit and the arithmetic unit, stages the encoded exception information, and activates the exception processing routine of the control storage unit.

[Effect]

In the present invention, even if the number of pipeline stages is increased, the synchronization between an instruction and the exception information of this instruction will not be lost.

〔Example〕

Next, an embodiment of an information processing apparatus according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a system diagram showing one embodiment. In FIG. 1, 1 is a preceding control unit, 2 is a control storage unit, 3 is an arithmetic unit, and 20
is a control memory, 21 is an address register, 22 is a control storage register, 40.41 is an encoder, 50 to 58 are registers, 60.61 is a selector, 70 is a flip-flop,
100~102,200,201,210,220.3
00.400～402,410,411゜500.50
1,510,511,520,521.530,531
,540,541.550~552.560~562,
570, 571.580.600, 610.700 are signal lines.

Advance control unit 1. Control storage unit 2. The arithmetic unit 3 and the exception indexing control unit are each configured in a pipeline system in which a series of instructions are processed in an overlapping manner in a temporally staggered manner. The exception indexing control unit includes the preceding control unit 1. Control storage unit 2. This unit has the functions depicted outside the frame of the calculation unit 3.

As shown in Figure 1, the stages of the pipeline are, in order from the top stage, A stage, B stage, C stage, D stage, and E stage.

It consists of 8 stages: F stage, C stage, and H stage.

The advance control unit 1 fetches an instruction, decodes this instruction, fetches an operand of this instruction, detects an exception related to the instruction fetch and operand fetch of this instruction, and controls the detected exception via a signal line 102 to determine the exception. Report to the unit.

Further, the advance control unit 1 supplies the selector 60 via the signal line 100 with the address of the first step of the microprogram consisting of one step or a plurality of steps corresponding to the above instruction stored in the control storage unit 2. ,
The selection signal S1 of the selector 60 is sent through the signal line 101, the selector 60 selects the address of the first step of the microprogram, and the selected signal is applied to the address register 21 of the control storage unit 2 through the signal line 600. This activates the microprogram corresponding to the above instruction.

The advance control unit 1 occupies the stage before the A stage, the A stage, and the B stage, and inputs the address of the first step of the microprogram corresponding to the command given to the selector 60 via the signal line 100 and the signal line 101. The selection signal S1 of the selector 60 sent out via the signal line 102 exists in the stage before the A stage, and the exception detection signal reported via the signal line 102 exists in the B stage.

The control memory unit 2 includes a control memory 20 that stores a plurality of microinstructions, an address register 21 that holds the address of the control memory 20, and a control unit that controls the arithmetic unit 3 in response to the microinstructions stored in the control memory 20. It is composed of a storage register 22. The selector 60 normally sends the branch destination address of the microinstruction stored in the control memory 20 to the signal line 201 when an instruction is activated or an exception is identified.
and supplies it to the address register 21 via the signal line 600. Address register 21 is selector 60
The selected address is received via the signal line 600, and the address is given to the control memory 20 via the signal line 210.

The control storage register 22 receives signals other than the branch destination address of the microinstruction corresponding to the address held in the address register 21 via the signal line 200, and controls the arithmetic unit 3 via the signal line 220. The control storage unit 2 occupies the A stage and the B stage. address register 21
and control memory 20 are present in the A stage, and control memory register 22 is present in the B stage.

The arithmetic unit 3 executes an arithmetic operation using a control signal held in the control memory register 22 of the control memory unit 2 via a signal line 220, and sends an exception detected by the arithmetic operation to a signal vA3.
00 to the exception indexing control unit. The arithmetic unit 3 occupies four stages: C stage, D stage, E stage, and F stage, and exceptions generated by the arithmetic operation are reported at the F stage via a signal line 300.

Exceptions detected by the advance control unit 1 are reported to the encoder 40 via the signal line 102. The encoder 40 is a priority encoder and has a function of prioritizing and encoding the exception detected by the preceding control unit 1 and generating an exception detection signal. Here, the exception detection signal is referred to as an exception representative.

The exception detected by the preceding control unit 1 is this encoder 4.
0 is converted into an exception representative detected by the preceding control unit 1 and an exception code, which are reported to the register 50 via signal lines 400 and 401, respectively.

Registers 50 to 54 are registers that carry the exception representative detected by the preceding control unit 1 and the exception code corresponding to the stages of the pipeline, and registers 50 to 54 are used for the C stage, D stage, E stage, F stage, and G stage, respectively. exists in The registers 50 to 54 holding the preceding control unit 1 detected exception representative 2 exception code and the selector 61 are connected to signal lines 500, 501, 510 and 511.5, respectively.
20, 521, 530, 531, 540, and 541.

Exceptions detected by the arithmetic unit 3 are reported to the encoder 41 via a signal line 300. The encoder 41 is a priority encoder and has a function of prioritizing and encoding the exception detected by the arithmetic unit 3 and generating an exception detection signal.

Here again, the exception detection signal is referred to as an exception representative. The exception detected by the arithmetic unit 3 is converted by the encoder 41 into an arithmetic unit 3 detected exception representative and an exception code, and these are reported to the register 55 via signal lines 410 and 411, respectively. The register 55 is a register that receives an exception representative detected by the arithmetic unit 3 and an exception code, and is present on the G stage.

The selector 61 connects the registers 54 and 55 to the signal line 5.
41 and 551, and is selected via a signal line 540 by the exception representative held in the register 54. The exception code selected by selector 61 is applied to register 57 via signal line 610. Further, the exception representatives of registers 54 and 55 are logically summed and provided to registers 56 and 57 via signal line 552.

Register 56 is a register on the H stage, and register 5
The exception representative number 6 becomes the selection signal SO of the selector 60 via the signal line 560, which instructs the selector 60 to select the address of the first step microinstruction of a microprogram consisting of a plurality of microinstructions for handling the exception. Then, this selected address is set in the address register 21. The exception representative in register 56 also serves as an input signal to register 58.

The register 57 is also a register on the H stage, and the signal line 55
2.610, receives the exception representative and the exception code selected by the selector 61. The exception representative of the register 57 becomes a hold signal of the register 57 itself via a signal line 570. Also, the exception code in the register 57 is on the signal line 57.
1 to the selector 60, and is connected so that the address of the first step microinstruction of the exception processing microprogram corresponding to the exception code can be given to the address register 21.

Register 58 connects the exception representative of register 56 to signal line 560.
The exception representative in the register 56 receives the microinstruction corresponding to the address of the first step of the microprogram that performs the exception handling corresponding to the exception code set in the address register 21 via the signal line 580. Set in the control storage register 22. flip flop 7
0 is a flip-flop that indicates whether the operation of the control storage unit 2 is valid or invalid, and a state of "1" indicates validity and a state of "0" indicates invalidity.

Next, the operation when an exception is detected in the advance control unit 1 or the arithmetic unit 3 and the exception detection control is performed is shown in FIGS. 1 and 2.
This will be explained with reference to FIGS.

2 and 3 are time charts showing exception detection control, FIG. 2 shows the exception detected by the advance control unit 1, and FIG. 3 shows the exception detected by the arithmetic unit 3. It shows the index.

In FIG. 1, the exception detected by the advance control unit 1 is reported to the encoder 40 of the exception indexing control unit via the signal line 102 in the B stage.Here, the number of causes of the exception detected by the advance control unit 1 is For the sake of simplicity, there are eight factors. Therefore, eight signal lines 102 are required. Since the number of exception factors detected by the advance control unit 1 is 8, the encoder 40 has a function of taking the priorities of the 8 factors, converting them into a 3-bit code, and calculating the logical sum of the 8 factors. Here, the eight preceding control unit 1 detected exception causes are listed in descending order of priority, P0 to P? , and if the exception detection signal (exception representative) detected by the encoder 40 is V, then V1=Po+P, +P1+Ps+Pa+Ps+Pi+P
It is t. Here, + indicates a logical sum. The exception code generated by the encoder 40 only needs to express 8 factors, so 3
It becomes a bit code. This 3° bit code C6°~Cat and the exception cause P. -P? The relationship between V and the representative exception V is expressed in the truth table of Table 1 on the next page.

When the encoder 40 detects the cause of the exception in the preceding control unit 1, the flip-flop 70 in the set state "1" is set to the reset state "0" in the exception representative (2). The flip-flop 70 indicates the valid state of the control storage unit 2. When the flip-flop 70 is reset, the control storage unit 2 stores the exception representative V generated by the non-encoder 40.
, and the exception codes cv, o""cat are sent to the register 50.

As shown in the time chart of FIG. 2, from now on, register 5
1 to 54 are sequentially transmitted corresponding to clock cycles. This is sequentially transmitted (signals are transmitted to each register 50~
54, the exception representative bits are Vc,
V D, V t, V F, V Go, exception codes are Cc0~cc! ,C1,. ~CDt,cE0~co
.

CF6~C,t,C,. . ~C,. It is called 2. The contents of the signals held and transmitted are shown below. However, RG represents a register.

RG50: Tadashi] Ii Wataru■! F, C stage RGRG51
: Vn Cl16CDIC, D stage RGRG
52: Vt CtoCt+Ctt, E stage RGRG53: VF CFOCFIC, E stage') RGRG54: VcoCcoo Cc, oI
CGO! , G stage RG In FIG. 2, a w d indicates that an instruction or microinstruction step exists on a certain stage or register. a flows through the pipeline sequentially from the upper stage to the lower stage without generating an exception. b is an instruction or microinstruction step following a, generates an exception, and is subject to exception allocation control. In FIG. 2, b flows sequentially through the pipeline from the A stage, an exception is reported by the advance control unit 1 on the B stage, and the encoder 40 in FIG. 1 outputs the exception representative Vl and the exception code Cl. ~Cat is generated, the flip-flop 70 is reset at clock t4 in FIG. 2, and the exception representative vll and exception code CIO~c!
l! is transmitted to the register 50. The exception 1 table vc and the exception codes C6° to CCt held by the register 50 sequentially advance through the stages of registers 51, 52, 53° and 54 in synchronization with clocks t, to t. The 4 exception representative VG held by the register 54 (1 and the exception code CG+1° to C6°2 are selection 2
61, the exception representative v0° is selected.

Further, the exception number detected by the arithmetic unit 3 in FIG. 1 is reported to the encoder 41 of the exception indexing control unit via the signal line 300 at the F stage. Here, the number of exception causes detected by one arithmetic unit 3 is assumed to be 8, which is the same as the number of exception causes detected by the preceding control unit 1, 2, for the sake of simplicity. Therefore, one signal line 300 is required. Since the number of exception factors detected by the arithmetic unit 3 is 8, the encoder 41 has the function of taking the priority of the 8 factors, converting them to a 3-bit code, and calculating the OR of the 81 codes. Here, each of the eight 6-arithmetic unit 3 detection exception causes is BRIO.

If the exception detection signal (exception representative) detected by the encoder 4 is 1, then e Vx= IO+ I ++ Iz+ 13+
14+ l, + l, + 1. It is t. Here, + indicates a logical sum. The exception code generated by encoder 41 is 8
It would be nice if it could express a prisoner in need, so it would be a 3-pinto code. The relationship between the 3-bit 1 codes C1° to C+Z, the exception causes 10 to 7, and the exception representative v1 is expressed by the truth table in Table 2.

When the error factor of the arithmetic unit 3 is detected by the encoder 41, the flip-flop 70 in the set state a(rlJ) is set to the reset state (rOJ) with the exception representative V. Here, it is assumed that no exception was detected in the advance control unit 1 and the flip-flop 70 was in the cent state.

The exception representative (1) and exception codes CIO to C+Z generated by the encoder 41 are sent to the register 55.

As shown in the time chart of FIG. 3, the clock t.

The value is fixed in register 55. The exception representative held by the register 55 is V G l + the exception code is C0°~CGIt
It is called. The contents of the signals held and transmitted are shown below.

However, RG represents a register.

RG 55: VaIC61 (ICGI.C,,2
, c stage RG In FIG. 3, a w h indicates that an instruction or microinstruction step exists on a certain step or register. A flows through the pipeline from the upper stage to the lower stage without generating an exception. b is an instruction or microinstruction step following a, generates an operation exception, and is subject to exception allocation control. In FIG. 3, b flows sequentially through the pipeline from the A stage, an exception is reported by the arithmetic unit 3 on the F stage, and the encoder 41 in FIG. 1 generates an exception representative V and exception codes C1° to C+Z. Then, at t in FIG. 3, the flip-flop 70 is reset, and the exception representative ■1 and exception codes C111 to C1
5. Exception representative VOI held by register 55
and exception code CG I. ~C6° is selected by the selector 61.

The selector 61 has a function of selecting and identifying an exception code detected by the advance control unit 1 and encoded by the encoder 40 and an exception code detected by the arithmetic unit 3 and encoded by the encoder 41. If the selection signal of the selector 61 is S, then the following is true. Here, the selection signal S is the exception representative vG0 held by the register 54. That is, S=V. . It is.

Selector 61 has a 4-bit output to distinguish between 3-bit and 3-bit codes. The most significant bit of these 4 bits is a bit that identifies the preceding control unit 1 detected exception and the arithmetic unit 3 detected exception.When it is "0", it is the preceding control unit 1 detected exception, and when it is "1", it is the arithmetic unit 3 detected exception. do. The 4-bit exception codes output by the selector 61 are called 00 to C3. The relationship between the 4-bit exception codes C0 to C5 output by the selector 61, the exception causes P0 to P7 detected by the advance control unit 1, and the exception causes 10 to I7 detected by the arithmetic unit 3 is shown in Table 3 on the next page. .

4-bit exception code C0 to C1 output by selector 61
is applied to the register 57 on the H stage via the signal line 610. The exception representative v6° held by the register 54 and the exception representative Va+ held by the register 55 are logically summed to become the exception representative vH of the register 57 and the input signal of the register 56. The contents of the signals held and transmitted are shown below. just"
RG is a register.

represents.

RG 57: Vn CHOCMI CuzCH3,
The exception representative vH held by the H stage RG register 57 is a hold signal of the register 57 itself, and the exception representative V,
and exception representative code CH0~CH! Continue to hold. Exception code CM. is the address of the first step of the microprogram that handles the exception. That is, 16 types of exception handling microprograms can be activated.

If the hold signal of register 57 is H5'l, Hs
t=VH. The purpose of holding the register 57 here is to keep the history of the exception code.

Register 56 is a register on the 1-bit H stage.
The signal held by this register 56 is assumed to be 85°. The contents of the signals held and transmitted are shown below.

Register 56: I■1), H stage register The signal SS& held by the register 56 is the address 00 to the microinstruction word of the first step of the microinstruction routine that performs the exception handling corresponding to the exception code selected by the selector 60.
C1 and gives this address to the address register 21 of the control storage unit 2, and also to the register 58.
It also serves as an input signal.

Register 58 is a register on the 1-bit A stage.
The signal held by this register 58 is assumed to be 351. The contents of the signals held and transmitted are shown below.

Register 58: [, A stage register register 58
The signal SSM held by the address register 21 provides the control storage register 22 with a microinstruction corresponding to the address of the microinstruction in the first step of the microinstruction routine that performs the exception handling corresponding to the exception code held in the address register 21. The address of the microinstruction is given to the address register 21, the flip-flop 70 in the reset state is set, the control storage unit 2 is enabled, and the exception handling microinstruction routine is activated to perform exception handling.

The signal held by the flip-flop 70 indicates the valid/invalid state of the control storage unit 2, with "1" indicating the valid state and "0" indicating the valid state.
” and is in an invalid state. This signal is called rVJ. If the reset signal of the flip-flop 70 is R3T, then R5T=V, +V.

and is reset when an exception is detected. Further, Patent No. 5ET=Ssa is characterized by a set signal of the flip-flop 70. The flip-flop 70 is set at the same time that the first step microinstruction for performing exception handling is determined in the control storage register 22.

Hold signals of registers 50 to 56.58 are always rOJ
So, it is 0 clamp. The hold signal HtI of the address register 21 is Hzt=V+Ssh+Sss. The hold signal H of the control storage register 22 is Htz=V+Sss.

Assuming that the selection signal of the selector 60 is So, 31, the results are as shown in the following table.

If rFJ is a signal that selects and instructs the address of the first step microinstruction corresponding to the instruction sent from the preceding control unit 1 via the signal line 101, then S O = S sh l -F.

The branch destination address when so, 5t=o, o shown in the above display is the branch destination address of the microinstruction stored in the control It memory 20 that corresponds to the microinstruction address held in the address register 21. ,SO,
The instruction first address when 51=0.1 is the address of the first step of the microinstruction corresponding to the instruction sent by the advance control unit 1 to the control storage unit 2, and
The exception handling first address of O,5l-1,0 is the address of the first step microinstruction of the microprogram that performs exception handling, and is a fixed value.

EXO to EX of the address register 21 in FIGS. 2 and 3
2 indicates the address of a microinstruction that performs exception handling.

〔Effect of the invention〕

As explained above, the present invention includes a preceding control unit that detects exception information, a control storage unit that can operate according to instructions from this preceding control unit, an arithmetic unit that detects an operation exception, and a preceding control unit and an arithmetic unit. By providing an exception identification control unit that encodes the exception information to be reported, manages the stages of this encoded exception information, and activates the exception handling routine in the control storage unit, pipe processing becomes faster as the clock cycle speeds up. Even if the number of stages in a line is increased, exception information is managed without disrupting the synchronization between an instruction and the exception information of this instruction, and a microprogram that efficiently performs exception handling corresponding to the exception code is started and the exception processing It has the effect of

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an embodiment of the information processing device according to the present invention, FIG. 2 is a time chart showing exception identification control when an exception is detected by the preceding control unit, and FIG. 5 is a time chart showing exception identification control when an exception is detected. l...preceding control unit, 2...control memory unit, 3...arithmetic unit, 2o...control memory, 21...address register, 22...control memory register , 40.41... Encoder, 50-5
8...Register, 60.61...Selector, 70
...Flip-flop, 100-102.200,
201°210.220,300,400~402,4
10.411,500,501,510,511゜52
0.521,530,531,540,541.550
〜552.560〜562,570゜571.580,
600, 610.700...Signal line.

Claims (1)

[Claims] In an information processing device using a pipeline control method, which processes a series of multiple instructions in an overlapping manner while staggered in time so that the same cycle of instructions does not overlap, fetching of an instruction, decoding of this instruction, and operand of this instruction are performed. fetch,
A preceding control unit that detects exceptions related to the instruction fetch and operand fetch of this instruction, a control memory unit that can operate according to the instructions of this preceding control unit, and a control memory unit that executes operations under the control of this control memory unit. an arithmetic unit that detects an arithmetic exception; and an arithmetic unit that encodes the exception information reported from the preceding control unit and the arithmetic unit and that is detected at multiple stages of the pipeline, stages manage this encoded exception information, and encodes the coded exception information. an exception identification control unit that uses the exception information as part of an address of a control memory constituting the control memory unit to start an exception handling routine consisting of a plurality of microinstructions in the control memory unit corresponding to the exception information; An information processing device characterized by comprising: and performing effective exception handling.