JPS6320855A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To fix a plurality of conductive connecting grains efficiently to pads, and to improve the productivity of a semiconductor device remarkably by temporarily fastening the connecting grains onto a support substrate, arranging a semiconductor substrate, on which the pads are formed, and fixing and moving the connecting grains to the pads. CONSTITUTION:A process in which conductive connecting grains 24 are shaped, a process in which a plurality of the connecting grains 24 are disposed and fastened at desired positions on a support substrate 22, a process in which a semiconductor substrate 16, to which semiconductor elements are formed minimally and on the surface of which pads 12, 13 are shaped, is arranged onto the support substrate 22 so that the connecting grains 24 on the substrate 22 and the pads 12, 13 on the semiconductor substrate 16 coincide, and a process in which the connecting grains 24 are fixed to the pads 12, 13 on the semiconductor substrate 16 and shifted to the pad side are provided. Accordingly, a plurality of the conductive connecting grains 24 can be fastened efficiently to the pads 12, 13 on the semiconductor substrate 16, and the method can be applied effectively for manufacturing a semiconductor device having three-dimensional structure enabling multifunction and having the high degree of integration and high reliability.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device in which the process of forming continuous grains on pads on a semiconductor substrate is improved. It is related to the manufacturing method.

(Prior Art) Conventionally, in a semiconductor II, in order to connect a pad that is a signal input/output terminal to an external substrate, a bump is formed on the pad by plating means. However, with this method, the bumps could not be grown to a sufficient size, and the plating method required a complicated process.Additionally, the bumps were hard and the reliability of bonding with the external board was low. .

For this reason, the applicant has decided to use metals, especially soft A.
We proposed a method in which connecting grains made of LIf)AR are fixed to pads, and then fixed and connected to an external substrate via the connecting grains.

Hereinafter, the method of fixing the connected grains to the pad will be explained in detail with reference to the connected grain fixing machine 3 shown in FIG. 7, which is comprised of a gun WI2 having an inner diameter of 40 μm and is provided with a heater 1 on the outside.

First, the semiconductor substrate 5 on which a plurality of pads 4 are formed is placed on a support stand (not shown) that includes a built-in heater. Subsequently, after aligning the gun barrel 3 with the pad 4 of the semiconductor substrate 5, the gun barrel 2 is maintained at about 350° C. by the heater 1.
Inside the gun barrel 2? ! ! Connected grains 6 made of Au having a spherical shape of 40 μm are inserted, and the connected grains 6 are heated with compressed nitrogen 7 while being accelerated so as to be placed on the pad 4 heated to about 30° C. by the support table. It is fixed by hot pressure welding.

However, in the conventional method for fixing connected grains, a plurality of connected grains cannot be fixed to pads of a semiconductor substrate at the same time, resulting in a problem that the productivity of semiconductor devices is low.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned conventional problems, and is a semiconductor device capable of efficiently fixing a plurality of conductive connected grains to pads of a semiconductor substrate. The present invention aims to provide a method for manufacturing.

[Structure of the Invention] (Means for Solving the Problems) The present invention comprises a step of forming conductive connected grains, a step of arranging and fixing a plurality of said connected grains at desired positions on a support substrate, a step of arranging a semiconductor substrate on which at least a semiconductor element is formed and a pad formed on the surface thereof on the supporting substrate so that the connecting grains match the pads of the semiconductor M11; This method of manufacturing a semiconductor device is characterized by comprising the steps of fixing the semiconductor device to the pad of the semiconductor device and moving the semiconductor device to the pad side.

(Function) The present invention temporarily fixes a plurality of conductive connecting grains on a supporting substrate in advance in a desired arrangement state, and attaches a semiconductor substrate on which a parid is formed on the supporting substrate so that the pads match the connecting grains. By arranging the conductive particles in such a manner that the conductive particles are fixed to the pads and transferred to the same pads, the plurality of conductive bonded particles can be efficiently fixed to the pads of the semiconductor substrate, and the productivity of semiconductor devices can be significantly improved. .

(Embodiments of the Invention) Hereinafter, an example in which the present invention is applied to manufacturing a three-dimensional LSI will be described in detail with reference to the drawings.

(I) First, the thickness was 450μ by two-dimensional LSI manufacturing method.
Semiconductor elements and wiring between the elements (
50 μm x 50
Pads 12 and 13 of μm were formed. Among these pads, a part of the pad 13 corresponding to a connecting hole described later is embedded in an opening formed in an interlayer insulating film, and a thin oxide film is formed on the substrate surface at the bottom of the opening. is formed. This oxide film is used to prevent the pad from being electrically connected to the substrate surface, which would interfere with the die sort test. However, instead of the thin oxide film, an impurity diffusion layer for forming a pn junction may be formed on the peripheral substrate surface including the bottom of the opening.

Next, the silicon wafer 1 corresponding to the pad 13 is
A wine cup-shaped hole 14 with an opening of 30 μm x 30 μm and a depth of 50 μm was formed on the back surface of the substrate 1 by a combination of isotropic etching and anisotropic etching (as shown in FIG. 1(a)).
. Note that etching was performed using fluorine-based or chlorine-based gas plasma.

(II) Next, after performing a die word test on the silicon wafer, dicing was performed to produce individual chips, and a good chip 15 was obtained by sorting (Fig. 1(b)
). Next, the entire back surface of the non-defective chip 15 is anisotropically etched to produce a thin plate-like semiconductor substrate 16 having a thickness of 45 μm (as shown in FIG. 1C). In this anisotropic etching process, the wine cup-shaped hole 14 opened on the back surface is etched while substantially maintaining its shape, so that a tapered connecting hole 17 is formed. Further, during the etching, the thin oxide film at the bottom of the opening was removed, so that a part of the pad 13 was exposed at the bottom of the connecting hole 17 corresponding to the opening.

(I[I) Next, spherical connecting particles made of, for example, Au are fixed in the connecting holes 17 of the semiconductor substrate 16 for lamination,
This method will be explained in detail using the steps shown in FIGS. 2(a) to 2(C).

First, a glass support substrate 22 with a thickness of 1 m on which convex portions 21 are formed around the area including the portion where the connected grains to be described later are temporarily fixed is used, and the surface of the support substrate 22 including the convex portions 21 is coated by spin coating. A polyimide film 23 having a thickness of 8 to 10 μm was formed by the method, and the solvent was volatilized by heating at 150° C. for 30 minutes. The polyimide film 23 thus formed was soft and had some stickiness because it was not baked at a high temperature. Note that the polyimide 1123 has a mark (not shown) for alignment with a semiconductor substrate, which will be described later.
is formed by etching or the like. Subsequently, connection branches 24 made of AU having a spherical shape of 30 μm in diameter were temporarily fixed on the polyimide film 32 at the same array position as the pads 3 of the semiconductor substrate 6 manufactured in FIG. figure(
a) As shown).

Next, as shown in FIG. 2(b), the glass support substrate 22 is
The semiconductor substrate 16 was arranged so that the connection hole 17 having the pad 13 of the substrate 16 coincided with the connection branch 24 of the support substrate 22. Since the support substrate 22 is made of transparent glass, this alignment is performed by a mark (not shown) formed on the polyimide film 23 from the back side of the support substrate 22 and a mark (not shown) attached to the back surface of the semiconductor substrate. This was done by moving the semiconductor substrate 16 so that the Note that 18 in FIG. 2(b) is an insulating layer for electrically insulating the substrate 16 and the pad 13, and one is formed on the insulating film 18 to connect a part of the pad 13 to the above-mentioned connection. This is an opening for exposing the bottom of the hole 17. Next, the semiconductor substrate 16 is heated to 300° C. from the pad 13 side of the semiconductor substrate 16 using a holding jig 25 having a heating mechanism.
6 and the glass support substrate 22, A
The connecting branch 24 made of U contacts the pad 13 made of A2 at the upper part of the connecting hole 17 of the substrate 16, and forms an intermetallic compound of Au-A2 to be fixed (as shown in FIG. 2C). In this step, the supporting substrate 2 to which the connecting branches 24 are temporarily fixed
Since the convex portion 21 is formed on the two parts, the connecting branch 24
When inserting the connecting branch 24 into the connecting hole 17 of the substrate 16, the connecting branch 24 is inserted into the upper pad 1 inside the connecting hole 17 without the polyimide film 21 on the supporting substrate 22 coming into contact with the back side of the substrate 16.
You can contact 3. Note that it is also possible to apply ultrasonic waves to the holding jig 25 to further promote fixation of the connecting branches, or to perform fixation at low temperatures. Thereafter, the connecting branches 24 were peeled off from the polyimide 1123 by moving the glass support substrate 22 downward. Through these steps, Figure 1 (d)
A semiconductor substrate 16 for lamination was obtained in which a connecting branch 24 of Au was fixed to the exposed portion of the pad 13 corresponding to the connecting hole 17 shown in )'.

(IV) Next, a thickness of 45
A 50 μm×50 μm pad consisting of a semiconductor element, wiring between elements, and ARIII was formed on a 0 μm silicon wafer. Subsequently, after the die sort test, the silicon wafer is diced, good chips are selected, and spherical connecting branches made of, for example, Au are fixed onto the pads on the surface of the good chips. Steps a) to (C) will be explained.

First, a polyimide film 32 with a thickness of 8 to 10 μm was formed on the surface of a glass support substrate 31 with a thickness of 1 μl by a spin coating method, and was baked at 150° C. for 30 minutes to volatilize the solvent. The polyimide film 32 thus formed was soft and had some stickiness because it was not baked at a high temperature. Note that the polyimide 1123 has a mark (not shown) for alignment with a semiconductor substrate, which will be described later.
is formed by etching or the like. Next, connecting branches 33 made of Au and having a spherical shape of 40 μm in diameter are temporarily fixed on the polyimide film 32 at the same alignment position as the pads of the good chip (as shown in FIG. 3(a)).

Next, as shown in FIG. 3(b), the glass support substrate 31 is
A non-defective chip 34 manufactured by the method described above was placed so that the pads 35 on its surface matched with the connecting branches 3.3 of the support base Ifi31. This alignment is performed using the supporting substrate 3.
Since the chip 1 is made of transparent glass, a mark (not shown) formed on the polyimide film 32 from the back side of the support substrate 31 and a mark (not shown) attached to the back side of the good chip 34 are checked so that they match. This was done by moving the chip 34. Note that 36 in FIG. 3<b> is an interlayer insulation a for electrically insulating the chip 34 and the pad 35.
It is m. Subsequently, by pressing the good chip 34 and the glass support substrate 31 together while heating the good chip 34 to 300° C. from the non-defective chip 34 side with a holding jig 37 having a heating mechanism, the connected grains 33 made of Au are applied to the surface of the non-defective chip 34. A of
2 and formed an intersynthetic compound of Au-An, which was fixed (as shown in FIG. 3(C)).

Thereafter, by moving the glass support substrate 31 downward, the connected grains 33 were peeled off from the polyimide film 32 hs. Through these steps, as shown in FIG. 1(e), 40! Connected grains 33 made of ALI having a spherical shape with a diameter of m were fixed.

(V) Next, the semiconductor substrate 16 for lamination produced by the steps <I) to (I[) above is placed on the good product depth 34 produced in the step (IV) above, and is made of Au on the pad 35 of the chip 34. Connecting grain 33 and connecting hole 1 of semiconductor substrate 1G
After aligning so that the connected grains 24 made of AU in 7 are aligned, the semiconductor substrate 16 for lamination is pressed against the chip 34 while heating to 300° C., thereby forming the connected grains 33.
24 were fixed together (as shown in FIG. 1(f)). Continuing.

T? A predetermined pad 12 on the surface of the semiconductor substrate 16 with a width of 4 m
．． 13 (shown in FIG. 1 (Q)).

(Vl) Then, by the same steps as (I) to (II) above? ! ! Several thin plate-shaped single-layer semiconductor substrates are manufactured, and these semiconductor substrates are sequentially stacked on top of the semiconductor substrate 16 laminated as shown in FIG. % stacked semiconductor devices (not shown)
was manufactured.

According to the method of the present invention, a plurality of connected grains 24 made of Au are temporarily fixed in advance in a desired arrangement on the polyimide 1123 of a glass support substrate (for example, 22), and the pads 13 are placed on this support substrate 22. The formed semiconductor substrate 16 is arranged so that the pad 13 matches the connected grain 24, and the connected grain 24 is fixed to the pad 13 and transferred to the pad 13, thereby forming a plurality of connected grains 24. can be efficiently fixed to the pad 13 of the semiconductor substrate 16. Moreover,
Connection grain 3 made of Au to the bad chip 35 of the good chip 34
3 is similarly fixed using the glass support substrate 31 coated with polyimide PA32, so a plurality of connected grains 3
3 can be efficiently fixed to the pads 35 of the good chip 34. Therefore, the semiconductor If! productivity can be significantly improved.

In addition, in the semiconductor device manufactured by this method, there is a space between the non-defective chip 34 on which the semiconductor element, etc. is formed and the semiconductor substrate 16 for the V44 layer on which the same element is formed, and furthermore, in each layered semiconductor M temporary 16. A between the exposed part of the pad 13 corresponding to the connection hole 17 of the semiconductor substrate 16 for lamination and the mating pad 35.
Fixed via connected grains 33, 24, 38 consisting of u, Vl
Since the i-layer is formed, a semiconductor device having a highly integrated and multifunctional three-dimensional structure can be obtained.

Furthermore, since the lamination between the non-defective chip 34, the semiconductor substrate for lamination 16, and each of the semiconductor substrates for lamination If116 is performed by the connecting grains 33, 24, and 38 made of Au, thermal stress can be absorbed by the AU grains 33, 24, and 38. Since it can be absorbed, it is possible to prevent the occurrence of racks like in conventional 5othxa. Furthermore, for the same reason, a desired gap can be formed between the non-defective chip 34 and the semiconductor substrate 16 for faffl, so that heat is not trapped between the respective substrates, and heat dissipation is improved. Therefore, a semiconductor device having a highly reliable three-dimensional structure can be obtained.

In the above example, the connected grains were temporarily fixed using a semi-cured polyimide film formed on a glass support substrate, but the present invention is not limited to this, and as shown in FIGS. 4 to 6 described below, The method shown in the figure may also be used.

(2) As shown in FIG. 4, semicircular-arc-shaped recesses 42 of desired diameter and depth are formed in the glass support substrate 41 at the positions where the connected grains are arranged by a honing method, etc., and these recesses 42 are filled with, for example, A
The connected grains 43 made of R are dropped and temporarily fixed.

② As shown in FIG.
111144 is decomposed using a laser beam to form holes 45 at the positions where the connected grains are arranged, and connected grains 43 made of A2, for example, are dropped into these holes 45 and temporarily fixed. Note that a matching mark (not shown) is attached to the handle 44.

(2) As shown in FIG. 6, a magnetic thin film 46 of a desired thickness made of ferrite or the like is formed on the back surface of the glass support substrate 41;
Connecting branches 43', each of which has an Au plating film 48 applied to the surface of the N1 sphere 47, are placed on the surface of the support substrate 41 at desired arrangement positions. In this case, the connecting branch 43' is temporarily fixed to the surface of the support base Ifi41 by the magnetic force of the three magnetic films 46 coated on the surface of the support substrate 411.

In the above embodiment, the fixing of the connecting branch to the pad of a semiconductor substrate, etc. is achieved by using a heating gate structure of a holding jig placed on the substrate side, or an ultrasonic wave t.
Although this was carried out using one mechanism, it may also be carried out using a heating mechanism or an ultrasonic mechanism added to the mounting table for the support substrate.

[Effects of the Invention] As detailed above, according to the present invention, a plurality of conductive connecting branches can be efficiently fixed to pads of a semiconductor substrate, and a highly integrated and highly reliable tertiary device that can be multi-functionalized. It has remarkable effects, such as being able to be effectively applied to the manufacture of semiconductor devices with original structures.

[Brief explanation of the drawing]

FIGS. 1(a) to (Q) are cross-sectional views showing the manufacturing process of a three-dimensional structure semiconductor device in an embodiment of the present invention, and FIG.
a) to (C) are cross-sectional views illustrating the process of fixing connecting branches made of ALJ to pads and I dos of connecting holes of semiconductor substrates for lamination;
3(a) to 6(C) are cross-sectional views showing the process of fixing connecting branches made of Au to the pads of a non-defective chip, and FIGS. 4 to 6
The figures are cross-sectional views showing other embodiments of the present invention, and FIG. 7 is a cross-sectional view showing a conventional process of fixing connecting branches to pads of a semiconductor substrate. 11... Silicon wafer, 12.13.35... Pad, 16... Semiconductor substrate for lamination, 17... Connecting hole, 22.31.41... Glass support substrate, 23.32
...Polyimide film, 24.33.38.43.43'
. . . Connecting branch, 34 . . . Good chip, 42 . . . Recess, 44 . Applicant's agent Patent attorney Takehiko Suzue -9.4-

Claims (1)

[Claims] a step of forming conductive connected grains; a step of arranging and fixing a plurality of said connected grains at desired positions on a support substrate; and supporting the semiconductor substrate on which at least a semiconductor element is formed and a pad is formed on the surface. It is characterized by comprising the steps of arranging the connected grains on the substrate so that they match the pads of the semiconductor substrate, and fixing the connected grains to the pads of the semiconductor substrate and moving them to the pad side. A method for manufacturing a semiconductor device.