JPH0577339B2 - - Google Patents

Info

Publication number
JPH0577339B2
JPH0577339B2 JP21662287A JP21662287A JPH0577339B2 JP H0577339 B2 JPH0577339 B2 JP H0577339B2 JP 21662287 A JP21662287 A JP 21662287A JP 21662287 A JP21662287 A JP 21662287A JP H0577339 B2 JPH0577339 B2 JP H0577339B2
Authority
JP
Japan
Prior art keywords
semiconductor substrate
lamination
semiconductor
cylindrical body
grains
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP21662287A
Other languages
Japanese (ja)
Other versions
JPS6459845A (en
Inventor
Katsuya Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP21662287A priority Critical patent/JPS6459845A/en
Publication of JPS6459845A publication Critical patent/JPS6459845A/en
Publication of JPH0577339B2 publication Critical patent/JPH0577339B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

PURPOSE:To prevent a crack from being caused while a thermal stress is absorbed by using a coupling particle and to enhance heat-dissipating performance by forming a gap between substrates by a method wherein, when the semiconductor substrates for lamination use are laminated three-dimensionally, the semiconductor substrates are laminated mutually by using the coupling particle. CONSTITUTION:A conductive coupling particle composed of a metallic substance which has been filled into a hard cylindrical body and a hard cylindrical body, whose inside diameters differ from each other, in such a way that the particle protrudes partly from an end part at the side of a smaller inside diameter is fixed to a pad 3 of a coupling hole 7 in a semiconductor substrate 6 for lamination use. As this fixing method, the semiconductor substrate 6 for lamination use is set on a retention stage 35 in such a way that an opening of the coupling hole 7 faces upward; after that, a gun barrel 32 is aligned with the coupling hole 7 in the semiconductor substrate 6. A temperature of the retention stage 35 is increased to 300 deg.C by using a built-in heater 34; after that, the outside of the gun barrel 32 is maintained at about 350 deg.C by using a heater 31; a conductive coupling particle 19 is inserted into the gun barrel 32 and is discharged with accelerated velocity while the coupling particle 19 is being heated by compressed nitrogen 36. The semiconductor substrate 6 for lamination use where the conductive coupling particle 19 has been fixed to an exposed part of the pad 3 corresponding to the coupling hole 7 via a protruding part 17 is thereby obtained.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置に関し、半導体素子等が
形成された半導体基板を複数枚積層した三次元構
造を有する半導体装置に係わる。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and relates to a semiconductor device having a three-dimensional structure in which a plurality of semiconductor substrates on which semiconductor elements and the like are formed are laminated. .

(従来の技術) 近年、半導体装置の高集積化、多機能化を目的
とした三次元SOI(Silicon on Insulation)デバ
イスの開発が盛んに行なわれている。これは、半
導体基板表面の非晶質絶縁膜上にシリコン単結晶
を形成し、該単結晶層を用いて半導体素子を作
り、三次元的に半導体素子を積層していく技術で
ある。かかる技術は、例えば日経エレクトロニク
ス1985年10月17日号 p229〜253の“高集積、多
機能デバイスとして姿が見えてきた三次元LSI”
に記載されている。
(Prior Art) In recent years, three-dimensional SOI (Silicon on Insulation) devices have been actively developed for the purpose of increasing the integration and multifunctionality of semiconductor devices. This is a technique in which a silicon single crystal is formed on an amorphous insulating film on the surface of a semiconductor substrate, a semiconductor element is manufactured using the single crystal layer, and the semiconductor elements are stacked three-dimensionally. This technology is described, for example, in Nikkei Electronics October 17, 1985 issue, p. 229-253, “Three-dimensional LSI emerging as a highly integrated, multifunctional device.”
It is described in.

しかしながら、SOI技術は開発の途についたば
かりであり、実用化の上で数々の欠点を有する。
本質的な欠点としては、異質なものを多重に積
層し、高温プロセスを経て単結晶化が進められる
ため、ストレスが非常に大きくなり、クラツク等
が発生し易いこと、層間が密着構造を有してい
るため、放熱性が低く、熱がこもり易いことが挙
げられるまた、シリコン以外の半導体材料を積層
していくことは現在の技術では不可能である。
However, SOI technology is still in the early stages of development and has a number of drawbacks in terms of practical application.
The essential disadvantages are that different materials are laminated in multiple layers and single crystallization is progressed through a high-temperature process, so the stress is extremely large and cracks are likely to occur, and the layers have a close contact structure. Therefore, heat dissipation is low and heat is easily trapped.Furthermore, it is impossible with current technology to stack semiconductor materials other than silicon.

(発明が解決しようとする問題点) 本発明は、上述した従来の三次元化によるクラ
ツク発生及び放熱性の悪化を解決し、高信頼性、
高集積度で多機能化を達成した半導体装置を提供
しようとするものである。
(Problems to be Solved by the Invention) The present invention solves the above-mentioned problems of crack generation and deterioration of heat dissipation caused by three-dimensionalization, and achieves high reliability and
The present invention aims to provide a semiconductor device that achieves high integration and multifunctionality.

[発明の構成] (問題点を解決するための手段) 本発明は、半導体素子が少なくとも形成され、
かつ表面の所定部分に複数のパツドが形成された
半導体基板と、 表面に形成されたパツドに対応する箇所に連結
孔が前記パツドの裏面の少なくとも一部を露出さ
せるように厚さ方向に開口されると共に半導体素
子が形成された少なくとも1つの積層用半導体基
板とを具備し、 一端付近の内径が他端付近の内径より小さい形
状を有する硬質の円筒体は、その内部に金属体か
らなる導電性連結粒が前記円筒体の一端から突出
するように充填され、かつ前記円筒体は前記積層
用半導体基板の連結孔から露出した前記パツドの
裏面に前記連結粒の突出部を介して固着され、 前記積層用半導体基板と前記半導体基板とは、
前記円筒体の他端に露出した前記連結粒を前記半
導体基板の前記パツド側に配置した別の導電性連
結粒に固着することにより積層されることを特徴
とするものである。
[Structure of the Invention] (Means for Solving the Problems) The present invention provides a method in which a semiconductor element is formed at least,
and a semiconductor substrate having a plurality of pads formed on a predetermined portion of the surface, and a connecting hole opened in the thickness direction at a location corresponding to the pad formed on the surface so as to expose at least a part of the back surface of the pad. and at least one laminated semiconductor substrate on which a semiconductor element is formed, and the hard cylindrical body has an inner diameter near one end smaller than an inner diameter near the other end. The cylindrical body is filled with connecting grains so as to protrude from one end of the cylindrical body, and the cylindrical body is fixed to the back surface of the pad exposed from the connecting hole of the laminated semiconductor substrate via the protrusion of the connecting grains, The semiconductor substrate for lamination and the semiconductor substrate are:
It is characterized in that the connecting grains exposed at the other end of the cylindrical body are laminated by fixing them to other conductive connecting grains arranged on the pad side of the semiconductor substrate.

(作用) 本発明は、半導体素子等が形成された半導体基
板と同素子が形成された積層用半導体基板の間、
更に積層用半導体基板間を積層用半導体基板の連
結孔に対応するパツドの露出部及び相手側のパツ
ドに導電性連結粒を介して固着、接続することに
よつて、半導体基板上に積層用半導体基板を三次
元的に積層できる。
(Function) The present invention provides a structure in which between a semiconductor substrate on which a semiconductor element, etc. is formed, and a laminated semiconductor substrate on which the same element is formed,
Further, by fixing and connecting the semiconductor substrates for stacking to the exposed portion of the pad corresponding to the connecting hole of the semiconductor substrate for stacking and the pad on the other side via conductive connecting grains, the semiconductor substrates for stacking are bonded and connected to each other via conductive connecting grains. Substrates can be stacked three-dimensionally.

また、半導体基板相互の積層は連結粒によりな
されているため、熱ストレスを該連結粒で吸収で
き、従来のSOI構造のようなクラツク発生を防止
できる。
Further, since the semiconductor substrates are laminated with each other using connected grains, thermal stress can be absorbed by the connected grains, and the occurrence of cracks as in the conventional SOI structure can be prevented.

更に、半導体基板相互の積層は連結粒によりな
され、それら基板間に所望の〓間を形成できるた
め、各基板間に熱がこもることなく、放熱性が改
善される。特に、前記基板間の〓間に冷媒を流通
させることが可能であるため、大幅な放熱効果を
発揮できる。
Further, since the semiconductor substrates are laminated with each other by connecting grains, and a desired distance can be formed between the substrates, heat is not trapped between the substrates, and heat dissipation is improved. In particular, since it is possible to circulate the coolant between the substrates, a significant heat dissipation effect can be exhibited.

更にまた、積層用半導体基板の連結孔内のパツ
ドに固着される導電性連結粒は異なる内径を有す
る硬質の円筒体と、該円筒体内に小さい内径側の
端部から一部突出するように充填された金属体か
ら構成されているため、該金属体の突出部を介し
て該パツドに容易に固着できる。しかも、該連結
粒をパツドに固着する際に連結粒全体に機械的な
力が与えられても、硬質の円筒体によりその軸と
直交する方向への変形を阻止できるため、該連結
粒の変形に伴つて連結孔の内側面に露出する半導
体基板と接触して短絡するのを防止できる。
Furthermore, the conductive connecting grains fixed to the pads in the connecting holes of the semiconductor substrate for lamination are filled with hard cylindrical bodies having different inner diameters, and into the cylindrical bodies so as to partially protrude from the end on the smaller inner diameter side. Since the pad is made of a metal body, it can be easily fixed to the pad via the protrusion of the metal body. Moreover, even if a mechanical force is applied to the entire connected grain when fixing the connected grain to the pad, the hard cylindrical body can prevent deformation in the direction perpendicular to the axis, so the deformation of the connected grain can be prevented. Accordingly, it is possible to prevent short-circuiting due to contact with the semiconductor substrate exposed on the inner surface of the connecting hole.

(発明の実施例) 以下、本発明の実施例を製造方法を併記して詳
細に説明する。
(Examples of the Invention) Examples of the invention will be described in detail below along with manufacturing methods.

() まず、二次元のLSI製造法により厚さ
450μmのシリコンウエハ1に半導体素子、素子
間の配線(いずれも図示せず)及びAl膜から
なる50μm×50μmのパツド2,3を形成した。
なお、これらパツドのうち、後充する連結孔に
対応するパツド3の一部は、層間絶縁膜に形成
された開孔部内に埋込まれ、かつ該開孔部底部
の基板表面には薄い酸化膜が形成されている。
この酸化膜は、ダイソートテストの障害となる
パツドの基板表面への電気的な接続を防止する
ために用いられる。但し、前記薄い酸化膜の代
わりに開孔部の底部を含む周辺の基板表面に
pn接合を作るための不純物拡散層を形成して
もよい。つづいて、前記パツド3に対応するシ
リコンウエハ1の裏面に等方性エツチングと異
方性エツチングの組合わせにより開口30μm×
30μm、深さ50μmのワイカツプ状の孔4を開孔
した(第1図a図示)。なお、エツチングは、
いずれもフツ素系ガスのプラズマを用いて行な
つた。
() First, the thickness is
On a 450 μm silicon wafer 1, semiconductor elements, interconnections between the elements (none of which are shown), and 50 μm×50 μm pads 2 and 3 made of an Al film were formed.
Of these pads, a part of the pad 3 corresponding to the connecting hole to be filled later is embedded in the opening formed in the interlayer insulating film, and a thin oxide layer is formed on the substrate surface at the bottom of the opening. A film is formed.
This oxide film is used to prevent electrical connection of the pad to the substrate surface, which would be an obstacle in the die sort test. However, instead of the thin oxide film, a thin oxide film is formed on the surrounding substrate surface including the bottom of the opening.
An impurity diffusion layer may be formed to create a pn junction. Subsequently, the back surface of the silicon wafer 1 corresponding to the pad 3 is etched by a combination of isotropic etching and anisotropic etching to form an opening of 30 μm×.
A round hole 4 having a diameter of 30 μm and a depth of 50 μm was drilled (as shown in FIG. 1a). In addition, etching is
Both experiments were carried out using fluorine-based gas plasma.

() 次いで、前記シリコンウエハのダイソート
テストを行なつた後、ダイシングを施して個々
のチツプを作り、選別を行なつて良品チツプ5
を得た(第1図b図示)。つづいて、良品チツ
プ5の裏面全体を異方性エツチングを行なつて
厚さ45μmの薄板状の積層用半導体基板6を作
製した(第1図c図示)。この異方性エツチン
グの工程において、裏面に開口されたワインカ
ツプ状の孔4は略その形状が保持されながらエ
ツチングされるため、テーパ状の連結孔7が形
成された。また、前記エツチングに際して前述
した開孔部底部の薄い酸化膜除去を行なつて、
該連結孔7の底部に開孔部に対応してパツド3
の一部を露出させた。
() Next, after performing a die sort test on the silicon wafer, dicing is performed to produce individual chips, which are then sorted to produce 5 good chips.
was obtained (as shown in FIG. 1b). Subsequently, the entire back surface of the non-defective chip 5 was subjected to anisotropic etching to produce a thin plate-shaped semiconductor substrate 6 for lamination having a thickness of 45 μm (as shown in FIG. 1c). In this anisotropic etching process, the wine cup-shaped hole 4 opened on the back surface is etched while substantially maintaining its shape, so that a tapered connecting hole 7 is formed. Also, during the etching, the thin oxide film at the bottom of the opening was removed,
A pad 3 is provided at the bottom of the connecting hole 7 corresponding to the opening.
exposed part of.

() 次いで、前記積層用半導体基板6の連結孔
7のパツド3に異なる内径を有する硬質の円筒
体及び該円筒体内に小さい内径側の端部から一
部突出するように充填された金属体からなる導
電性連結粒を固着するが、この導電性連結粒の
製法を第2図a〜dを参照して説明すると共
に、該導電性連結粒の前記連結孔7内のパツド
に固着する方法を第3図a,bに示す外部にヒ
ータ31が配設された内径40μmの銃筒32か
らなる連結粒固着機33と、半導体基板がセツ
トされるヒータ34を内蔵した保持台35とか
ら構成される装置を参照して説明する。
() Next, the pad 3 of the connecting hole 7 of the semiconductor substrate 6 for lamination is filled with a hard cylindrical body having different inner diameters and a metal body filled in the cylindrical body so as to partially protrude from the end on the smaller inner diameter side. The manufacturing method of the conductive connected grains will be explained with reference to FIGS. As shown in FIGS. 3a and 3b, it consists of a connected grain fixing machine 33 consisting of a gun barrel 32 with an inner diameter of 40 μm and a heater 31 disposed on the outside, and a holding table 35 with a built-in heater 34 on which a semiconductor substrate is set. This will be explained with reference to the device.

まず、支持台11上に厚さ約20μmのフオト
レジスト膜12を塗布した後、外径60μm、内
径20μm、長さ50μmのアルミナを主成分とする
セラミツクス製円筒体13を前記支持台11上
に該円筒体13の下端が該レジスト膜12によ
り覆われるように直立して固定した(第2図a
図示)。つづいて、フツ酸と硝酸を主成分とし
た混酸溶液中に浸漬して円筒体13を略3μmエ
ツチングした。エツチング後、レジスト膜を除
去することにより第2図bに示す異径、特に内
径の異なる(大内径部;26μm、小内径部;
20μm)のセラミツク製円筒体14が作製され
た。ひきつづき、第2図cに示すように支持台
15上に載置された厚さ50μmの金箔16に前
記円筒体14の大内径部側を先端として圧搾空
気を用いて打込むことによつて、小内径部側の
後端から金(Au)が約10μm突出した。この
後、金が充填された円筒体14を支持基体15
から取出すことによつて、第2図dに示すよう
に異なる内径を有する硬質の円筒体14と該円
筒体14内に充填された小内径部側の端部から
突出した突出部17を有する金体(Au体)1
8からなる導電性連結粒19を製造した。
First, a photoresist film 12 with a thickness of about 20 μm is applied on the support base 11, and then a ceramic cylinder 13 mainly made of alumina and having an outer diameter of 60 μm, an inner diameter of 20 μm, and a length of 50 μm is placed on the support base 11. The cylindrical body 13 was fixed upright so that the lower end was covered with the resist film 12 (see Fig. 2a).
(Illustrated). Subsequently, the cylindrical body 13 was etched by approximately 3 μm by immersing it in a mixed acid solution containing hydrofluoric acid and nitric acid as main components. After etching, the resist film is removed to create different diameters as shown in FIG.
A ceramic cylindrical body 14 with a diameter of 20 μm was fabricated. Subsequently, as shown in FIG. 2c, by using compressed air, the gold foil 16 with a thickness of 50 μm placed on the support stand 15 is driven with the large inner diameter side of the cylindrical body 14 as the tip. Gold (Au) protruded approximately 10 μm from the rear end of the small inner diameter side. After this, the cylindrical body 14 filled with gold is placed on the supporting base 15.
As shown in FIG. 2d, a hard cylindrical body 14 having different inner diameters and a metal having a protrusion 17 protruding from the end on the small inner diameter side filled in the cylindrical body 14 are obtained. Body (Au body) 1
Conductive connected grains 19 consisting of 8 were manufactured.

次いで、第3図aに示すように保持台35上
に前記積層用半導体基板6をその連結孔7の開
口部が上になるようにセツトした後、銃筒32
を前記半導体基板6の連結孔7に位置合せし
た。つづいて、内蔵されたヒータ34によつて
保持台35を300℃に昇温した後、銃筒32の
外部をヒータ31によつて約350℃に保持し、
該銃筒32に前述した方法により製造した導電
性連結粒19を挿入し、圧縮窒素36により該
連結粒19を加熱しながら加速度をもたせて放
射することによつて、第3図bに示すように連
結粒19の円筒体14の小内径部部側から突出
したAu製突出部17を連結孔7底部のパツド
3の露出部上に熱圧接して固着した。なお、第
3図bの中の8は基板6とパツド3とを電気的
に絶縁するための層間絶縁膜、9は該絶縁膜8
に形成され、パツド3の一部を前記連結孔7底
部に露出させるための開孔部である。こうした
工程により第1図dに示す連結孔7に対応する
パツド3の露出部に側面が異形のセラミツク製
円筒体14及び該円筒体14に充填されたAu
体18からなる導電性連結粒19が突出部17
を介して固着された積層用半導体基板6を得
た。
Next, as shown in FIG. 3a, the semiconductor substrate 6 for lamination is set on the holding table 35 so that the opening of the connecting hole 7 is facing upward, and then the gun barrel 32 is set.
was aligned with the connecting hole 7 of the semiconductor substrate 6. Next, the temperature of the holding base 35 is raised to 300°C by the built-in heater 34, and then the outside of the gun barrel 32 is maintained at about 350°C by the heater 31.
The conductive connecting grains 19 manufactured by the method described above are inserted into the gun barrel 32, and the compressed nitrogen 36 heats the connecting grains 19 while emitting radiation with acceleration, as shown in FIG. 3b. Then, the Au protrusion 17 protruding from the small inner diameter side of the cylindrical body 14 of the connecting grain 19 was fixed by hot pressure welding onto the exposed portion of the pad 3 at the bottom of the connecting hole 7. Note that 8 in FIG. 3b is an interlayer insulating film for electrically insulating the substrate 6 and the pad 3, and 9 is the insulating film 8.
This is an opening for exposing a part of the pad 3 to the bottom of the connecting hole 7. Through these steps, a ceramic cylindrical body 14 with an irregular side surface is formed in the exposed part of the pad 3 corresponding to the connecting hole 7 shown in FIG.
The conductive connected grains 19 consisting of the body 18 are connected to the protrusion 17
A semiconductor substrate 6 for lamination was obtained which was fixed through the wafer.

() 次いで、二次元のLSI製造法により厚さ
450μmのシリコンウエハに半導体素子、素子間
の配線及びAl膜からなる50μm×50μmのパツ
ドを形成した。つづい、ダイソートテストの
後、前記シリコンウエハをダイシングし、良品
チツプ21を選別し、この良品チツプ21表面
のパツド22上に前述の連結粒固着機を用いて
40μm径の球状をなすAu粒23を固着した(第
1図e図示)。
() Next, the thickness was determined using a two-dimensional LSI manufacturing method.
A 50 μm x 50 μm pad consisting of a semiconductor element, wiring between elements, and an Al film was formed on a 450 μm silicon wafer. Subsequently, after the die sort test, the silicon wafer is diced, non-defective chips 21 are selected, and the above-mentioned connected grain fixing machine is used to place the chips on the pads 22 on the surface of the non-defective chips 21.
Au particles 23 having a spherical shape with a diameter of 40 μm were fixed (as shown in FIG. 1e).

() 次いで、前記()の工程で作製した良品チ
ツプ21上に前記()〜()の工程により作製
した積層用半導体基板6を該チツプ21のパツ
ド22上のAu粒23と該半導体基板6の連結
孔7内の導電性連結粒19の大内径部側端部と
が合致するように重ねた後、300℃に加熱しな
がら積層用半導体基板6をチツプ21に対して
押し付けることによりAu粒23と連結粒19
のAu体18を互いに固着した(第1図f図
示)。つづいて、積層された半導体基板6表面
の所定のパツド2,3上に前述した連結固着機
を用いて球状をなすAu粒24を熱圧接して固
着した(第1図g図示)。
() Next, the semiconductor substrate 6 for lamination produced in the steps () to () above is placed on the good chip 21 produced in the step () above, and the Au grains 23 on the pads 22 of the chip 21 and the semiconductor substrate 6 are placed on top of the non-defective chip 21 produced in the step () above. After stacking the conductive connecting grains 19 in the connecting hole 7 so that the ends of the large inner diameter side coincide with each other, the semiconductor substrate 6 for lamination is pressed against the chip 21 while heating to 300°C, thereby removing the Au grains. 23 and connected grain 19
The Au bodies 18 were fixed to each other (as shown in FIG. 1f). Subsequently, spherical Au particles 24 were bonded and fixed by thermocompression onto predetermined pads 2 and 3 on the surface of the stacked semiconductor substrates 6 using the above-mentioned connecting fixing machine (as shown in FIG. 1g).

() 次いで、前記()〜()と同様な工程により
複数枚の薄板状の積層用半導体基板を作製し、
これら半導体基板を前記第1図gにより積層し
た半導体基板6の上に前記()と同様な工程に
より順次積層し、多層積み重ねた半導体装置
(図示せず)を製造した。
() Next, a plurality of thin plate-shaped semiconductor substrates for lamination are produced by the same steps as in () to () above,
These semiconductor substrates were sequentially stacked on top of the semiconductor substrate 6 stacked as shown in FIG.

しかして、本発明の半導体装置は半導体素子等
が形成された良品チツプ21と同素子が形成され
た積層用半導体基板6の間、更に各積層用半導体
基板6間を積層用半導体基板6の連結孔7に対応
するパツド3の露出部及び相手側のパツド22に
異なる内径を有する硬質円筒体14と該円筒体1
4内に充填され小内径部側の端部から突出した突
出部17を有するAu体18からなる導電性連結
粒19及びAu粒23,24を介して固着、積層
するため、高集積度で多機能の三次元構造を有す
る半導体装置を得ることができる。
Therefore, in the semiconductor device of the present invention, the semiconductor substrate 6 for lamination is connected between the non-defective chip 21 on which a semiconductor element or the like is formed and the semiconductor substrate 6 for lamination on which the same element is formed, and further between the semiconductor substrates 6 for lamination 6. A hard cylindrical body 14 and the cylindrical body 1 having different inner diameters in the exposed part of the pad 3 corresponding to the hole 7 and the mating pad 22.
The conductive connecting grains 19 made of the Au body 18 having the protruding part 17 that is filled in the inner diameter part 4 and protruding from the end on the small inner diameter side are fixed and laminated via the Au grains 23 and 24. A semiconductor device having a three-dimensional functional structure can be obtained.

また、良品チツプ21と積層用半導体基板6及
び各積層用半導体基板6間の積層は、導電性連結
粒19及びAu粒23,24によりなされている
ため、熱ストレスを該連結粒19のAu体18、
Au粒23,24で吸収できるため、従来のSOI
構造のようなクラツク発生を防止できる。しか
も、同様な理由により良品チツプ21と積層用半
導体基板6の間、各半導体基板6の間に所望の〓
間を形成できるため、各基板間に熱がこもること
なく、放熱性が改善される。従つて、高信頼性の
三次元構造を有する半導体装置を得ることができ
る。
Furthermore, since the non-defective chip 21, the semiconductor substrate for lamination 6, and the lamination between the semiconductor substrates for lamination 6 and each of the semiconductor substrates for lamination 6 are made of the conductive connecting grains 19 and the Au grains 23, 24, the Au body of the connecting grains 19 is 18,
Because it can be absorbed by Au grains 23 and 24, it
It is possible to prevent cracks from occurring in structures. Moreover, for the same reason, a desired distance between the non-defective chip 21 and the semiconductor substrate 6 for lamination, and between each semiconductor substrate 6 is maintained.
Since gaps can be formed between the substrates, heat is not trapped between the substrates, and heat dissipation is improved. Therefore, a semiconductor device having a highly reliable three-dimensional structure can be obtained.

更に、積層用半導体基板6の連結孔内7のパツ
ド7に固着される導電性連結粒19は異なる内径
を有する硬質の円筒体14と該円筒体14内に充
填され小内径部側の端部から突出した突出部17
を有するAu体18からなる構成されているため、
該Au体18の突出部17を介して該パツド3に
簡単かつ確実に固着できる。しかも、該導電性連
結粒19を連結孔7内のパツド3に固着に際して
連結粒19全体に機械的な力が与えられても、硬
質の円筒体14によりその軸と直交する方向への
変形を阻止できる。その結果、連結粒19を構成
するAu体18と連結孔7の内側面に露出する積
層用半導体基板6との接触に伴う短絡を防止でき
る。特に、実施例のようにセラミツクで円筒体1
4を形成すれば、積層用半導体基板6の連結孔7
内のパツド3に導電性連結粒19の固着する際、
該連結粒19の側面が連結孔7内面に露出する積
層用半導体基板6に接触して該円筒体14により
連結粒19と積層用半導体基板6が短絡するのを
阻止できるため、該連結粒19の固着時の合せ精
度をラフにでき、半導体装置の生産性を向上でき
る。同様な理由により連結孔にテーパを付けなく
とも前記短絡を防止できるため、連結孔の微細
化、半導体装置の製造の簡略化を達成できる。
Further, the conductive connecting grains 19 fixed to the pads 7 in the connecting holes 7 of the semiconductor substrate 6 for lamination are connected to a hard cylinder 14 having different inner diameters, and the ends of the cylinders 14 are filled in the small inner diameter side. A protrusion 17 protruding from the
Since it is composed of an Au body 18 having
The Au body 18 can be easily and reliably fixed to the pad 3 via the protrusion 17. Moreover, even if mechanical force is applied to the entirety of the conductive connecting grains 19 when fixing them to the pads 3 in the connecting holes 7, the hard cylindrical body 14 prevents deformation in the direction perpendicular to the axis thereof. It can be prevented. As a result, it is possible to prevent short circuits caused by contact between the Au bodies 18 constituting the connection grains 19 and the stacking semiconductor substrate 6 exposed on the inner surface of the connection hole 7. In particular, as in the example, the cylindrical body 1 is made of ceramic.
4, the connection hole 7 of the semiconductor substrate 6 for lamination is formed.
When the conductive connecting grains 19 are fixed to the inner pad 3,
The connecting grains 19 can prevent the connecting grains 19 from coming into contact with the laminating semiconductor substrate 6 exposed on the inner surface of the connecting hole 7 and causing a short circuit between the connecting grains 19 and the laminating semiconductor substrate 6 due to the cylindrical body 14. The alignment accuracy during fixing can be made rough, and the productivity of semiconductor devices can be improved. For the same reason, the short circuit can be prevented without tapering the connecting hole, so that miniaturization of the connecting hole and simplification of manufacturing of the semiconductor device can be achieved.

なお、上記実施例では導電性連結粒を構成する
硬質の円筒体としてアルミナを主成分とするセラ
ミツクから形成したが、これに限定されない。例
えば、ムライト、窒化ケイ素などのアルミナ以外
のセラミツク、ガラス、ポリイミド等の耐熱性有
機合成樹脂、ステンレスなどの硬質金属、又は金
属とセラミツクを張合わせた材料で円筒体を形成
してもよい。
In the above embodiment, the hard cylindrical body constituting the conductive connected grains is made of ceramic containing alumina as a main component, but the present invention is not limited thereto. For example, the cylindrical body may be formed of ceramics other than alumina such as mullite and silicon nitride, glass, heat-resistant organic synthetic resins such as polyimide, hard metals such as stainless steel, or a material made by bonding metal and ceramic.

上記実施例では、金属体として金(Au)を用
いたが、例えば前述した第2図cの工程で金箔の
代わりにAl箔を用いてもよい。更にAg−Pt、Au
−Pd、Mo、Wの導体粉末とバインダからなる導
体ペーストを支持基体上に塗布し、同図bで作製
した異径の円筒体を該導電ペース層に打込んだ
後、焼成して同図dに示す導電性連結粒を製造し
てもよい。
In the above embodiment, gold (Au) was used as the metal body, but for example, Al foil may be used instead of gold foil in the step shown in FIG. 2c described above. Furthermore, Ag−Pt, Au
- A conductive paste consisting of conductor powder of Pd, Mo, and W and a binder is applied onto a supporting substrate, and the cylindrical bodies of different diameters prepared in Figure b are implanted into the conductive paste layer and fired. You may manufacture the electroconductive connected grain shown in d.

上記実施例では、側面を絶縁物で覆つた導電性
連結粒を連結孔内のパツドに固着した例を説明し
たが、該連結孔以外の箇所に用いる連結粒(例え
ば実施例のAu粒23,24)を異なる内径を有
する硬質の円筒体と、該円筒体内に小さい内径側
の端部から一部突出するように充填された金属体
からなる導電性連結粒を用いてもよい。
In the above example, an example was explained in which conductive connecting grains whose side surfaces were covered with an insulating material were fixed to pads in the connecting holes. 24) may be used as electrically conductive connected grains made of hard cylinders having different inner diameters and metal bodies filled in the cylinders so as to partially protrude from the end on the smaller inner diameter side.

上記実施例では、シリコンからなる積層用半導
体基板のみを複数枚用い、これら積層用半導体基
板をチツプ上に積層した構造について説明した
が、これに限定されない。例えば、積層用半導体
基板の間に配線基板を連結粒を介して挿入し、該
配線基板を境にして下側の積層用半導体基板等と
上層側の積層用半導体基板との間の電流経路を変
更するようにしてもよい。また、第4図に示すよ
うにチツプ51をシリコンで形成し、このシリコ
ンチツプ51上にシリコン半導体基板52とガリ
ウム砒素半導体基板53とを積層し、更にこれら
シリコン半導体基板52及びガリウム砒素半導体
基板53にシリコン半導体基板54を積層した三
次元構造の半導体装置としてもよい。こうした第
4図図示の構成とすれば、従来のSOI構造に比べ
てより一層多機能化が図られた三次元構造の半導
体装置を簡単に実現できる。
In the above embodiment, a structure in which only a plurality of laminated semiconductor substrates made of silicon are used and these laminated semiconductor substrates are laminated on a chip has been described, but the present invention is not limited to this. For example, a wiring board is inserted between the semiconductor substrates for lamination via a connecting grain, and a current path is established between the semiconductor substrate for lamination on the lower side and the semiconductor substrate for lamination on the upper side with the wiring substrate as a boundary. It may be changed. Further, as shown in FIG. 4, a chip 51 is formed of silicon, a silicon semiconductor substrate 52 and a gallium arsenide semiconductor substrate 53 are laminated on this silicon chip 51, and further these silicon semiconductor substrate 52 and gallium arsenide semiconductor substrate 53 are laminated. The semiconductor device may have a three-dimensional structure in which a silicon semiconductor substrate 54 is stacked on top. With the configuration shown in FIG. 4, it is possible to easily realize a semiconductor device with a three-dimensional structure that has more functions than the conventional SOI structure.

[発明の効果] 以上詳述した如く、本発明によれば熱ストレス
によるクラツク発生を防止し、かつ放熱性に優
れ、更に従来のSOI構造に比べて多機能化が可能
な高集積度で高信頼性の三次元構造の半導体装置
を提供できる。
[Effects of the Invention] As detailed above, the present invention prevents the occurrence of cracks due to thermal stress, has excellent heat dissipation, and has a highly integrated and highly integrated structure that can be multi-functional compared to conventional SOI structures. A semiconductor device with a reliable three-dimensional structure can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜gは本発明の三次元構造の半導体装
置を得るための製造工程を示す断面図、第2図a
〜dは本実施例に用いる導電性連結粒の製造工程
を示す断面図、第3図a,bは、積層用半導体基
板の連結孔のパツドに第2図a〜dにより製造し
た連結粒を固着する工程を示す断面図、第4図は
本発明の他の実施例を示す三次元構造の半導体装
置を示す断面図である。 1……シリコンウエハ、2,3,22……パツ
ド、6……積層用半導体基板、7……連結孔、8
……層間絶縁膜、9……開孔部、12……支持
台、13,32……銃筒、14……セラミツク製
の円筒体、17……突出部、18……金体(Au
体)、19……導電性連結粒、21……良品チツ
プ、23,24……Au粒、33……連結粒固着
機、35……保持台、51……シリコンチツプ、
52,54……シリコン半導体基板、53……ガ
リウム砒素半導体基板。
Figures 1a to 1g are cross-sectional views showing the manufacturing process for obtaining a three-dimensionally structured semiconductor device of the present invention, and Figure 2a
- d are cross-sectional views showing the manufacturing process of the conductive connected grains used in this example, and Figures 3 a and b show the connected grains manufactured according to Figures 2 a to d in the pads of the connecting holes of the semiconductor substrate for lamination. FIG. 4 is a cross-sectional view showing the fixing process, and FIG. 4 is a cross-sectional view showing a three-dimensional semiconductor device according to another embodiment of the present invention. 1... Silicon wafer, 2, 3, 22... Pad, 6... Semiconductor substrate for lamination, 7... Connecting hole, 8
... Interlayer insulating film, 9 ... Opening part, 12 ... Support stand, 13, 32 ... Gun barrel, 14 ... Ceramic cylindrical body, 17 ... Protrusion part, 18 ... Gold body (Au
body), 19... Conductive connected grains, 21... Good chips, 23, 24... Au grains, 33 ... Connected grain fixing machine, 35... Holding stand, 51... Silicon chips,
52, 54...Silicon semiconductor substrate, 53...Gallium arsenide semiconductor substrate.

Claims (1)

【特許請求の範囲】 1 半導体素子が少なくとも形成され、かつ表面
の所定部分に複数のパツドが形成された半導体基
板と、 表面に形成されたパツドに対応する箇所に連結
孔が前記パツドの裏面の少なくとも一部を露出さ
せるように厚さ方向に開口されると共に半導体素
子が形成された少なくとも1つの積層用半導体基
板とを具備し、 一端付近の内径が他端付近の内径より小さい形
状を有する硬質の円筒体は、その内部に金属体か
らなる導電性連結粒が前記円筒体の一端から突出
するように充填され、かつ前記円筒体は前記積層
用半導体基板の連結孔から露出した前記パツドの
裏面に前記連結粒の突出部を介して固着され、 前記積層用半導体基板と前記半導体基板とは、
前記円筒体の他端に露出した前記連結粒を前記半
導体基板の前記パツド側に配置した別の導電性連
結粒に固着することにより積層されることを特徴
とする半導体装置。 2 前記積層用半導体基板の前記連結孔内のパツ
ドに固着される導電性連結粒以外に用いられる導
電性連結粒は、一端付近の内径が他端付近の内径
より小さい形状を有する硬質の円筒体の内部に前
記円筒体の一端から突出するように充填された金
属体からなることを特徴とする特許請求の範囲第
1項記載の半導体装置。 3 複数枚の前記積層用半導体基板を用意し、前
記各積層用半導体基板は前記連結孔に対応する領
域以外にもパツドを有し、一層目の前記積層用半
導体基板の連結孔以外のパツドと二層目の前記積
層用半導体基板の連結孔に対応するパツド裏面の
露出部とを導電性連結粒と一端付近の内径が他端
付近の内径より小さい形状を有する硬質の円筒体
の内部にその一端から突出するように充填された
金属体からなる導電性連結粒とを用いて相互に固
着して積層し、同様に三層目以降の積層用半導体
基板を順次前記導電性連結粒と前記円筒体の内部
に充填された導電性連結粒とを用いて相互に固着
して積層することを特徴とする特許請求の範囲第
1項記載の半導体装置。 4 前記積層用半導体基板の厚さは、前記一端付
近の内径が他端付近の内径より小さい形状を有す
る硬質の円筒体の内部にその一端から突出するよ
うに充填された金属体からなる導電性連結粒の高
さと略同じであることを特徴とする特許請求の範
囲第1項記載の半導体装置。
[Scope of Claims] 1. A semiconductor substrate on which at least a semiconductor element is formed and a plurality of pads are formed on a predetermined portion of the surface, and a connecting hole is formed on the back surface of the pad at a location corresponding to the pad formed on the surface. at least one laminated semiconductor substrate having an opening in the thickness direction so as to expose at least a portion thereof and on which a semiconductor element is formed; The cylindrical body is filled with conductive connecting particles made of a metal body so as to protrude from one end of the cylindrical body, and the cylindrical body is arranged so that the back surface of the pad exposed from the connecting hole of the semiconductor substrate for lamination is are fixed to each other through the protruding portions of the connected grains, and the semiconductor substrate for lamination and the semiconductor substrate are
A semiconductor device characterized in that the semiconductor device is stacked by fixing the connecting grain exposed at the other end of the cylindrical body to another conductive connecting grain arranged on the pad side of the semiconductor substrate. 2. The conductive connecting grains used in addition to the conductive connecting grains fixed to the pads in the connecting holes of the semiconductor substrate for lamination are hard cylindrical bodies having a shape in which an inner diameter near one end is smaller than an inner diameter near the other end. 2. The semiconductor device according to claim 1, further comprising a metal body filled inside the cylindrical body so as to protrude from one end of the cylindrical body. 3. A plurality of the semiconductor substrates for lamination are prepared, and each of the semiconductor substrates for lamination has pads in areas other than the areas corresponding to the connecting holes, and the pads other than the connecting holes of the semiconductor substrate for lamination in the first layer are different from each other. The exposed part of the back surface of the pad corresponding to the connecting hole of the second layer semiconductor substrate for lamination is placed inside a hard cylindrical body having a shape in which the inner diameter near one end is smaller than the inner diameter near the other end. Conductive connecting grains made of a metal body filled in such a way as to protrude from one end are used to adhere to each other and stack, and in the same way, semiconductor substrates for lamination from the third layer onwards are sequentially connected to the conductive connecting grains and the cylinder. 2. The semiconductor device according to claim 1, wherein the semiconductor device is stacked by being fixed to each other using conductive connecting particles filled inside the semiconductor device. 4. The thickness of the semiconductor substrate for lamination is determined by a conductive metal body filled in a hard cylindrical body having an inner diameter near one end smaller than an inner diameter near the other end so as to protrude from one end. 2. The semiconductor device according to claim 1, wherein the height is substantially the same as that of the connected grains.
JP21662287A 1987-08-31 1987-08-31 Semiconductor device Granted JPS6459845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21662287A JPS6459845A (en) 1987-08-31 1987-08-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21662287A JPS6459845A (en) 1987-08-31 1987-08-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6459845A JPS6459845A (en) 1989-03-07
JPH0577339B2 true JPH0577339B2 (en) 1993-10-26

Family

ID=16691319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21662287A Granted JPS6459845A (en) 1987-08-31 1987-08-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6459845A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119659A (en) * 2002-09-26 2004-04-15 Fujitsu Ltd Manufacturing method of semiconductor device
JP4325630B2 (en) 2006-03-14 2009-09-02 ソニー株式会社 3D integration device

Also Published As

Publication number Publication date
JPS6459845A (en) 1989-03-07

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