JPH0373145B2 - - Google Patents

Abstract

PURPOSE:To facilitate laminating a laminating semiconductor substrate on a semiconductor substrate three-dimensionally and avoid development of crackings by a method wherein pads on the semiconductor substrate and exposed parts of pads corresponding to the contact holes of the laminating semiconductor substrate are fixed and connected together with pairs of conductive connecting particles. CONSTITUTION:A semiconductor substrate 21 on which at least a semiconductor device is formed and pads 22 are formed at predetermined positions on its surface and at least one laminating semiconductor substrate 6 which has contact holes 7 along its thickness direction and on which pads 2 and 3 are formed in the neighborhood including bottom parts of the contact holes 7 so as to expose at least parts of them in the bottoms of the contact holes 7 and at least a semiconductor device is formed are prepared. The pad 22 on the semiconductor substrate 21 and the exposed part of the pad 3 corresponding to the contact hole 7 of the laminating substrate 6 are fixed and laminated together with a pair of connecting particles 16 and 23. With this constitution, development of crackings caused by thermal stress can be avoided and a three-dimensional structure semiconductor device which has excellent heat radiation properties, high integrity and high reliability and facilitates multiplied functions compared to the conventional SOI structure can be obtained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and relates to a semiconductor device having a three-dimensional structure in which a plurality of semiconductor substrates on which semiconductor elements and the like are formed are laminated. .

(Prior Art) In recent years, three-dimensional SOI (Silicon on Insulation) devices have been actively developed for the purpose of increasing the integration and multifunctionality of semiconductor devices. This is a technique in which a silicon single crystal is formed on an amorphous insulating film on the surface of a semiconductor substrate, a semiconductor element is manufactured using the single crystal layer, and the semiconductor elements are stacked three-dimensionally. Such technology is described, for example, in Nikkei Electronics, October 17, 1985 issue, pages 229-253,
3D is emerging as a multifunctional device
LSI”.

However, SOI technology is still in the early stages of development and has a number of drawbacks in terms of practical application.
The essential disadvantages are that different materials are laminated in multiple layers and single crystallization is progressed through a high-temperature process, so the stress is extremely large and cracks are likely to occur, and the layers have a close contact structure. Because of this, heat dissipation is low and heat is easily trapped. Furthermore, it is impossible with current technology to stack semiconductor materials other than silicon.

(Problems to be Solved by the Invention) The present invention solves the above-mentioned problems of crack generation and deterioration of heat dissipation caused by three-dimensionalization, and achieves high reliability and
The present invention aims to provide a semiconductor device that achieves high integration and multifunctionality.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a method in which a semiconductor element is formed at least,
and a semiconductor substrate having a pad formed on a predetermined portion of its surface, a connecting hole in the thickness direction, and a pad formed around the connecting hole including the bottom so that at least a part of the pad is exposed to the bottom surface. and at least one laminated semiconductor substrate on which a semiconductor element is formed, and a pad of the semiconductor substrate and an exposed portion of the pad corresponding to a connecting hole of the laminated semiconductor substrate are connected with two conductive connection grains. It is characterized by being adhered and laminated through.

(Function) The present invention provides a structure in which between a semiconductor substrate on which a semiconductor element, etc. is formed, and a laminated semiconductor substrate on which the same element is formed,
Further, by fixing and connecting the semiconductor substrates for stacking to the exposed portion of the pad corresponding to the connecting hole of the semiconductor substrate for stacking and the pad on the other side via conductive connecting grains, the semiconductor substrates for stacking are bonded and connected to each other via conductive connecting grains. Substrates can be stacked three-dimensionally. Further, since the semiconductor substrates are laminated with each other using connected grains, thermal stress can be absorbed by the connected grains, and the occurrence of cracks as in the conventional SOI structure can be prevented. Further, since the semiconductor substrates are laminated with each other by connecting grains, and a desired gap can be formed between the substrates, heat is not trapped between the substrates, and heat dissipation is improved. In particular, since it is possible to circulate the coolant in the gap between the substrates, a significant heat dissipation effect can be exhibited.

(Examples of the Invention) Examples of the invention will be described in detail below along with manufacturing methods.

() First, the thickness was 450μ by two-dimensional LSI manufacturing method.
A silicon wafer 1 with a size of
Pads 2..., 3... of 50 μm x 50 μm were formed.
Among these pads, a portion of pads 3 corresponding to connecting holes described later are embedded in the openings formed in the interlayer insulating film, and a thin oxide layer is formed on the substrate surface at the bottom of the openings. A film is formed. This oxide film is used to prevent electrical connection of the pad to the substrate surface, which would be an obstacle in the die sort test. However, instead of the thin oxide film, an impurity diffusion layer for creating a pn junction may be formed on the peripheral substrate surface including the bottom of the opening. Next, openings of 30 μm are formed on the back surface of the silicon wafer 1 corresponding to the pads 3 by a combination of isotropic etching and anisotropic etching.
A wine cup-shaped hole 4 measuring m×30 μm and 50 μm deep was opened (as shown in FIG. 1a). Note that the etching was performed using fluorine-based plasma in both cases.

() Next, after performing a die sort test on the silicon wafer, dicing is performed to produce individual chips, which are then sorted to produce 5 good chips.
was obtained (as shown in FIG. 1b). Subsequently, the entire back surface of the non-defective chip 5 was subjected to anisotropic etching to produce a thin plate-shaped semiconductor substrate 6 for lamination having a thickness of 45 μm (as shown in FIG. 1c). In this anisotropic etching process, the wine cup-shaped hole 4 opened on the back surface is etched while substantially maintaining its shape, so that a tapered connecting hole 7 is formed. Also, during the etching, the thin oxide film at the bottom of the opening was removed,
A pad 3 is provided at the bottom of the connecting hole 7 corresponding to the opening.
exposed part of.

() Next, spherical connecting particles made of, for example, Au are fixed in the connecting holes 7 of the semiconductor substrate 6 for lamination. This will be explained with reference to a device comprising a connected particle fixing device 13 consisting of a gun barrel 12, and a holding table 15 having a built-in heater 14 on which a semiconductor substrate is set.

First, the semiconductor substrate 6 for lamination was set on the holding table 15 so that the opening of the connecting hole 7 of the semiconductor substrate 6 faced upward, and then the gun barrel 12 was aligned with the connecting hole 7 of the semiconductor substrate 6 (the second (Figure a shown). Subsequently, the holding table 1 is heated by the built-in heater 14.
5 to 300°C, the outside of the gun barrel 12 is maintained at about 350°C by the heater 11, and the gun barrel 1 is heated to 300°C.
A spherical Au particle 16 with an inner diameter of 30 μm is inserted into the hole 2, and the compressed nitrogen 17 heats the Au particle 16 and radiates it with acceleration to form the pad 3 at the bottom of the connecting hole 7, as shown in FIG. 2b. It is fixed by hot pressure welding on the exposed part. In addition, 8 in Figure 2b
9 is an interlayer insulating film for electrically insulating the substrate 6 and the pad 3, and 9 is an opening formed in the insulating film 8 to expose a part of the pad 3 to the bottom of the connecting hole 7. . Through these processes, the first
A semiconductor substrate 6 for lamination was obtained in which Au grains 16 were fixed to the exposed portions of the pads 3 corresponding to the connecting holes 7 shown in FIG. d.

() Next, the thickness was determined using a two-dimensional LSI manufacturing method.
A 50 μm x 50 μm pad consisting of a semiconductor element, wiring between elements, and an Al film was formed on a 450 μm silicon wafer. Subsequently, after the die sort test, the silicon wafer is diced, non-defective chips 21 are selected, and spherical Au particles with a diameter of 40 μm are placed on the pads 22 on the surface of the non-defective chips 21 using the aforementioned connected particle fixing machine. 23 was fixed (as shown in Figure 1e).

() Next, the semiconductor substrate 6 for lamination produced in the steps () to () above is placed on the good chip 21 produced in the step () above.
The Au particles 23 on the pad 22 and the semiconductor substrate 6
The Au particles 23 and 16 were stacked so that they matched with the Au particles 16 in the connecting holes 7, and then the semiconductor substrate 6 for lamination was pressed against the chip 21 while heating at 300° C., thereby fixing the Au particles 23 and 16 to each other. 1
Figure f (illustrated). Subsequently, spherical Au particles 24 were bonded and fixed by thermocompression onto predetermined pads 2 and 3 on the surface of the stacked semiconductor substrates 6 using the above-mentioned connecting fixing machine (as shown in FIG. 1g).

() Next, a plurality of thin plate-shaped semiconductor substrates for lamination are produced by the same steps as in () to () above, and these semiconductor substrates are placed on top of the semiconductor substrate 6 laminated as shown in FIG. 1g above. A multilayer stacked semiconductor device (not shown) was manufactured by sequentially stacking layers in the same process as above.

Therefore, in the semiconductor device of the present invention, the semiconductor substrate 6 for lamination is connected between the non-defective chip 21 on which a semiconductor element or the like is formed and the semiconductor substrate 6 for lamination on which the same element is formed, and further between the semiconductor substrates 6 for lamination 6. The semiconductor has a highly integrated and multifunctional three-dimensional structure because it is fixed and stacked on the exposed part of the pad 3 corresponding to the hole 7 and on the mating pad 22 via the Au grains 23, 16, and 24 as connecting grains. You can get the equipment.

In addition, since the non-defective chip 21, the semiconductor substrate 6 for lamination, and the lamination between the semiconductor substrates 6 for lamination are made of the Au grains 23, 16, 24 as connecting grains, thermal stress is not applied to the Au grains 23, 16, 24. This prevents the occurrence of cracks that occur in conventional SOI structures. Furthermore, for the same reason, a desired gap can be formed between the non-defective chip 21 and the laminated semiconductor substrate 6, and between each semiconductor substrate 6, so that heat is not trapped between the substrates, and heat dissipation is improved. Therefore, a semiconductor device having a highly reliable three-dimensional structure can be obtained.

Furthermore, by making the shape of the connecting hole 7 tapered, when the spherical Au grains 16 are fixed to the exposed part of the pad 3 corresponding to the connecting hole 7, the Au grains 1
Since Au particles 16 can be fixed without coming into contact with the inner surface of the connecting hole 7 of the semiconductor substrate 6, short circuits caused by contact between the Au particles 16 and the inner surface of the connecting hole 7 can be prevented.

Furthermore, according to the method shown in the example, after forming wine cup-shaped holes 4 on the back surface of the silicon wafer by a combination of isotropic etching and anisotropic etching, the entire back surface is anisotropically etched. Thus, a thin plate-shaped semiconductor substrate 6 for lamination having a tapered connection hole 7 can be easily produced. Furthermore, by using the connected grain fixing machine shown in FIG. 2, connected grains such as Au grains can be thermocompressed and fixed onto the exposed portion of the pad 3 without causing damage to the pad 3 or the like.
As a result, a three-dimensionally structured semiconductor device can be manufactured through extremely simple steps.

In addition, in the above example, spherical Au was used as the connected grains.
Although grains were used, for the purpose of cost reduction, etc., connected grains in which the surface of spherical stainless steel grains was coated with an Au film may also be used. Specifically, as shown in FIG. 3, for example, a nickel film 32 with a thickness of about 3 μm is formed on the surface of a spherical stainless grain 31 with a diameter of 30 μm by a plating method, and then a nickel film 32 with a thickness of about 3 μm is formed on the nickel film 32 by a plating method. Connected grains 34 formed with an Au film 33 having a thickness of about 3 μm may also be used. In this case, particles of other metals, glass, ceramics, or heat-resistant plastics may be used instead of stainless steel particles. Further, the shape of the connected grains is not limited to a spherical shape, but may be any shape such as a cylindrical shape. However, from the viewpoint of thermal stress alleviation effect and operability, it is desirable to use spherical connected grains.

In the above embodiment, a structure in which only a plurality of laminated semiconductor substrates made of silicon are used and these laminated semiconductor substrates are laminated on a chip has been described, but the present invention is not limited to this. For example, a wiring board is inserted between the semiconductor substrates for lamination via a connecting grain, and a current path is established between the semiconductor substrate for lamination on the lower layer side and the semiconductor substrate for lamination on the upper layer side with the wiring substrate as a boundary. It may be changed. Further, as shown in FIG. 4, a chip 41 is formed of silicon, a silicon semiconductor substrate 42 and a gallium arsenide semiconductor substrate 43 are laminated on this silicon chip 41, and further these silicon semiconductor substrate 42 and gallium arsenide semiconductor substrate 43 are laminated. The semiconductor device may have a three-dimensional structure in which a silicon semiconductor substrate 44 is stacked on top of the semiconductor substrate. With the configuration shown in FIG. 4, it is possible to easily realize a semiconductor device with a three-dimensional structure that has more functions than the conventional SOI structure.

[Effects of the Invention] As detailed above, the present invention prevents the occurrence of cracks due to thermal stress, has excellent heat dissipation, and has a highly integrated and highly functional structure that can be multi-functional compared to conventional SOI structures. A semiconductor device with a reliable three-dimensional structure can be provided.

[Brief explanation of drawings]

FIGS. 1a to 1g are cross-sectional views showing the manufacturing process for obtaining a three-dimensional semiconductor device of the present invention, and FIGS.
Figure 3 is a cross-sectional view showing the process of fixing Au grains.
A cross-sectional view showing another example of connected grains used in the present invention,
FIG. 4 is a sectional view showing a three-dimensional semiconductor device according to another embodiment of the present invention. 1... Silicon wafer, 2, 3, 22... Pad, 6... Semiconductor substrate for lamination, 7... Connecting hole, 8
... interlayer insulating film, 9 ... hole, 12 ... gun barrel,
13... connected grain fixing machine, 15... holding stand, 16,
23, 24...Au grain, 21...Good chip, 3
1...Stainless grain, 34...Connected grain, 41...
Silicon chip, 42, 44... silicon semiconductor substrate, 43... gallium arsenide semiconductor substrate.

Claims (1)

[Claims] 1. A semiconductor substrate on which at least a semiconductor element is formed and a pad is formed on a predetermined portion of the surface;
At least one semiconductor for lamination, which has a connecting hole in the thickness direction, and a pad is formed around the connecting hole including the bottom so that at least a part of the pad is exposed on the bottom surface, and a semiconductor element is formed thereon. A semiconductor device comprising: a substrate; a pad of the semiconductor substrate and an exposed portion of the pad corresponding to the connection hole of the semiconductor substrate for lamination are fixed via two conductive connection grains and stacked; . 2. The semiconductor substrate for lamination consists of a plurality of sheets, which have pads in addition to the area corresponding to the connecting hole,
Fixing the pads other than the connecting holes of the first-layer laminated semiconductor substrate and the exposed portions of the pads corresponding to the connecting holes of the second-layer laminated semiconductor substrate via two connecting grains,
2. The semiconductor device according to claim 1, wherein the semiconductor substrates for laminating the third and subsequent layers are sequentially fixed and laminated via connecting grains. 3. The semiconductor device according to claim 1, wherein the thickness of the semiconductor substrate for lamination and the size of the connecting grains are substantially the same.