JPS63207276A - Facsimile decoding circuit - Google Patents

Abstract

PURPOSE:To quickly decode a non-compressed mode code with an inexpensive constitution by performing switching of run length data, switching of color of a reproduced picture signal, and generation of a load signal to a counter by a control circuit having a hardware constitution. CONSTITUTION:When detecting the non-compressed mode code, a sequence ROM 1 inputs the detection signal to a main sequence ROM 5. Then, the main sequence ROM 5 outputs the load signal which sets white run length data to a counter 3. A run length end signal is inputted to a control circuit 6 also. When the run length end signal is inputted to the control circuit 6, the control circuit 6 switches a switching gate so that black run length code is outputted. When detecting the black run length end signal, the control circuit 6 decides that the processing concerning one non-compressed mode code is terminated and inputs a code processing end signal to the main sequence ROM 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a facsimile decoding circuit, and more particularly to a decoding circuit for uncompressed mode codes.

(Prior Art) As is well known, CCITT Recommendations T4 and T6 allow for the optional use of uncompressed mode codes in addition to compressed mode codes.

FIG. 5 is a block diagram showing a conventional decoding circuit for decoding this uncompressed mode code.
It consists of a run length data switching gate, a 2° picture signal reproduction counter, a 32 picture number 48 reproduction shift register 4, and a main sequence ROM 5.

Here, the uncompressed mode code consists of run-length data and a code that returns from the uncompressed mode to the original mode,
The run length data includes the content of a white run length followed by a black run length. Sequence ROM
I detects such an uncompressed mode code using the input code data. When an uncompressed mode code is detected, first, white run length data is input to the counter 3 via the data switching gate 2. do. On the other hand, the main sequence ROM 5 inputs a load signal to the counter 3 after a predetermined time delay. As a result, white run length data is loaded (set) into the counter 3. When the run length data is set, the counter 3 transmits a start signal to the shift register 4 to start reproducing the image signal.

In the shift register 4, since the color of the reproduced image signal is specified from the main sequence ROM 5 in advance,
From the time when the start signal is input from the counter 3, the image signal reproduction operation starts in the designated color. With the start of this image signal reproduction operation, the signal ENB is sent back from the shift register 4 to the counter 3. From the time when this signal eENB is sent back, the counter 3 counts down the run length data ( After the time indicated by the run length data has elapsed, a run length end signal is generated, and this signal is sent to the shift register 4 and the main sequence ROM 5.
Enter.

The shift register 4 stops reproducing the white image signal upon input of the run length end signal. On the other hand, the main sequence ROM 5 counts up an internal processing end counter (not shown) by inputting the GQ planning end signal, switches the switching gate 2 so that the black run length data is input to the counter 3, and then When the predetermined time approaches, the load signal is output again. As a result, counter 3
Black run length data is set in , and the operation of the counter 3 and shift register 4 reproduces a black image signal having a length indicated by the black run length data. When the playback is finished and a run length end signal is output from the counter 3, the main sequence ROM
5 counts up the internal processing 3111 completion counter and sets it to "2". Then, when the processing end counter = "2", it is determined that the decoding for one uncompressed mode code has been completed, and it is determined whether or not a code exiting from the uncompressed mode has arrived, and the decoding for one uncompressed mode code is determined. If the outgoing code has not arrived, processing returns to the white run length data of the next uncompressed mode code. However, if the code exiting from the non-compression mode is written, it is determined whether the color to be processed next is white or black, and the color of the reproduced image is set according to the determination result.

FIG. 6 is a flowchart showing such operations in sequence.

(Problem to be Solved by the Invention) However, the sequence ROM 5 monitors input signals using software, and controls the external switching gate 2, counter 3, and shift register using software according to the monitoring results. Therefore, the incoming horn monitoring process of "Run length processing completed?" shown in step 14 in FIG. eJP Raw”, Step 15 “White/Black Run Length Data Switch”, Step 1
Several cycle times are required for each step of "self set" and "black set" of 7°18.

Therefore, there is a problem in that the decoding processing time for the uncompressed mode code becomes long. This can be shortened to some extent by increasing the system clock frequency, but this will make the elements more expensive and increase the noise within the circuit board, resulting in cost and reliability issues. A new problem will arise.

An object of the present invention is to provide an inexpensive facsimile decoding circuit that can decode uncompressed mode codes at high speed.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a detection circuit that detects an uncompressed mode code and outputs white and black run length data, and a detection circuit that detects an uncompressed mode code and outputs white and black run length data; A counter that performs a counting operation for a time corresponding to data and outputs a run-length end signal after the elapse of the time, a shift register that reproduces an image signal while this counter is counting, and a shift register that reproduces an image signal in this shift register. A code processing end signal indicating that color switching control, run length data setting control for the jj counter, and reproduction of an image signal for one uncompressed mode code has been completed is outputted, and a code processing end signal is output to the detection circuit to indicate the next uncompressed mode The above object is achieved by providing a control circuit for performing a code detection operation.

(Function) Switching of run length data, switching of the color of the reproduced image signal in the shift register, and generation of a load signal for the counter, which were conventionally performed by software, are performed by a control circuit having a hardware configuration.

Therefore, high-speed processing of uncompressed mode codes becomes possible.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention.
4 is the same as the conventional structure, but a control circuit 6 is added. In this case, since a part of the main sequence ROM was moved to the control circuit 6, the main sequence ROM is shown as 5- here.

In this configuration, when the sequence ROM1 detects an uncompressed mode code, it transmits the detection signal to the main sequence R
Input to OM5-. Therefore, the main sequence ROM
5- outputs a load signal for setting white run length data in the counter 3. On the other hand, when an initialization signal (not shown) is input to the control circuit 6, the data switching gate is switched to output white run length data by the gate switching signal of the control circuit 6. On the other hand, the control circuit 6 is configured to transfer the load signal from the main sequence ROM 5'' to the counter 3 when it is input. Therefore, when the load signal is generated, the counter 3 displays a white line. The length data is set. When the white run length data is set, the counter 3 sends a start signal to the shift register 4 to start reproducing the white image signal.

Accordingly, when the signal ENB is output from the shift register 4, the counter 3 starts a counting operation. Then, after the time indicated by the run-length data has elapsed, a run-length end signal is output, and the playback operation of the white image signal in the shift register 4 is stopped.

The run length end signal is also input to the control circuit 6. Therefore, when the run-length end signal is input, the control circuit 6 switches the switching gate so that black run-length data is output. Further, the color of the reproduced image signal in the shift register 4 is set to black. Further, a load signal is generated at a timing that is a predetermined time after the run length end signal.

As a result, the counter 3 and shift register 4 perform the reproduction operation of the black image signal based on the black run length data. Then, when the playback image of the black image signal is finished,
The run length end signal is output from counter 3 again,
The signal is input to the flilJ control circuit 6. When the control circuit 6 detects the black run-length end signal, it determines that the processing for one uncompressed mode code has ended, and inputs the code processing end signal to the main sequence ROM 5'.

Therefore, the main sequence ROM 5- determines whether or not a code coming out of the uncompressed mode code has arrived, and if so, inputs a detection signal indicating this to the control circuit 6, and selects the next color to be processed by the control circuit. 6 to set it in the shift register 4.

The flowchart in FIG. 2 shows the processing contents of the main sequence ROM 5- in the above configuration. As shown, since the number of processing steps is significantly smaller than in the case of FIG. 6, it is clear that high-speed processing of uncompressed mode codes becomes possible.

FIG. 3 is a circuit diagram showing the detailed configuration of the control circuit 6,
a first flip-flop F1 for alternately switching between run length data set in the counter 3 and white and black run length data each time the run length end signal is generated;
Each time the run length end signal is generated, the shift register 4
a second flip-flop F2 for switching the color of the reproduced image signal, a gate G1 for outputting a code processing end signal according to the run length end signal when the color of the reproduced image signal is black, and generation of the run length end signal. The third and fourth flips 70 and gates G6 and G7 output a load signal for setting run length data in the counter 3 at a timing two cycles of the clock signal CLK from the timing, and the generation of a code processing end signal. A fifth flip-flop F5 and gates G3 to G5 set the second flip-flop F2 to a state corresponding to the next color to be processed if a code coming from an uncompressed mode code is present.
It is composed of.

Figure 4(a) - Uncompressed mode code detection Shintan when uncompressed mode code is detected in (CI>), main sequence R
The time chart shows the load signal generated by OM5-, the gate switching signal, the run length end signal, the load signal input to the counter 3, the reproduction color in the shift register 4, and the code processing end signal.

[Effects of the Invention] As explained above, according to the present invention, the switching of run length data, the switching of the color of the reproduced image signal, and the generation of the load signal to the counter are performed by a control circuit having a hardware configuration. , it is possible to decode uncompressed mode codes at high speed with an inexpensive configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a flowchart showing the processing contents of the main sequence RO in the embodiment. FIG. 3 is a detailed diagram of the control circuit in the example.
FIG. 4 is a timing diagram explaining the operation of the circuit in FIG. 3, FIG. 5 is a block diagram showing the conventional decoding circuit configuration, and FIG. This is a flowchart showing the processing contents of the ROM. DESCRIPTION OF SYMBOLS 1...Sequence ROM, 2...Run length switching gate, 3...Picture signal reproduction counter, 4...Signal reproduction shift register, 51...Main sequence RO
M, 6...control circuit.

Claims (2)

[Claims] (1) A detection circuit that detects an uncompressed mode code and outputs white and black run-length data, and a detection circuit that performs a counting operation for a time corresponding to the data when the run-length data is set, and after the elapse of that time. a counter that outputs a run-length end signal; a shift register that reproduces an image signal while the counter is counting; a control for switching the color of the reproduced image signal in the shift register; a control for setting run-length data for the counter; outputting a code processing end signal indicating that reproduction of the image signal for the two uncompressed mode codes has been completed;
A facsimile decoding circuit comprising: a control circuit that causes the detection circuit to detect a next uncompressed mode code. (2) The control circuit includes a first control circuit for alternately switching between run-length data set in the counter and white and black run-length data each time the run-length end signal is generated.
a flip-flop, a second flip-flop for switching the color of the reproduced image signal by the shift register each time the run-length end signal is generated, and the run-length end signal when the color of the reproduced image signal is black. Consisting of a gate that outputs a code processing end signal, and third and fourth flip-flops that output a load signal for setting run length data in the counter at a timing delayed by a predetermined time from the generation timing of the run length end signal. A facsimile decoding circuit according to claim (1), characterized in that: