JPS63207170A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To inhibit a crystal defect and the spread of trench width by forming MOS capacitors by utilizing the side walls of the trenches and burying capacitor electrodes consisting of polysilicon, etc., into all trenches through insulating films. CONSTITUTION:A first mask material 31 is shaped onto a transistor forming region in a first conductivity type semiconductor substrate 11, and the surface of the substrate 11 is etched selectively by using the mask material 31 and trenches 13 for element isolation are formed. Second conductivity type impurity introducing layers are shaped onto the bases and side surfaces of capacitor forming regions in the trenches 13, second mask materials 34 are formed onto the side walls of the trenches 13, and the bottoms of the tenches 13 are etched selectively by employing the first and second mask materials 31, 34 and the impurity introducing layers shaped onto the bases of the trenches 13 are removed. The second mask material 34 is gotten rid of and insulating films 14 are formed onto the wall surfaces of the trenches 13, capacitor electrodes 15 are buried and shaped into the trenches 13, the first mask material 31 is taken off, and a MOS transistor is formed into the transistor forming region. Accordingly, the generation of a crystal defect is inhibited, and the spread of the trenches is prevented.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device in which a memory cell is configured by a MOS transistor and a MOS capacitor, and particularly relates to a semiconductor memory device in which a capacitor is formed in an element isolation trench. The present invention relates to a method of manufacturing a semiconductor memory device.

(Conventional Technique #g) In recent years, MO8-type dRAM has become highly integrated and its elements have become smaller, but the reduction in the area of one memory cell results in a decrease in capacitance, which impairs the reliability of dRAM. It becomes a factor. Therefore, various memory cell structures have recently been proposed in order to reduce the area occupied by the memory cell without reducing the capacitor capacity.

As a typical example, as shown in FIG. 5, a groove 52 is dug in the surface of a substrate 51, the bottom of the groove 52 is used as an element area, and the sidewalls of the groove 52 are used to form a capacitor.
CC (Folded Capacitor Cell
) is known, which makes it possible to increase the capacitor capacity without increasing the planar cell area. In FIG. 5, 53 is a buried oxide film for element isolation, 54 is an oxide film for capacitors, 55 is a capacitor electrode, and 56 is a gate electrode.

However, this type of structure has the following problems. In other words, since an oxide film is embedded in the trench other than the capacitor formation region and at the bottom of the trench in the capacitor formation region, crystal defects occur in the silicon substrate due to stress due to the difference in thermal expansion coefficient between the substrate silicon and the buried oxide film. do. In addition, in the process of leaving the oxide group at the bottom of the trench by etchback, the upper part of the all walls of the trench is etched and the width of the trench increases. It is difficult to leave behind.

(Problems to be Solved by the Invention) As described above, the conventional FCC structure has caused crystal defects in the silicon substrate and widening of the groove width. Further, the crystal defects and the widening of the grooves lead to an increase in junction leakage and a decrease in the capacitor area, causing performance deterioration of dRAM.

The present invention has been made in consideration of the above circumstances, and its purpose is to use only a capacitor electrode such as polysilicon as the material to be buried in the groove, to eliminate embedding and etchback of oxide film, and to eliminate crystal defects and grooves. An object of the present invention is to provide a method for manufacturing a semiconductor memory device that can suppress width expansion and improve reliability of memory cells.

[Structure of the Invention] (Means for Solving Problems) The gist of the present invention is to use only polysilicon as the material to be buried in the trench without using an oxide film, and to ensure reliable element isolation even in this state. It is in.

That is, the present invention provides a method for manufacturing a semiconductor memory device in which a memory cell is configured from a MoS transistor and a MOS capacitor, in which a first mask material is formed on a transistor formation region of a semiconductor substrate of a first conductivity type, and then this mask material is The surface of the substrate is selectively etched using etching to form a trench for element isolation, and then a second conductivity type impurity-introduced layer is formed on the bottom and side surfaces of the capacitor formation region of this trench, and then the trench is etched. forming a second mask material on the sidewalls of the groove, and then selectively etching the bottom of the groove using the first and second mask materials to remove the impurity-introduced layer formed on the bottom of the groove; Then, after removing the second mask material, an insulating film is formed on the wall surface of the trench, and then a capacitor electrode is buried in the trench, and then, after removing the first mask material, an insulating film is formed on the wall surface of the trench. This is a method for forming a MOS transistor.

(Function) According to the present invention, a MOS capacitor is formed using the sidewalls of the trench, and a capacitor electrode made of polysilicon or the like is buried inside the trench through an insulating film. The difference in thermal expansion coefficient between the silicon substrate and the silicon substrate can be reduced, thereby suppressing the occurrence of crystal defects in the silicon substrate. Furthermore, by forming a second mask material on the side walls of the trench during the second etching for element isolation, the side walls of the trench do not recede. Therefore, unlike the conventional method of etching back a buried oxide film, it is possible to prevent the trench from widening.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a plan view showing a memory cell structure of a dRAM according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the arrow AA in FIG. Note that this memory cell has one transistor/
It consists of one capacitor.

An upper well 12 is formed on the p-type Sin plate 1, and a groove 13 provided in the p-well 12 divides the element forming region into island shapes. A capacitor Ia15 made of poly 3i is embedded in the trench 13 with an insulating film 14 interposed therebetween. A MOS capacitor is constituted by this electrode 15 and an n-layer 16 formed on the side wall of the groove 13 by diffusion. Furthermore, a p+ layer 17 for a channel stopper is formed at the bottom of the groove 13.

On the other hand, in the island-like regions (transistor formation regions) divided by the grooves 13, gate electrodes 19 that will become word lines are formed via the gate oxide film 18, and the n+ layer 21 is roughly formed.
, 22 are formed to constitute a MOS transistor. Then, a λ wiring layer 24 is formed on this substrate via an interlayer insulating film 23 to serve as a bit line.

Here, the width of the groove 13 is narrower at its bottom than the area where the nth layer 16 is formed. Also, the impurity concentration of the substrate 11 is 2X 10''t,m'', p well 1
The impurity concentration of 2 is lX101Tc13. moreover,
+2■ to capacitor electrode 15, -2 to p-well 12
■ is applied.

Next, the manufacturing process of the above device will be explained with reference to FIG.

First, as shown in FIG. 3(a), a 5i02 film 3 as a first mask material is placed on the p-well 12 of the ρ-type S1 substrate 11.
1 and then form n-layers 16 in necessary parts. Subsequently, using 5iO2 1131 as a mask, the surface of the p well 12 is selectively etched by RIE to form a hole 13 for element isolation. The trench 13 divides the transistor formation region into island shapes.

Next, as shown in FIG. 3(b), a resist 32 is applied to the entire surface.
is applied to fill the inside of the groove 13 and flatten the surface. Furthermore, 5OG (spin-on glass) [
133 is formed, and this SOG film 3 film tube 3 n layer 16 is removed. Next, as shown in FIG. 3(C), the SOG
A resist 32 is etched on the membrane 3 membrane tube 3 screen by 02RIE, and As ions are implanted to form the p-well 1.
A layer 16 is again formed on the side and bottom surfaces of the groove 13 of No. 2.

Next, after removing the SOG film 3 and film tube 3 resist 32, as shown in FIG. 3(d), a CVD-8i02 film 34 serving as a second mask material is formed on the entire surface. Then, SiO
Using the two films 31 and 34 as a mask, the bottom of the 13 layers is etched again by RIE, as shown in FIG. 3(e). Next, B is ion-implanted into the bottom of the trench 13 to form a p'' 117. At this point, during the second etching, the SiO2 film 34 acts as a mask, so the sidewalls of the trench 13 are etched. will not retreat.

That is, when a groove that has been formed is etched again by RIE, the sidewalls of the groove are also etched, leading to an increase in the width of the groove, but the SiO2 film 34 left on the sidewalls prevents this.

In addition, during the above etching, silicon and 5iO211
If a gas that etches 134 is used, the SiO2 film 3
Although the S i 02111134 on the groove 1 and the bottom of the groove 13 is removed, the SiO2 film 34 can remain on the sidewall of the groove 13. As a result, Fig. 3(,e)
Selective etching of only the bottom of the groove 13 as shown in FIG. Alternatively, instead of this method, the SiO2 film 34 is etched back by RIE by an amount corresponding to the thickness of the film 34, and then the SiO2 film 31 and the trench sidewalls are etched by RIE.
It is also possible to perform selective etching of silicon using the 02 film 34 as a mask.

Next, after removing the 5i02 film 34, as shown in FIG.
As shown in the figure, the wall surface of the groove 13 has a thickness of, for example, 20
0 thin 5i0211! (Insulating film for capacitor) 14
form. Next, poly 5ill all over! A capacitor electrode 15 is deposited, its surface is planarized, and phosphorus is further diffused. Instead of this phosphorus diffusion, polyS
As the i film, phosphorus-doped or arsenic-doped poly 3i can also be used. Next, the third layer is etched back.
As shown in Figure (g), the capacitor electrode 15 is etched so that the capacitor electrode 15 remains only in the groove 13.

Next, as shown in FIG. 3(h), the entire SiO2 film 31 is
1, then gate oxide film 18. A MOS transistor is formed by forming the gate electrode 19 and n''!21°22 which will become the source and drain.From this point on, as in the normal process, the bit line will become the bit line through the living room insulating film. By forming two wiring lines, etc., the structure shown in FIGS. 1 and 2 can be realized.

In the memory cell thus formed, since the material buried in the groove 13 is only the poly 3i film which becomes the capacitor electrode 15, the coefficient of thermal expansion between the material buried in the groove and the 81 substrate (p-well) is This makes it possible to avoid problems such as crystal defects occurring in the substrate due to the difference in thermal expansion coefficients.

In addition, since there is no need to perform etch-back unlike filling in an oxide film, it is possible to prevent the trench from widening. Therefore, the reliability of the dRAM memory cell can be improved, and it is effective for high integration. Furthermore, during the second etching of the bottom of the trench 13 (etching for element isolation), the 5iOz film 34 acts as a mask, so this etching may cause inconveniences such as the sidewalls of the trench 13 receding. can be avoided.

Note that the present invention is not limited to the embodiments described above. fruit! i! ! In the example, a groove is formed in the p-well,
When forming grooves directly on the substrate, the insulating film 14 may be made thicker (for example, 1000 thick) than in the previous embodiment, as shown in FIG. Furthermore, when the thickness of the cut-off film 14 is the same as in the previous embodiment, the potential applied to the substrate side may be set to Ov, for example, to reduce the potential difference between the substrate and the capacitor electrode. Furthermore, the above insulation 111wo8 i 02 /S i N/
S i 02 (7) It is also possible to increase the capacitor capacity by using a three-layer structure.

Furthermore, in the embodiment, the silicon was etched using the SiO2 film as a first mask to form the element isolation grooves, but any film that is resistant to RIE can be used as this mask. Furthermore, it is possible to use S;N or others instead of SiO2 as the second mask material. Furthermore, the material that is once buried in the groove is not limited to resist, but may be any flattening material. Furthermore, the formation of the impurity-introduced layer is not limited to ion implantation, but it is also possible to use ΔsSG diffusion or the like.

Further, the poly layer 3i may be provided not only as a single layer but also as a two-layer structure with an oxide thin film interposed between them.

In this case, the boundaries between the poly-Si layers of the buried capacitor electrodes are shown by broken lines in FIG. 3(h). In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to suppress crystal defects and widening of groove width, prevent junction leakage and decrease in capacitor area, and realize a highly reliable semiconductor memory device. can do.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a memory cell structure of a dRAM according to an embodiment of the present invention, FIG. 2 is a sectional view taken along arrow A-A in FIG. 1, and FIG. 3 shows a manufacturing process of the memory cell. cross section,
FIG. 4 is a sectional view for explaining another embodiment of the present invention;
FIG. 5 is a sectional view showing a conventional memory cell structure. 11...3i substrate, 12...p well, 13...
Element isolation groove, 14...S i 02 film (insulating film),
15... Capacitor electrode, 16... n'' layer, 17.
...p+ layer, 18...gate oxide film, 19...gate electrode (word line), 21.22...n+ layer, 23.
...Interlayer insulating film, 24...A2 wiring layer (bit II>
, 31... SiO2 film (first mask material), 32...
- Cyst, 33... SOG film, 34... SiO2
Membrane (second mask material). Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 3 (1) Figure 3 (4) Figure 4 Figure 5

Claims (4)

[Claims] (1) A method for manufacturing a semiconductor memory device in which a memory cell is configured from a MOS transistor and a MOS capacitor, including the step of forming a first mask material on a transistor formation region of a semiconductor substrate of a first conductivity type; a step of selectively etching the surface of the substrate to form a trench for element isolation using the method; a step of forming an impurity-introduced layer of a second conductivity type on the bottom and side surfaces of the capacitor formation region of the trench; a step of forming a second mask material on the side wall of the groove; and selectively etching the bottom of the groove using the first and second mask materials to remove an impurity-introduced layer formed on the bottom of the groove; a step of forming an insulating film on the wall surface of the trench after removing the second mask material; a step of embedding a capacitor electrode in the trench; and a step of removing the first mask material. 1. A method of manufacturing a semiconductor memory device, comprising the step of forming a MOS transistor in a transistor formation region. (2) As the selective formation step of the impurity-introduced layer, after burying a resist in the trench and flattening the surface, a third mask material is formed on the resist except for the capacitor formation region, and then this Manufacturing a semiconductor memory device according to claim 1, wherein the resist is etched using a third mask material, and then impurities are introduced using the third mask material as a diffusion mask. Method. (3) The second mask material is formed on the first mask material and the entire wall surface of the groove, and then the portions on the first mask material and the bottom of the groove are removed by etchback. A method for manufacturing a semiconductor memory device according to claim 1, characterized in that: (4) The method of manufacturing a semiconductor memory device according to claim 1, wherein a silicon substrate is used as the semiconductor substrate, and a polysilicon film is used as the capacitor electrode.