JPS63206828A - Stretch circuit for maximum value - Google Patents

Abstract

PURPOSE:To lower cost and miniaturize a device, by providing (n-1) of data effective bits, and detecting the maximum values of (n)-number of data shift registers with (n-1)-number of comparators. CONSTITUTION:A digital value data 2 of (k)-bits is inputted to an input register 3 at every supplying of a clock pulse 1, and is shifted to the data shift registers 51-54 in order. When a valve 1 is stored in the register 3, since all of the values 61-64 of the data shift register 5 are all 0s, the outputs of the comparators 71-73 show A>B, and all of the values 132-134 of a data effective register 12 are shown as invalid valves. Therefore, an AND gate 81 becomes effective, and a tri-state buffer 91 is opened, and the data 61 of the register 51 is outputted to a maximum stretch data 10. Next, when a value 3 is stored in the register 3, since it is larger than the values of the data 61-63, all of the values show the invalidity of data, then, the data 3 of the register 51 is outputted to a data 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field J] This invention relates to a peak hold device in a system that inputs and processes digital information every time a clock pulse is applied.

[Prior Art] A conventional circuit of this type is shown in FIG. FIG. 4 shows the maximum value stretch circuit when the data shift register's value (6) is set to 4.

In the figure, (1) #-t clock pulse, (2) bit digital value data, (3) input register that inputs digital value data (2) every time a positive pulse is applied, and (4) Its output is an input register output register, (5) is a data shift register that shifts data every time a clock pulse (1) is applied, (6
) is its output data shift register output data,
(7) is the output data of each data shift register, (6) a ratio converter that compares the magnitude of darkness, and (8) a logical operation of the output of the Vi ratio converter (7) to determine the data shift register with the maximum value. AND goo), (9) is the AED gate (8
) is the tri-state buffer for outputting the register data (6) determined by (io) is the maximum value stretch data that is its output.

Next, the operation will be explained with reference to FIG.

n pieces of data (n=4 in Figure 4) datal ~ da
Whether the first data datai in tanO has the maximum value depends on the remaining n-1 data data1 to 1-
1. It may be determined whether the following conditions are satisfied by comparing the size with data i+l-n.

data i) data l data i
) data i+1data i) data
2 data i) data i+2dat
ai) data-1data i) dat
For example, assume that the maximum value is stored in the second register (52) of the data shift registers (5).

Whether the data (62) stored in this register is the maximum value is determined by the register (51, 5s r 5
4) Data stored in (6t + 62 + 6
g) and a comparator (7l(I 7z-t + 72-
2) may be used to compare the sizes.

Since it is now assumed that the second register has the maximum value, the output I/1A)B of the ratio converter 71-1, the comparator 72-
The outputs of 1+72-2 are both A) and B. Result 4
Of the A11D gates (8), only the output of (82) is valid and the tri-state buffer (92) is involved. Therefore, the data (6z) of the data shift register (52) having the maximum value is output as the maximum value stop data (10). Other data shift registers (51+5m, 54
The operation is similar when the maximum value is stored in ).

In this way, as the maximum value stop data (10), the data (6) of the register having the maximum value among the data shift registers (5) is always output.

Also, input bit digital value data (2)
is held for four times in the data shift register (5). Therefore, when the maximum value is input, the maximum value stretched by 3 clocks (the maximum value continues for 4 clocks) is output as the maximum value stretch data (10).

[Problem to be solved by the invention] The conventional maximum value stretch circuit is configured as described above.
Therefore, if the stretch period is fil f n -1 clocks (maximum value f, nr output), there is a drawback that nC2 comparators are required to detect the maximum value.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a maximum value stretching circuit that is inexpensive, compact, and capable of OJ, which is composed of n-1 comparators. .

Means for Solving the Problem J The maximum value stretch circuit according to the present invention is provided with n-1 data valid bits.

The detection of the maximum value in n data shift registers is
- This is done using one comparator.

[Operation J] The maximum value stretch circuit of the present invention compares newly input digital value data with data stored in n -1 registers in the previous stage among the n pig shift registers. , the comparison result is stored as a data valid bit, and a logical operation is performed to detect the maximum value among the n pieces of data.

Example of “one shot”] Hereinafter, examples of the present invention will be explained with reference to the drawings.

FIG. 1 shows a liquid trench circuit according to an embodiment of the present invention, and the same or equivalent parts as those in FIG. 4 are shown.゛FIG. 1 #-i Similar to FIG. 4, this shows the maximum value trench circuit when the number of data shift registers is set to 4.

In Figure 1, (1) is clock puffless s (2)
rik bit digital 1 direct data, (3) is an input register that inputs digital value data (2) every time a clock pulse (1) is applied, (4) is the output data of the human input register, (5 ) is the clock pulse (
The data shift register that shifts 1"-':i', (6) is its output data shift register output, /117 data, (7) is the input register output data (4) and the four A comparator that compares the outputs (6t to 63) of the three preceding registers in the data shift register, and (11) an AND gate that determines whether the data stored in the data shift register is valid. , (12) is the data valid storage register of nl pins (in the example, n = 4, so 3 pins), and the comparator (7 pins) is the data valid storage register.
1) and AND (list 114) are stored, and a data valid signal (13) is output. (8) is an AND game that performs a logical operation on the data valid signal (13) to determine the data shift register with the maximum value), (9) is an AND game
Register data (6) determined by gate (8)
A tri-state buffer for outputting (10
) is the maximum value stretch data that can be obtained from the output.

Next, let’s talk about the operation! This will be explained with reference to FIG. 81 and FIG. 2 as appropriate.

K-bit digital 1 direct data (2) is input to the input register (3) every time a clock pulse (1) is applied, and is sequentially shifted to the data shift registers (51 to 54). 0.0.0.0.
1, 3.2.4.3.2.1.0.0.0. If you input O, the input register (3J), the value (4) of the data shift register (51-54).

(61-64) change to the values shown in FIG. Time t
.

When the value 1 is stored in the input register, the data shift register values (61 to 64) I/'i are all set to 0, so the outputs of the comparators (7t to 73) are all A. ) B
, and the data valid storage register (1
2) values (132 to 134) all indicate data invalidity.

As a result, the °CAND gate Cpl) is enabled, the tri-state buffer (91) is opened, and the data shift register (
5□) data (61) is the maximum value stretch data (1
0). In other words, the maximum @ at time t1 is 1. Also, time 1. When the value 3 is stored in the input register, the data in the data shift register (6
1 to 63), so the value of the data valid storage register (12) at time t2 is the same as last time (132 to 134).
indicates that all data are invalid, and the data shift register (5
Data 3 of 1) is output as maximum value stretch data (10). Next, when the value 2 is stored in the input register (3) at time t2, the value 3 is stored in the data shift register (51), so the output of the ratio converter (71) indicates A)B. , at time t3, the data valid signal (132
) only indicates valid. Therefore, the AND gate (82) is enabled, the tri-state buffer (92) is opened, and the data 3 of the data shift register (52) is output as the maximum value stretch data (10). Similar operations are performed after time t4, and maximum value stretch data (10) as shown in FIG. 2 is obtained.

This circuit compares the currently stored data with the next input data, and uses the principle that data with a smaller value than the newly input data cannot reach the maximum value after the next clock. It is.

In the above embodiment, the circuit is configured using a tri-state buffer as an element for outputting the maximum value, but in another embodiment, as shown in FIG. 3, bit n lines to Even if the l line data selector is used, the same effect as in the above embodiment can be obtained. In FIG. 3, (υ~(8), (lO)~(13)) are the same parts as in the embodiment shown in FIG.

Up&! In the embodiment, a manual register was specifically provided for the purpose of synchronizing the k-bit digital value with the circuit, but it is not necessary if the synchronization is established in the first place, and the circuit is constructed using all D flip-flops as registers. However, any synchronous memory element may be used, and the same effect as in the above embodiment can be achieved.

[Effects of the Invention] As described above, according to the present invention, the maximum value trench circuit performs a magnitude comparison between newly input data and n −1 pieces of data in the previous stage currently stored in the data shift register. The output of the nl focus is stored in a data valid storage register as information indicating the presence or absence of data significance for the next stage data, and the maximum value is detected by performing a logical operation on the output. Therefore, the number of required comparators is n -1, and the circuit is inexpensive.
Further, there is an effect that miniaturization is realized.

[Brief explanation of the drawing]

FIG. 1I/'i is a circuit diagram showing a maximum stretch circuit according to an embodiment of the present invention, in which the maximum stretch interval is three clocks (that is, n=4). Figure 2 Fi
Figure 1 is a data diagram for explaining and explaining the operation, Figure 3 is a circuit diagram of another embodiment of the present invention, and Figure vj4 is a circuit diagram showing a conventional maximum trench circuit.
As in Fig. 3, n = 4. In the figure, (1) beam Otsuk pulse, (2) t-tl
The bit digital value data input to the al path, (
3) is input register, (4) is input register output data, (5) is data shift register, (6) ri data shift register output data, (7) is comparator, (8) is A
ND gate, (9) is a tri-state buffer, (
10) is maximum value stretch data, (11) is an AND gate, (12) is a data valid storage register, and (13) is a data valid signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An input register that inputs k bits of digital value data each time a clock pulse is applied, n data shift registers that input and shift data from the input registers each time a clock pulse is applied, and data in the input register and n n-1 comparators that perform magnitude comparisons with the data in n-1 registers, excluding the register with the oldest data among the data shift registers, and the outputs of the comparators and data valid storage registers to be described later. a logical operation circuit that performs a logical operation between the n-1 data shift registers and determines the significance of the data stored in the n-1 data shift registers;
an n-1 bit data valid storage register that inputs the result of a logical operation and stores the significance of n-1 pieces of data excluding the most recently inputted data among n data shift registers; and a data valid storage register. The maximum value is equipped with a logic operation circuit that determines the register with the maximum value among n data shift registers based on the signal output from the register, and a tri-state buffer that opens the gate and outputs the maximum value based on the result. stretch circuit.